CN111916456B

CN111916456B - Scalable logic gate non-volatile memory array and method of manufacturing the same

Info

Publication number: CN111916456B
Application number: CN201910382991.7A
Authority: CN
Inventors: 王立中
Original assignee: Xinlijia Integrated Circuit Hangzhou Co ltd
Current assignee: Xinlijia Integrated Circuit Hangzhou Co ltd
Priority date: 2019-05-09
Filing date: 2019-05-09
Publication date: 2024-04-30
Anticipated expiration: 2039-05-09
Also published as: CN111916456A

Abstract

The invention provides a scalable logic gate non-volatile memory NOR array and its manufacturing method, which is manufactured by standard complementary metal oxide semiconductor technology, and is applied as a solution of digital circuit embedded flash memory. To substantially reduce the area of a memory array fabricated by conventional processes, the gate cap in the memory region is removed using the topology regularity and self-aligned etch process steps of the memory cells in the array. The invention can be used to achieve a minimum cell area of 12F ² for a NOR flash array of a scalable logic gate non-volatile memory without sacrificing the yield of the memory array, where F is a minimum feature size for a particular CMOS logic technology generation.

Description

Scalable logic gate non-volatile memory array and method of manufacturing the same

Technical Field

The present invention relates to a technology generation (technology node) scalable semiconductor non-volatile memory array fabricated using conventional complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) logic process technology. In particular, a plurality of memory cells (cells) of a flash array may be scaled down to a minimum cell area of 12F ², where F represents the minimum feature size (feature size) of a particular CMOS logic technology generation.

Background

CMOS processes have become the most popular process for Application SPECIFIC INTEGRATED Circuits (ASICs). An asic includes specific functions of the device or system on a single integrated circuit (INTEGRATED CIRCUIT) or chip (chip). In the digital age, almost all electronic components or devices are controlled and operated by integrated circuit chips. Depending on the application, the integrated circuit or chip must be flexible to modify the specific function or configuration. For example, a programmable nonvolatile memory is required to store programming instructions (programmed instruction) when initializing programming (initial programming) and configuring a microprocessor. The non-volatile memory retains stored digital information even when power to the electronic system is turned off (off). When the electronic system is turned on, the stored digital information or instructions are retrieved recall. In addition, during development, the programming instructions and the starting data can be allowed to be changed at any time without changing hardware. The above-mentioned requirements are fulfilled by an EEPROM (ELECTRICAL ERASABLE PROGRAMMABLE READ-only memory) device (device). EEPROM is a semiconductor nonvolatile memory that is erasable and programmed by applying voltages to the electrodes of its memory elements. The operation of an EEPROM is typically on a cell-by-cell basis. Therefore, the EEPROM has a metal-oxide-semiconductor FIELD EFFECT transistor (MOSFET) device to access the memory cell. Generally, an EEPROM is a memory cell (access transistor+storage transistor (storing transistor)) that includes at least two transistors (2T). An eeprom (ELECTRICAL PROGRAMMABLE READ-only memory) is another semiconductor nonvolatile memory that contains only a single storage transistor (1T) without an access transistor. However, the eeprom requires Ultraviolet (UV) light (Ultra-Violate) to perform an erase operation. In a later development, EPROM (1T) array based EEPROMs have been specifically configured in flash EEPROMs that are capable of global (global) electronic erasure, i.e., page-by-page or sector-by-sector (sector) electronic erasure.

In conventional EEPROM processes, the control gate of an EEPROM memory cell is typically formed over an isolated conductive layer, such as a floating gate or a dielectric stack (stack of DIELECTRIC LAYERS) such as silicon oxide-nitride-oxide (ONO) for storing charge, both of which are located over the silicon channel surface (silicon channel surface). Compared to conventional CMOS processes, which are widely used in most ASIC fabrication, only a single conductive gate layer (conducting GATE LAYER) is used as the control gate for the logic MOSFET device. To fabricate the additional charge storage layer, the EEPROM process requires more process steps such as film deposition (film deposition), etching (etching), and patterning (patterning) lithography (photolithography). These additional process steps result in increased manufacturing costs, increased process complexity, impact yield, and longer process man-hours. Therefore, it is a challenge in the industry to use a process compatible with the CMOS baseline (baseline) process to fabricate an EEPROM without an additional storage layer for an embedded EEPROM ASIC.

The first single-poly (single-poly) floating gate EEPROM cell fabricated in conventional CMOS processes was proposed by Ohsaki et al and published in 1994 journal IEEE Journal of Solid-state, vol.29, no.3, mar.1994, pp.311-316. As shown in fig. 1a, the source (source), drain (drain) and N-well electrode (electrode) of the P-type MOSFET 11 in CMOS are all connected together to form the control gate of the EEPROM device 10, while the gate of CMOS is not connected to the external electrode to form the floating gate of the EEPROM device 10 to store charges. The source, drain and base electrodes of the N-type MOSFET12 in CMOS form the source, drain and base electrodes, respectively, of the EEPROM element 10. However, the array structure of the original device shown in FIG. 1b has the disadvantages of program/read disturb (disturbance) and insufficient endurance (poor endurance cycling). To address the severe program/read disturb and insufficient endurance, we have utilized cell pairing (PAIRED CELL) or staggered cell (STAGGERED CELL) configurations to construct scalable gate logic semiconductor nonvolatile memory (scalable gate logic NVM, SGLNVM) arrays, which are disclosed in the patent literature of the people's republic patent publication No. CN104303310B (the contents of which are incorporated herein by reference in their entirety). By applying this configuration of flash memory array, not only performance problems are solved, but SGLNVM arrays manufactured using the wafer foundry standard 40 nanometer (nm) CMOS logic technology generation are also scaled down to 32 nm gate length, shown in the scanning electron microscope (scanning electron microscopy, SEM) photograph of fig. 2.

Applicants have not only demonstrated scalability of SGLNVM arrays in three different standard CMOS logic process generations (110 nm, 55 nm, and 40 nm), but also reduced the memory cell area of each CMOS logic process generation to a minimum cell area to accommodate higher memory density and lower chip area cost. Because the layout of logic gates and flip-flops in the digital circuit bank (library) of ASIC chips is less "regular" than the layout of logic gates and flip-flops in the digital circuit bank (library) of the memory array, topology layout rules (topological layout rule) in CMOS logic processes are typically set to be relaxed to allow process tolerance (tolerance) for variations in the shape and orientation of the various MOSFET devices. For example, the width and length of the MOS devices used as the gates, buffers and inverters of different logic functions in the digital circuit bank are different to minimize the gate-level (gate-stage) delay for fast logic operation, and the rule of the minimum cell area of the memory devices is repeatedly applied to form the memory array.

In the fabrication of CMOS logic, a gate end cap (gate extension beyond the width (ACTIVE AREA WIDTH) of the active area of a MOSFET device) is required to establish a process margin (process margin) for the yield (yield) of the MOSFET device. This extended end cap is then applied to compensate for process imperfections, such as: the etch microloading (microloading) effect, the photolithographic proximity (proximity) effect, and misalignment (misalignment). As shown in fig. 3, the extended gate y (cap) of the MOSFET device is used to compensate for misalignment deltay between the active area mask (mask) and the gate mask. The rules (rule) for gate cap are defined by mask drawing rules for CMOS logic process technology, depending on the wafer fabrication process capability. Because the rules of gate cap are quite long and cannot be scaled in CMOS logic process technology generations, the area of the NVM array is increased when the gate cap is applied to the digital circuit library due to the relationship of the length of the extended gate cap and the required gate spacing.

As disclosed in the patent document CN104303310B, the scalable gate logic nonvolatile memory (SGLNVM) device is fabricated in standard CMOS processes. The gate length of the floating gate of the SGLNVM cell is defined according to the minimum gate length of a logic technology generation, which is the feature size of the technology generation, denoted by "F". The minimum gate width of a MOSFET device is typically defined by the minimum active area width of the process technology generation. Thus, the minimum floating gate length and minimum active region width of the SGLNVM cell form the minimum channel (channel) length and width of the floating gate MOSFET. A floating gate having a minimum gate length extends in a silicon active region to form a capacitive coupling between the floating gate and a control gate embedded in a silicon substrate (well), wherein the floating gate and the control gate are electrically separated by an insulating dielectric layer 419/519/619/719. The embedded control gate 420/520/620/720 is formed of a shallow semiconductor, and the type of the shallow semiconductor is opposite to the type of the silicon substrate (well). The shallow control gate semiconductor is formed by using an N-type ion implantation (ion implantation) to a P-type substrate or a P-type ion implantation to an N-type well, such that the junction 408/508/608/708 is located at a depth above the bottom of the field isolation 411/511/611/711. In conventional CMOS processes, the same masking layer MASKING LAYER may be used to incorporate the ion implants of the N-type SGLNVM devices into the threshold voltage (threshold voltage) ion implants of the P-type MOSFETs. In conventional CMOS processes, the same masking layer may be used to implant P-type SGLNVM devices in combination with the threshold voltage ion implants for N-type MOSFETs.

As shown in fig. 4d, the SGLNVM cells are configured as an NOR-type flash memory cell array, wherein each SGLNVM cell pair P _P shares a source electrode connected to a common line (common ground line), and two drains thereof are connected to two different bit lines (bit lines). The two NOR SGLNVM cell pairs (pairs) are physically separated and electrically isolated by field oxide 411/511 or an opposite type of semiconductor located under the dummy floating gate 605/705.

In the examples of fig. 4 a-4 d and 5 a-5 d (fig. 8 a-8 d and 9 a-9 d corresponding to the chinese patent publication number CN 104303310B), the N-type and P-type NOR SGLNVM cell pairs in the flash memory cell array are separated by a plurality of field oxides 411 and 511, respectively. Fig. 4a is a top view of an array of field oxide separated N-type NORSGLNVM flash memory cells, as disclosed in the japanese patent publication No. CN 104303310B. Fig. 4B and 4c are cross-sectional views of the tangent line "A1" and the tangent line "B1" in fig. 4a, respectively. FIG. 4d is a schematic diagram showing the architecture of the N-type SGLNVM flash memory cell array of MXn in FIG. 4 a. Fig. 5a is a top view of a P-type NOR SGLNVM flash memory cell array separated by field oxide, which is disclosed in the patent publication CN104303310B of the people's republic of China. Fig. 5B and 5c are cross-sectional views of the line "A2" and the line "B2" in fig. 5a, respectively. FIG. 5d is a schematic diagram showing the architecture of the m n P-type SGLNVM flash memory cell array of FIG. 5a.

The two rows (row) of active regions 401/501 define two word line regions and a row of rectangular active regions 402/502 define source/drain electrode regions, respectively, all processed with shallow trench isolation (shallow trench isolation, STI) modules (modules) in conventional CMOS processes. The width of the active regions 402/502 is preferably equal to the minimum width of the process capability to minimize the device size. As in conventional CMOS processes, a series of N-well and P-well ion implants are performed. Region 403 is an open area to receive a shallow N-type ion implant such that the depth of shallow N/P junction 408 formed in P-type substrate 412 is above the bottom of STI 411; region 503 is an open area to receive shallow P-type ion implantation such that the depth of shallow P/N junction 508 formed in N-well 512 is above the bottom of STI 511. Depending on the detailed CMOS process and the resistance requirements of the word line (control gate 420/520 connecting the non-volatile memory cells) in the array, the N-type ion implant may be incorporated into the threshold voltage and punch-through (P-through) ion implant of the P-type MOSFET in a conventional CMOS process. After completion of the well ion implants for both P-type and N-type MOSFETs, gate oxides of different thicknesses including tunnel oxide layers 409/509 and insulating dielectric layers 419/519 are grown, followed by deposition (deposition) of a polysilicon film (poly-CRYSTALLINE SILICON FILM) and patterning and etching to form the floating gates 404/504 in the array as well as the gates of other general MOSFETs. The width of the floating gates 404/504 is preferably equal to the minimum width of the process capability to minimize the device size. The floating gate 404/504 overlaps portions of the active region 402/502 to form the minimum channel (415/515) length and width of the floating gate MOSFET. Each two floating gate MOSFETs are paired and share the same source electrode 414/514. The field oxide 411/511 extends in a direction parallel to the bit lines and is formed between two adjacent active regions 402/502 to separate two adjacent drain electrodes 413/513, as shown in fig. 4c and 5 c. Lightly doped drain (lightly doped drain, LDD) and pocket ion implantation are then performed prior to formation of silicon nitride spacers (NITRIDE SPACER) 410/510. After receiving high dose N-type source/drain ion implantation, thermal activation (thermal activation) and metal oxide (salicide) formation, the front-end process (front-end process) of separating the N-type SGLNVM cell array of the plurality of NOR SGLNVM cell pairs with the field oxide 411 is completed. After receiving the high dose P-type source/drain ion implantation, thermal activation and metal oxide formation, the front-end process of separating the P-type SGLNVM cell array of the plurality of NOR SGLNVM cell pairs with the field oxide 511 is completed. The source electrode 414/514 and the drain electrode 413/513 of the SGLNVM element are connected to the metal line (METAL LINES) 407/507 via a contact 405/505, respectively. An N-type SGLNVM flash memory cell array configured by a plurality of NOR pairs separated by field oxide 411 in fig. 4a, with corresponding word lines (W _i), common source lines (G), and bit lines (B _j) are shown in the schematic diagram of fig. 4 d. The P-type SGLNVM flash memory cell array of fig. 5a, which is configured by a plurality of NOR pairs separated by field oxide 511, has the corresponding word line (W _i), common source line (V), and bit line (B _j) shown in the schematic diagram of fig. 5 d.

In the example of fig. 6 a-6 d and 7 a-7 d (fig. 2 a-2 d and 5 a-5 d corresponding to the chinese patent publication number CN 104303310B), a plurality of N-type and P-type NOR SGLNVM cell element pairs in a flash memory array are separated by a plurality of dummy floating gates 605 and 705, respectively. Fig. 6a is a top view of an N-type NOR SGLNVM flash memory cell array, which is disclosed in the patent document CN104303310B of the people's republic of China. Fig. 6B and 6c are cross-sectional views of the line "A3" and the line "B3" of fig. 6a, respectively. FIG. 6d is a schematic diagram showing the architecture of the N-type SGLNVM flash memory cell array of the mxn type in FIG. 6 a. Fig. 7a is a top view of a P-type NOR SGLNVM flash memory cell array separated by field oxide, which is disclosed in the patent publication CN104303310B of the people's republic of China. Fig. 7B and 7c are cross-sectional views of the line "A4" and the line "B4" in fig. 7a, respectively. FIG. 7d is a schematic diagram showing the architecture of the mXn P-type SGLNVM flash memory cell array of FIG. 7 a.

Three active regions (601/602/601; 701/702/701) are formed in three rows, defining word line regions, source/drain electrode regions and word line regions, respectively, fabricated with shallow trench isolation modules in conventional CMOS processes. The width of the active regions 602/702 is preferably equal to the minimum width of the process capability to minimize device size. As in conventional CMOS processes, a series of N-well and P-well ion implants are performed. Region 603 is an open region for receiving shallow N-type ion implantation such that the depth of shallow N/P junction 608 formed in P-type substrate 612 is above the bottom of STI 611; region 703 is an open region for receiving shallow P-type ion implantation such that the depth of shallow P/N junction 708 formed in N-well 712 is above the bottom of STI 711. Depending on the detailed CMOS process and the resistance requirements of the word lines (connecting the control gates 620/720 of the non-volatile memory cells) in the array, the N-type ion implants may be incorporated into the threshold voltage and the penetrating ion implants of the P-type MOSFETs in conventional CMOS processes. After well ion implantation of both P-type and N-type MOSFETs is completed, gate oxides of different thicknesses including tunnel oxide layers 609/709 and insulating dielectric layers 619/719 are grown, then a polysilicon film is deposited and patterned and etched to form floating gates 604/605/704/705 in the array, as well as gates of other general MOSFETs. The width of the floating gate 604/704 is preferably equal to the minimum width of the process capability to minimize the device size. The floating gate 604/704 partially overlaps (overlap) the active region 602/702 to form the minimum channel (615/715) length and width of the floating gate MOSFET. Each two floating gate MOSFETs are paired and share the same source electrode 614/714. The dummy floating gate 605 partially overlaps the active region 602 to form a P-channel stop (P-channel stop) region 616 separating two adjacent N-drain electrodes 613; the dummy floating gate 705 overlaps the active region 702 to form an N-channel stop region 716 separating two adjacent P-drain electrodes 713. Lightly doped drain and pocket ion implants are then performed prior to the formation of the silicon nitride spacers 610/710. After receiving high dose N-type source/drain electrode ion implantation, thermal activation and metal oxide formation, the front-end process of the N-type SGLNVM cell array is completed; lightly doped drain and pocket ion implants are performed prior to the formation of silicon nitride spacers 710. After receiving the high dose P-type source/drain electrode ion implantation, thermal activation and metal oxide formation, the front-end process of the P-type SGLNVM cell array is completed. The source electrode 614/714 and drain electrode 613/713 of the SGLNVM device are connected to metal line 607/707 via contacts 606/706, respectively. The N-type SGLNVM flash memory cell array of fig. 6a, with corresponding word lines, common source lines, and bit lines, is shown in the mxn array schematic of fig. 6 d. The P-type SGLNVM flash memory cell array of fig. 7a, with corresponding word lines, common source lines, and bit lines, is shown in the mxn array schematic of fig. 7 d.

Note that with respect to NOR SGLNVM flash memory arrays disclosed in the japanese patent publication No. CN104303310B, (1) floating gate 404/504/604/704 has end caps; (2) A plurality of field trench isolation regions and a plurality of floating gates are individually formed in the array region by the STI module and the gate formation process module of the CMOS logic process, respectively.

Disclosure of Invention

The embodiment of the invention provides a nonvolatile memory cell array and a method for manufacturing the nonvolatile memory cell array, so that the cell area is reduced, and the cost is saved.

In one aspect of the present invention, there is provided a nonvolatile memory cell array comprising:

a plurality of source lines;

A plurality of bit lines; and

A plurality of non-volatile memory cells arranged in a circuit configuration having rows and columns on a substrate, each of the non-volatile memory cells comprising a source region, a drain region, a floating gate, a control gate region and a channel region, the non-volatile memory cells in the same row being divided into a plurality of cell pairs such that each of the cell pairs comprises a common source region and two drain regions, the common source region being connected to a common source line, the two drain regions being connected to two different bit lines;

Wherein the floating gate is formed above the channel region and the control gate region and insulated from the channel region and the control gate region, and extends in a column direction from the channel region to the control gate region;

wherein the gate width of the floating gate is aligned with the boundary of the channel region and the control gate region without protruding from the channel region and the control gate region;

wherein the gate length of the floating gate is limited to a minimum feature size of a process technology generation; and

Wherein the source region, the drain region, and the control gate region have the same electrical conductivity type.

In another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory cell array including a plurality of nonvolatile memory cells arranged in a circuit configuration having rows and columns on a substrate, each nonvolatile memory cell including a source region, a drain region, a floating gate, a control gate region and a channel region, the nonvolatile memory cells located in the same row being divided into a plurality of cell pairs such that each of the cell pairs includes a common source region and two drain regions, a plurality of source lines, the common source region being connected to a common source line, the two drain regions being connected to two different bit lines, the method comprising the steps of:

A plurality of active area strips and a plurality of rows of active area rectangles are alternately defined on the substrate through a shallow trench isolation module, and extend along the row direction;

performing a first ion implantation to the active region to form the control gate region;

Forming an oxide layer on the active region strip and the active region rectangle;

Depositing and etching a polysilicon film on the active region strips and the active region rectangles to form a plurality of polysilicon strips extending in the column direction;

Depositing a mask on the substrate, wherein the mask comprises a plurality of barrier strips extending in a row direction; and

Etching through the mask, the polysilicon strips and the oxide layer to the substrate to form a plurality of trenches extending in a row direction, so that each active region strip and each active region rectangle are divided into two halves, and the polysilicon strips are divided to form the floating gate;

Wherein the gate width of the floating gate of each nonvolatile memory cell is aligned with the boundaries of its channel region and control gate region without protruding from its channel region and control gate region.

defining a plurality of first active area bands and a plurality of second active area bands on the substrate alternately by a shallow trench isolation module, extending in a row direction;

Performing a first ion implantation to the first active region to form the control gate region;

forming an oxide layer on the first active region band and the second active region band;

depositing and etching a polysilicon film on the first active region band and the second active region band to form a plurality of first polysilicon bands and a plurality of second polysilicon bands, extending in the column direction;

depositing a mask on the substrate, wherein the mask comprises a plurality of first barrier strips extending in a row direction and a plurality of second barrier strips extending in a column direction; and

Etching through the mask, the first and the plurality of second polysilicon strips and the oxide layer to the substrate to form a plurality of trenches extending in the row direction so as to divide each first active area strip and drain regions and source regions paired by any two adjacent row units;

Wherein the width of the floating gate of each nonvolatile memory cell is aligned with the boundaries of its channel region and control gate region without protruding from its channel region and control gate region.

By using the invention, the unit area can be reduced, and the cost can be saved.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1a is a cross-sectional view of an original single polysilicon floating gate nonvolatile memory device.

FIG. 1b is a schematic diagram of a single polysilicon floating gate nonvolatile memory cell array as disclosed in Ohsaki et al.

Fig. 2 shows a scanning electron micrograph of an SGLNVM device with a 32 nm gate length.

Fig. 3 shows that the extended gate cap length can address MOSFET device failure due to misalignment between the active area mask and the gate mask.

Fig. 4a shows a top view of an N-SGLNVM flash memory array disclosed in the patent publication CN104303310B of the people's republic of China.

Fig. 4b shows a cross-section of the line "A1" in fig. 4 a.

Fig. 4c shows a cross-section of the line "B1" in fig. 4 a.

FIG. 4d shows a schematic diagram of the N-type SGLNVM flash memory array with m N dimensions of FIG. 4 a.

Fig. 5a shows a top view of the P-type SGLNVM flash memory array disclosed in the patent publication CN104303310B of the people's republic of China.

Fig. 5b shows a cross-section of line "A2" in fig. 5 a.

Fig. 5c shows a cross-section of the line "B2" in fig. 5 a.

FIG. 5d shows a schematic diagram of the P-type SGLNVM flash memory array with m n dimensions of FIG. 5 a.

Fig. 6a shows a top view of an N-SGLNVM flash memory array disclosed in the patent publication No. CN104303310B of the people's republic of China.

Fig. 6b shows a cross-section of line "A3" in fig. 6 a.

Fig. 6c shows a cross-section of the line "B3" in fig. 6 a.

FIG. 6d shows a schematic diagram of the N-type SGLNVM flash memory array with m N dimensions of FIG. 6 a.

Fig. 7a shows a top view of the P-type SGLNVM flash memory array disclosed in the patent publication No. CN104303310B of the people's republic of China.

Fig. 7b shows a cross-section of line "A4" in fig. 7 a.

Fig. 7c shows a cross-section of line "B4" in fig. 7 a.

FIG. 7d is a schematic diagram of the P-type SGLNVM flash memory array with m n dimensions of FIG. 7 a.

Fig. 8a shows a top view of a conventional SGLNVM cell array, wherein each SGLNVM cell has a gate cap extension of 2F and a cell area of 24F ².

Fig. 8b shows a top view of an array of LGNVM cells of the present invention, where each LGNVM cell has no gate cap and has a cell area of 12F ².

Fig. 9a shows the active area pattern in the memory array after the STI process, according to the first embodiment of the present invention.

Fig. 9b shows the active area and gate pattern in the memory array after the gate formation process, in accordance with the first embodiment of the present invention.

Fig. 9c shows an additional mask pattern in the memory array after the self-aligned etch process, in accordance with the first embodiment of the present invention.

Fig. 9d is a top view of a LGNVM NOR-type flash memory array according to a first embodiment of the present invention, shown after a first metal process.

Fig. 10a shows the active area pattern in the memory array after the STI process, according to a second embodiment of the present invention.

Fig. 10b shows the active area and gate pattern in the memory array after the gate formation process, in accordance with the second embodiment of the present invention.

Fig. 10c is a diagram illustrating an additional mask pattern in the memory array after a self-aligned etch process, in accordance with a second embodiment of the present invention.

Fig. 10d is a top view of a LGNVM NOR-type flash memory array according to a second embodiment of the present invention, shown after a first metal process.

10. EEPROM with a memory cell having a plurality of memory cells and a plurality of memory cells

11 P-type metal oxide half field effect transistor

12 N-type metal oxide half field effect transistor

401. 402, 501, 502, 601, 602, 701, 702 Active regions

403. 503, 603, 703 Open area

404. 504, 604, 704, 812, 822 Floating gate

605. 705 Virtual floating gate

405. 505, 606, 706 Contacts

407. 507, 607, 707 Metal lines

408. 608 N/p junction

508. 708 P/n junction

409. 509, 609, 709 Tunneling oxide layers

410. 510, 610, 710 Silicon nitride spacers

411. 511, 611, 711 Field oxide (shallow trench isolation)

412. 612P type substrate

413. 513, 614, 714, 814, 815, 824, 825 Drain electrode

414. 514, 613, 713, 816, 826 Source electrodes

415. 515, 615, 715, 813, 823 Channels

616. 716 Blocking area

419. 519, 619, 719 Insulating dielectric layer

420. 520, 620, 720, 811, 821 Control gates

512. 712N type well

810 SGLNVM unit pairing

820 LGNVM unit pairing

111. 112, 911 Active area band

912. Rectangular active region

121. 921 Polysilicon strip

122. Virtual polysilicon strip

130. Barrier tape

131. Open rectangle

Detailed Description

The following detailed description is by way of example only and is not limiting. It is to be understood that other embodiments may be utilized and that structural changes or modifications may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. It should be understood by those skilled in the art that the embodiments of the methods and schematic illustrations in this specification are illustrative only and not limiting. Those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be utilized and still fall within the scope of the present invention as claimed.

Without sacrificing device yield, the invention applies the principles of topology regularity of memory cells and a self-aligned (self-aligned) etching process step to reduce the cell area (unit cell size) of the NOR-flash memory array of the invention by removing the gate cap in the memory array, where F represents the minimum feature size of a particular CMOS logic technology generation. Since the LGNVM NOR-type flash memory array of the present invention omits a storage stack (stack) (floating gate stack or charge-trap stack) which saves additional process costs and has a memory area compatible with the cell area of 9-10F ² of conventional stacked NOR-type flash memory arrays, the LGNVMNOR-type flash memory array of the present invention is the most cost-effective embedded (embedded) flash memory solution for CMOS digital circuits. Furthermore, because conventional NOR-type flash memory arrays have reached a gate length scaling barrier of less than 110 nanometers generation due to device penetration problems caused by conventional Channel Hot Electron Injection (CHEI) programming, the scalable LGNVM NOR-type flash memory arrays fabricated in conventional CMOS processes of the present invention are unique embedded flash memory solutions in digital circuits fabricated using advanced CMOS logic process technology generation (technology generation of less than 110 nanometers).

To achieve the goal of reducing the cell area (50% smaller area), fig. 8a shows a top view of a conventional SGLNVM cell array (disclosed in the japanese patent publication No. CN 104303310B), wherein each SGLNVM cell has a gate cap extension of 2F and a cell area of 24F ²; fig. 8b shows a top view of an array of LGNVM cells of the present invention, where each LGNVM cell has no gate cap and has a cell area of 12F 2. In fig. 8a, the configuration of a conventional SGLNVM unit pairing 810 is as follows: the control gates 811 of a column are connected together to form a horizontal word line; two floating gates 812 storing charges extend from the overlapped control gate region and the device channel region 813 by a length of 2F; the two drain electrodes 814 and 815 are connected to two vertical metal bit lines (not shown); the common source electrode 816 is connected to a common vertical metal source line (not shown). In the SGLNVM array of fig. 8a, STI is used to separate the SGLNVM cell pairs 810 along the x-axis direction; along the y-axis, two gate cap lengths and a gate spacing (spacing) are used to separate cell boundaries 831.

In fig. 8b, the configuration of the LGNVM unit pair 820 of the present invention is as follows: the control gates 821 of a column are connected together to form a horizontal word line; two charge-storing floating gates 822 do not extend any length from the overlapping control gate region and device channel region 823; the two drain electrodes 824 and 825 are connected to two vertical metal bit lines (not shown); the common source electrode 826 is connected to a common vertical metal source line (not shown). In the LGNVM array of fig. 8b, STI is used to separate SGLNVM cell pairs 820 along the x-axis direction; along the y-axis, the cell boundary 832 is separated with a minimum spacing between the two active regions.

To ensure seamless alignment of the widths of the floating gate and the active region, a self-aligned etch process is used to form zero cap floating gate and field isolation trenches in the cell boundary region 832 in the y-axis direction of LGNVM arrays, as shown in fig. 8 b. Compared to the conventional process of the cell array of fig. 8aSGLNVM, in which the STI process module and the gate formation process module are used to individually form the field isolation trenches and the floating gates with end caps in the array region, the array of fig. 8bLGNVM uses the additional self-aligned etching process to form the field isolation trenches and the floating gates with zero caps to separate the memory cells along the y-axis direction of the LGNVM array. The self-aligned etch process module is set to etch a depth through the gate material and tunnel oxide/coupling dielectric layer to the silicon substrate as a y-axis directional cell boundary trench.

In one embodiment of the present invention, field oxide isolation regions (corresponding to FOX 411/511 of FIG. 4 c/5 c) formed with STI process modules are used to separate the LGNVM cell pairs in the memory array along the x-axis direction. In this embodiment, a self-aligned etching process module is applied to form a plurality of floating gates with zero caps and a plurality of field isolation trenches at the cell boundary region in the y-axis direction of LGNVM arrays; except for the above, the remaining processes and the remaining schematic diagrams of the LGNVM array of the present invention are identical to those of fig. 4a to 4d and fig. 5a to 5d, and the description of the processes and the schematic diagrams of the identical parts will not be repeated herein unless otherwise specifically indicated in the present specification. CMOS logic process technology typically begins with well ion implantation that forms a MOSFET device body, followed by STI process modules. Since the common STI process module in CMOS logic process technology is well known in the art, the STI process module is not described in detail herein. A layout diagram (topologic view) of the LGNVM array (including a plurality of active region strips and a plurality of active region rectangles) after the STI module process is completed is shown in fig. 9 a. To make it easier to view the LGNVM array, the outline of the memory cell boundary of the LGNVM cell pair is depicted in the following figures (outline). In fig. 9a, each active region 911 includes two control gate regions (upper and lower word lines) that are not separated by the STI process; each active region rectangle 912 contains the source/drain active regions (upper and lower) of two LGNVM cells, which are not separated by the STI process. After the STI process module, ion implantation of the MOSFET device threshold voltage and LGNVM control gate (corresponding to control gate 420/520 of fig. 4 b/5 b) is performed. Thereafter, gate oxides (corresponding to tunnel oxide 409/509 and isolation dielectric 419/519 of fig. 4 b/5 b) of the different MOSFET devices are formed. After the step of forming the gate oxide, the MOSFET device gate is formed using a gate formation process module that includes a polysilicon film deposited and etched to form the MOSFET device gate.

After the device gate formation step, a plurality of poly floating gates of LGNVM arrays are shown in fig. 9 b. The parallel and vertical poly strips 921 have not been separated to act as floating gates for individual memory cells in the LGNVM array region. The memory cells along the y-axis of the array are separated by protecting the device pattern from the etching reaction of the self-aligned etching process step using a mask comprising a plurality of blocking regions, wherein the blocking regions comprise the pattern of the memory array of fig. 9c and the pattern of the outer full area of the memory array. The self-aligned etch process is configured to remove the gate material/oxide/silicon substrate. At the end of the self-aligned etch process step, the silicon substrate is etched to a depth deeper than the junction of the MOSFET device source/drain electrodes and the LGNVM cell control gate so that the trench 930 on the cell boundary in the y-axis direction of the memory array separates/partitions the source/drain electrode 912 (corresponding to source/drain electrode 413/414/513/514 of fig. 4 c/5 c) and the electrical connection of the active area strap 911. And after the front-end process is finished, continuing the back-end metal process. In the first inter-layer-dielectrics of the back-end-of-line process, the trench 930 in the y-axis direction of the memory array is filled with a dielectric material. FIG. 9d shows a top view of the memory array with the first metal bit lines and the common source metal lines after the contact and first metal process is completed.

In another embodiment of the present invention, field stop isolation regions (corresponding to the dummy floating gates 605/705 of FIGS. 6 a/6 c/7 a/7 c) are applied to separate the LGNVM cell pairs along the x-axis direction of the memory array. In this embodiment, a self-aligned etching process is used to simultaneously form the floating gate and the field isolation trench of the zero cap in the cell boundary region in the y-axis direction of LGNVM arrays; except for this, the remaining processes and the remaining schematic diagrams of LGNVM arrays are identical to the descriptions of fig. 6 a-6 d and fig. 7 a-7 d, and the descriptions of the processes and schematic diagrams of the same parts are not repeated herein unless otherwise specifically indicated in the present specification. CMOS logic process technology typically begins with well ion implantation to form the MOSFET device body, followed by the STI process. A layout of a plurality of parallel active area strips in LGNVM arrays after the STI module process is completed is shown in fig. 10 a. To make it easier to view the LGNVM array, the outline of the memory cell boundary for LGNVM cell pairs is depicted in the following figures. Each active region 111 includes two control gate regions (upper and lower word lines) that are not separated by the STI process; each active region stripe 112 includes source/drain active regions (upper and lower cells) of two LGNVM cells, which are not separated by the STI process. After the STI process, ion implantation of the MOSFET device threshold voltage and LGNVM control gates (corresponding to control gates 620/720 of fig. 6 b/7 b) is performed. Thereafter, gate oxides (corresponding to tunnel oxide 609/709 and isolation dielectric 619/719 of fig. 6 b/7 b) are formed for the different MOSFET devices. After the step of forming the gate oxide, the MOSFET device gate is formed using a gate formation process module that includes a polysilicon film deposited and etched to form the MOSFET device gate.

After the element gate formation step, the LGNVM array forms a plurality of parallel and vertical polysilicon strips. As shown in fig. 10b, the parallel and vertical poly strips 121 have not been separated to serve as floating gates for individual memory cells (corresponding to floating gates 604/704 of fig. 6c and 7 c), while a plurality of parallel and vertical poly strips 122 are used as dummy poly strips to isolate LGNVM cell pairs in the x-axis direction of the LGNVM array. The gate length of the LGNVM cell pair floating gate and the length of the dummy polysilicon strip are limited by the minimum gate length of a logic process technology generation. Note that the channel region under the dummy polysilicon strips 122, which serves as a field stop region, has opposite semiconductor types that electrically separate the two drains of the LGNVM cell pairs in the x-axis direction of the memory array.

The memory cells along the y-axis of the array are separated by protecting the device pattern from the etching reaction of the self-aligned etching process step using a mask comprising a plurality of blocking regions comprising the pattern of a plurality of blocking strips 130 of the memory array (comprising a plurality of open rectangles 131 within the blocking strips 130 as shown in fig. 10 c) and the pattern of all areas outside the memory array. The self-aligned etch process is configured to remove the gate material/oxide/silicon substrate. At the end of the self-aligned etch process step, the silicon substrate is etched to a depth deeper than the junction of the MOSFET device source/drain electrodes and the LGNVM cell control gate so that the trenches on the cell boundary in the y-axis direction of the memory array separate/partition the source/drain electrodes 112 (corresponding to drain electrodes 613/713 and source electrodes 614/714 of fig. 6 c/7 c) and the electrical connections of the active area stripe 111. And after the front-end process is finished, continuing the back-end metal process. In the first interlayer dielectric process, the trenches in the y-axis direction of the memory array are filled with a dielectric material. FIG. 10d shows a top view of the memory array with metal bit lines and common source metal lines after the contact and first metal process is completed.

The preferred embodiments provided above are merely illustrative of the present invention and are not intended to limit the invention to a specific type or exemplary embodiment. Accordingly, the description is to be regarded as illustrative in nature, and not as restrictive. Obviously, various modifications or variations of the geometry (including length and width), gate material or tunnel dielectric layer will be apparent to those skilled in the art. The foregoing description of the preferred embodiments is provided to effectively explain the principles of the present invention and its best mode contemplated for practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. The scope of the invention is defined by the claims and their equivalents (equivalents), wherein all terms (term) are intended to be given the broadest reasonable meaning unless otherwise specifically indicated. Thus, the terms "present invention" and the like do not limit the scope of the claimed subject matter to a particular embodiment, and any references to a particular preferred embodiment of the present invention are not intended to limit the present invention, and no such limitation is to be inferred. The present invention is to be defined solely by the scope and spirit of the appended claims. The abstract is provided to enable a searcher to quickly ascertain the subject matter of the technical disclosure, and is not intended to interpret or limit the scope or meaning of the claims, from any patent approved by the specification. Any advantages and benefits may not apply to all embodiments of the present invention. It should be understood that various modifications and changes may be made by those skilled in the art, which fall within the scope of the invention as defined in the appended claims. Furthermore, no element or component in the present specification is intended to be dedicated to the public regardless of whether the element or component is recited in the claims.

Claims

1. An array of non-volatile memory cells, comprising:

a plurality of source lines;

A plurality of bit lines; and

Wherein the source region, the drain region, and the control gate region have the same electrical conductivity type;

wherein, further comprising:

the isolation regions extend in the column direction, wherein each isolation region is formed between two drain regions of unit pairs of any two adjacent columns in each row;

The isolation region is a plurality of second isolation trenches extending in the column direction, wherein the source region and the drain region of the pair of cells of any two adjacent rows are divided into two halves by a third isolation trench extending in the row direction.

2. The array of claim 1, wherein the control gate regions of the non-volatile memory cells in each column form a word line, and any two word lines are separated by a first isolation trench extending in the column direction.

3. The array of claim 1, wherein the control gate region is of an opposite electrical conductivity type than the substrate or a corresponding well.

4. The array of claim 1, wherein the control gate region is embedded in a silicon substrate.

5. The array of claim 1, wherein the control gate and the floating gate are electrically isolated by a dielectric layer, and wherein a capacitive coupling is created between the control gate region and the floating gate through the dielectric layer.

6. The array of claim 1 wherein a minimum cell area of each nonvolatile memory cell is limited to 12F ², where F is a minimum feature size of the process technology generation.

7. A method of manufacturing an array of non-volatile memory cells, the array of non-volatile memory cells comprising a plurality of non-volatile memory cells arranged in a row and column circuit configuration on a substrate, each non-volatile memory cell comprising a source region, a drain region, a floating gate, a control gate region and a channel region, the non-volatile memory cells in the same row being divided into a plurality of cell pairs such that each of the cell pairs comprises a common source region and two drain regions, the common source region being connected to a common source line, the two drain regions being connected to two different bit lines, the method comprising the steps of:

8. The method according to claim 7, further comprising:

A second ion implantation is performed to the active region rectangle to form the source region and the drain region.

9. The method of claim 8, wherein the control gate region, the source region, and the drain region have a same electrical conductivity type.

10. The method of claim 7, wherein after the steps of depositing and etching the polysilicon film on the active region stripes and the active region rectangles, the active region rectangles in a same row are isolated from each other and arranged in a row direction, and each active region rectangle intersects two of the polysilicon stripes.

11. The method according to claim 7, further comprising:

prior to the defining step, a well ion implant is performed to the substrate to form a body of a plurality of MOSFET elements.

12. The method of claim 7 wherein the gate length of the floating gate of each nonvolatile memory cell is defined by a minimum feature size of a process technology generation, wherein a minimum cell area of each nonvolatile memory cell is limited to 12F ², wherein F is the minimum feature size of the process technology generation.

13. A method of manufacturing an array of non-volatile memory cells, the array of non-volatile memory cells comprising a plurality of non-volatile memory cells arranged in a row and column circuit configuration on a substrate, each non-volatile memory cell comprising a source region, a drain region, a floating gate, a control gate region and a channel region, the non-volatile memory cells in the same row being divided into a plurality of cell pairs such that each of the cell pairs comprises a common source region and two drain regions, the common source region being connected to a common source line, the two drain regions being connected to two different bit lines, the method comprising the steps of:

Etching through the mask, the first polysilicon strips, the second polysilicon strips and the oxide layer to the substrate to form a plurality of trenches extending in the row direction so as to divide each first active region strip and drain regions and source regions paired by any two adjacent row units;

14. The method of claim 13, wherein after the step of etching through the mask, the first plurality of polysilicon strips, the second plurality of polysilicon strips, and the oxide layer to the substrate, the first polysilicon strips are split to form the floating gate, and the second polysilicon strips are split to form a plurality of dummy polysilicon strips.

15. The method of claim 14, wherein each dummy polysilicon strip forms a channel stop region between two drain regions of a pair of cells of two adjacent columns, and wherein the channel stop region is of a semiconductor type opposite to its two adjacent drain regions.

16. The method according to claim 13, further comprising:

a second ion implantation is performed to the second active region to form the source region and the drain region.

17. The method of claim 16, wherein the control gate region, the source region, and the drain region have a same electrical conductivity type.

18. The method of claim 13 wherein the gate length of the control gate of each nonvolatile memory cell is defined by a minimum feature size of a process technology generation, and wherein a minimum cell area of each nonvolatile memory cell is limited to 12F ², where F is a minimum feature size of the process technology generation.

19. The method according to claim 13, further comprising: