CN111913822A - Inter-core communication mode based on AMP architecture - Google Patents
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Abstract
The invention discloses an inter-core communication mode based on an AMP architecture, which comprises the following steps: dividing a multi-core communication system into an application layer, a drive layer and a logic layer; configuring a circuit of a logic layer, and carrying out multi-core communication initialization configuration to obtain a configured multi-core communication system; starting a main core in the configured multi-core communication system, monitoring network information in an application layer through the main core, and constructing a main core and slave core management mechanism; and calling a driving layer interface to establish a communication request between the master core and the slave core according to a master-slave core management mechanism, and starting communication between the master core and the slave core. The invention provides an inter-core communication mode based on an AMP architecture, which reduces the inconsistency of data interaction interfaces between different operating systems, has short response time and avoids the problem of data loss.
Description
Technical Field
The invention belongs to the technical field of communication control, and particularly relates to an inter-core communication mode based on an AMP architecture.
Background
In recent years, the integration of the number of CPU cores on one chip has reached thousands due to the rapidly advancing semiconductor technology. Embedded mobile devices are indispensable in work and life interaction, frequently activated among industries, and also occupy an important position in the market. However, the increase rate of the performance of the chip using only a single core starts to slow down, and although the performance can be improved by improving the main frequency of the single-core processor and increasing the parallelism of the instruction level, the increase of the main frequency of the CPU also means that the power consumption of the chip needs to be increased, and the peak value of the power consumption of the modern general-purpose processor is already up to hundreds of watts. Therefore, the multi-nuclear technology gradually enters the human vision
The embedded processor is developed from a single core to a multi-core, and the process of isomorphism development to isomerism meets the requirements of different fields. For the current multi-core environment, the technology of inter-core communication, task scheduling, Cache consistency, inter-core synchronization and mutual exclusion, inter-core interrupt processing mechanism and the like of the processor are very important. However, the multi-core parallel embedded architecture simply adopting the SMP architecture cannot give play to the respective characteristics of each CPU, and the operating system communication interaction interfaces used by each CPU are also different, which results in an excessively complex inter-core communication mechanism.
Disclosure of Invention
Aiming at the defects in the prior art, the inter-core communication mode based on the AMP architecture solves the problem that an inter-core communication mechanism in the prior art is complex.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: an inter-core communication mode based on AMP architecture comprises the following steps:
s1, dividing the multi-core communication system into an application layer, a drive layer and a logic layer;
s2, configuring a circuit of the logic layer, and performing multi-core communication initialization configuration to obtain a configured multi-core communication system;
s3, starting a main core in the configured multi-core communication system, and monitoring network information in an application layer through the main core to construct a main core and slave core management mechanism;
and S4, calling a driving layer interface to establish a communication request between the master core and the slave core according to the master-slave core management mechanism, and starting communication between the master core and the slave core.
Further, the application layer in step S1 is configured to provide a network data interaction interface, perform TCP reliable network communication, provide a data packing processing or instruction parsing interface according to a communication protocol, obtain a device driver descriptor, and perform inter-core data interaction and data sharing by using a driver layer interface;
the driver layer in step S1 is configured to perform data read-write operation on a specific address or a register according to the hardware address provided by the logic layer, and provide a bottom layer operation interface for the application layer;
the logic layer in step S1 is configured to design an interrupt signal generating circuit, configure a system clock, and share a memory address, so as to provide a physical link connection for multi-core communication management.
Further, the step S2 includes the following sub-steps:
s21, configuring a circuit of a logic layer, initializing a register, reading a BOOT mode of the multi-core communication system, and acquiring a BOOT.bin file on an SD card in the multi-core communication system;
s22, transmitting the BOOT. bin file obtained in the step S21 to a DDR memory, judging whether a bit file exists in the DDR memory, if so, loading the bit file into the FPGA, and entering the step S23, otherwise, directly entering the step S23;
and S23, judging whether the elf file exists or not, if so, loading the elf file into a corresponding memory address space to obtain the configured multi-core communication system, otherwise, not operating to obtain the configured multi-core communication system.
Further, the master-slave management mechanism in step S3 includes a master management mechanism and a slave management mechanism.
Further, the master core management mechanism is specifically:
a1, starting a main core CPU0, and initializing a Linux system through the main core CPU 0;
a2, enabling the Linux system to start working, creating a TCP network communication object through a main core CPU0, and adding the TCP network communication object into a thread pool to obtain a network communication thread;
a3, monitoring the network state through the network communication thread, judging whether a connection object exists, if so, receiving port data corresponding to the connection object, storing the port data into a cache, and entering the step A4, otherwise, repeating the step A3;
a4, judging whether the start of the network communication thread is based on the acquisition of the network communication data according to the port data, if so, the thread is in a ready state, does not operate and is ended, otherwise, the thread is converted from the ready state to a running state to carry out control instruction and shared memory management, and the step A5 is carried out;
a5, judging whether a slave core awakening instruction exists in a signal sent by a network communication thread through a drive management thread in the Linux system, if so, awakening the process of a slave core CPU1 through an interrupt device of a logic layer, and ending a master core management mechanism, otherwise, directly ending the master core management mechanism.
Further, the slave core management mechanism is specifically: starting the slave core CPU1, judging whether the process is awakened or not through the slave core CPU1, if so, establishing a thread through the slave core CPU1, converting the ready state into an operation state, performing data processing, feeding back information to the master core CPU0, entering the ready state after the data processing is finished, waiting for awakening, and otherwise, not performing operation;
the data interaction between the master core CPU0 and the slave core CPU1 adopts a shared memory mode.
Further, the specific step of calling the driver layer interface to establish the communication request between the master core and the slave core in step S4 is:
b1, starting application program operation, calling a drive layer interface in an application layer through a main core CPU0, and sending an interrupt signal;
b2, calling a copy _ from _ uesr () function through a driver layer according to the interrupt signal to acquire the memory address of the application program operation under the application layer;
b3, judging whether the memory address is in the address range set by the logic layer, if so, calling an IOwrite32() function to write the address, carrying out interrupt response by the slave core CPU1, and proceeding to step B4, otherwise, not operating, and feeding back information of calling drive interface failure to the master core CPU 0;
b4, establishing a thread by the slave core CPU1, converting from a ready state to a running state, starting data processing, and feeding back information to the master core CPU 0;
b5, the main core CPU0 judges whether feedback information is wrong, no feedback information exists or the waiting time is overtime, if yes, the communication request is abnormal, the step B1 is returned, the inter-core communication application is carried out again, and if not, the communication request flow is judged to be correct, and the communication request is successful.
Further, the communication between the master core and the slave core in step S4 includes a master core communication flow and a slave core communication flow, and the master core communication flow and the slave core communication flow share a memory.
Further, the main core communication process specifically includes:
c1, monitoring the network data through the application layer, and performing command analysis on the monitored network data;
c2, acquiring a slave core CPU1 memory access mark corresponding to the command, and judging whether the slave core CPU1 memory access mark is false, if so, modifying the slave core CPU1 memory access mark to be true, calling a data access driver to store the data in a shared memory, entering the step C3, otherwise, repeating the step C2;
c3, sending an interrupt communication application to the slave core CPU1, and acquiring a memory access mark of the master core CPU 0;
and C4, judging whether the main core CPU0 memory access mark is false, if so, judging that the process of the slave core CPU1 does not feed back correct information or the interrupt communication application fails, repeating the step C3 after the waiting time is overtime, otherwise, judging that the data interaction of the master core and the slave core is successful, setting the memory access mark of the main core CPU0 to be false, and finishing the communication flow of the main core.
Further, the slave core communication process specifically includes:
d1, receiving an interrupt signal uploaded by the logic layer from the core CPU1, starting a data processing process, and acquiring a memory access mark of the slave core CPU 1;
d2, determining whether the memory access flag of the slave CPU1 is false, if so, repeating step D2, otherwise, setting the memory access flag of the slave CPU1 to be false, and proceeding to step D3;
d3, acquiring data from the shared memory by the slave CPU1 and processing the data;
d4, obtaining the memory access flag of the master CPU0 and determining whether it is true, if so, repeating step D4 after the waiting time is overtime, otherwise, setting the memory access flag of the master CPU0 to false, and completing the slave core communication process.
The invention has the beneficial effects that:
(1) the invention is suitable for the characteristics of different CPUs, adopts different operating systems for interaction, and simultaneously ensures that each operating system can use the independent API to communicate without adding other API interfaces by an interrupt mechanism.
(2) The shared memory of the invention realizes the convenience of resource management and allocation and simplifies the problem of cache consistency in multi-core communication.
(3) The invention provides an inter-core communication mode based on an AMP architecture, which reduces the inconsistency of data interaction interfaces between different operating systems, has short response time and avoids the problem of data loss.
Drawings
Fig. 1 is a flowchart of an inter-core communication method based on an AMP architecture according to the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, an inter-core communication method based on an AMP architecture includes the following steps:
s1, dividing the multi-core communication system into an application layer, a drive layer and a logic layer;
s2, configuring a circuit of the logic layer, and performing multi-core communication initialization configuration to obtain a configured multi-core communication system;
s3, starting a main core in the configured multi-core communication system, and monitoring network information in an application layer through the main core to construct a main core and slave core management mechanism;
and S4, calling a driving layer interface to establish a communication request between the master core and the slave core according to the master-slave core management mechanism, and starting communication between the master core and the slave core.
The application layer in the step S1 is configured to provide a network data interaction interface, perform reliable network communication of TCP, provide a data packing processing or instruction parsing interface according to a communication protocol, obtain a device driver descriptor, and perform inter-core data interaction and data sharing by using a driver layer interface;
the driver layer in step S1 is configured to perform data read-write operation on a specific address or a register according to the hardware address provided by the logic layer, and provide a bottom layer operation interface for the application layer;
the logic layer in step S1 is configured to design an interrupt signal generating circuit, configure a system clock, and share a memory address, so as to provide a physical link connection for multi-core communication management.
The step S2 includes the following sub-steps:
s21, configuring a circuit of a logic layer, initializing a register, reading a BOOT mode of the multi-core communication system, and acquiring a BOOT.bin file on an SD card in the multi-core communication system;
s22, transmitting the BOOT. bin file obtained in the step S21 to a DDR memory, judging whether a bit file exists in the DDR memory, if so, loading the bit file into the FPGA, and entering the step S23, otherwise, directly entering the step S23;
and S23, judging whether the elf file exists or not, if so, loading the elf file into a corresponding memory address space to obtain the configured multi-core communication system, otherwise, not operating to obtain the configured multi-core communication system.
The master-slave management mechanism in step S3 includes a master management mechanism and a slave management mechanism.
The main core management mechanism specifically comprises:
a1, starting a main core CPU0, and initializing a Linux system through the main core CPU 0;
a2, enabling the Linux system to start working, creating a TCP network communication object through a main core CPU0, and adding the TCP network communication object into a thread pool to obtain a network communication thread;
a3, monitoring the network state through the network communication thread, judging whether a connection object exists, if so, receiving port data corresponding to the connection object, storing the port data into a cache, and entering the step A4, otherwise, repeating the step A3;
a4, judging whether the start of the network communication thread is based on the acquisition of the network communication data according to the port data, if so, the thread is in a ready state, does not operate and is ended, otherwise, the thread is converted from the ready state to a running state to carry out control instruction and shared memory management, and the step A5 is carried out;
a5, judging whether a slave core awakening instruction exists in a signal sent by a network communication thread through a drive management thread in the Linux system, if so, awakening the process of a slave core CPU1 through an interrupt device of a logic layer, and ending a master core management mechanism, otherwise, directly ending the master core management mechanism.
The slave core management mechanism is specifically as follows: starting the slave core CPU1, judging whether the process is awakened or not through the slave core CPU1, if so, establishing a thread through the slave core CPU1, converting the ready state into an operation state, performing data processing, feeding back information to the master core CPU0, entering the ready state after the data processing is finished, waiting for awakening, and otherwise, not performing operation;
the data interaction between the master core CPU0 and the slave core CPU1 adopts a shared memory mode.
The specific steps of calling the driver layer interface to establish the communication request between the master core and the slave core in step S4 are as follows:
b1, starting application program operation, calling a drive layer interface in an application layer through a main core CPU0, and sending an interrupt signal;
b2, calling a copy _ from _ uesr () function through a driver layer according to the interrupt signal to acquire the memory address of the application program operation under the application layer;
b3, judging whether the memory address is in the address range set by the logic layer, if so, calling an IOwrite32() function to write the address, carrying out interrupt response by the slave core CPU1, and proceeding to step B4, otherwise, not operating, and feeding back information of calling drive interface failure to the master core CPU 0;
b4, establishing a thread by the slave core CPU1, converting from a ready state to a running state, starting data processing, and feeding back information to the master core CPU 0;
b5, the main core CPU0 judges whether feedback information is wrong, no feedback information exists or the waiting time is overtime, if yes, the communication request is abnormal, the step B1 is returned, the inter-core communication application is carried out again, and if not, the communication request flow is judged to be correct, and the communication request is successful.
The communication between the master core and the slave core in step S4 includes a master core communication flow and a slave core communication flow, and the master core communication flow and the slave core communication flow share a memory.
The main core communication process specifically comprises the following steps:
c1, monitoring the network data through the application layer, and performing command analysis on the monitored network data;
c2, acquiring a slave core CPU1 memory access mark corresponding to the command, and judging whether the slave core CPU1 memory access mark is false, if so, modifying the slave core CPU1 memory access mark to be true, calling a data access driver to store the data in a shared memory, entering the step C3, otherwise, repeating the step C2;
c3, sending an interrupt communication application to the slave core CPU1, and acquiring a memory access mark of the master core CPU 0;
and C4, judging whether the main core CPU0 memory access mark is false, if so, judging that the process of the slave core CPU1 does not feed back correct information or the interrupt communication application fails, repeating the step C3 after the waiting time is overtime, otherwise, judging that the data interaction of the master core and the slave core is successful, setting the memory access mark of the main core CPU0 to be false, and finishing the communication flow of the main core.
The slave core communication flow specifically comprises the following steps:
d1, receiving an interrupt signal uploaded by the logic layer from the core CPU1, starting a data processing process, and acquiring a memory access mark of the slave core CPU 1;
d2, determining whether the memory access flag of the slave CPU1 is false, if so, repeating step D2, otherwise, setting the memory access flag of the slave CPU1 to be false, and proceeding to step D3;
d3, acquiring data from the shared memory by the slave CPU1 and processing the data;
d4, obtaining the memory access flag of the master CPU0 and determining whether it is true, if so, repeating step D4 after the waiting time is overtime, otherwise, setting the memory access flag of the master CPU0 to false, and completing the slave core communication process.
In this embodiment, under a ZYNQ-7000 series dual-core chip platform, 16MB/s auto-increment data received by the network interface is used as an input test, and the experimental result shows: compared with an SMP (symmetric multi-processing) architecture system, the method meets the performance requirement of a real-time system, and can improve the interrupt response time from the level of a few milliseconds to the level of tens of microseconds. In multiple measurements, no data loss or data packet drop phenomenon is found.
The invention has the beneficial effects that:
(1) the invention is suitable for the characteristics of different CPUs, adopts different operating systems for interaction, and simultaneously ensures that each operating system can use the independent API to communicate without adding other API interfaces by an interrupt mechanism.
(2) The shared memory of the invention realizes the convenience of resource management and allocation and simplifies the problem of cache consistency in multi-core communication.
(3) The invention provides an inter-core communication mode based on an AMP architecture, which reduces the inconsistency of data interaction interfaces between different operating systems, has short response time and avoids the problem of data loss.
Claims (10)
1. The inter-core communication mode based on the AMP architecture is characterized by comprising the following steps:
s1, dividing the multi-core communication system into an application layer, a drive layer and a logic layer;
s2, configuring a circuit of the logic layer, and performing multi-core communication initialization configuration to obtain a configured multi-core communication system;
s3, starting a main core in the configured multi-core communication system, and monitoring network information in an application layer through the main core to construct a main core and slave core management mechanism;
and S4, calling a driving layer interface to establish a communication request between the master core and the slave core according to the master-slave core management mechanism, and starting communication between the master core and the slave core.
2. The inter-core communication method based on the AMP architecture of claim 1, wherein the application layer in step S1 is configured to provide a network data interaction interface, perform TCP reliable network communication, provide a data packing processing or instruction parsing interface according to a communication protocol, obtain a device driver descriptor, and perform inter-core data interaction and data sharing by using a driver layer interface;
the driver layer in step S1 is configured to perform data read-write operation on a specific address or a register according to the hardware address provided by the logic layer, and provide a bottom layer operation interface for the application layer;
the logic layer in step S1 is configured to design an interrupt signal generating circuit, configure a system clock, and share a memory address, so as to provide a physical link connection for multi-core communication management.
3. The AMP architecture-based inter-core communication of claim 1, wherein the step S2 comprises the sub-steps of:
s21, configuring a circuit of a logic layer, initializing a register, reading a BOOT mode of the multi-core communication system, and acquiring a BOOT.bin file on an SD card in the multi-core communication system;
s22, transmitting the BOOT. bin file obtained in the step S21 to a DDR memory, judging whether a bit file exists in the DDR memory, if so, loading the bit file into the FPGA, and entering the step S23, otherwise, directly entering the step S23;
and S23, judging whether the elf file exists or not, if so, loading the elf file into a corresponding memory address space to obtain the configured multi-core communication system, otherwise, not operating to obtain the configured multi-core communication system.
4. The AMP architecture-based inter-core communication manner of claim 1, wherein the master-slave core management mechanism in the step S3 comprises a master core management mechanism and a slave core management mechanism.
5. The AMP architecture-based inter-core communication manner of claim 4, wherein the primary core management mechanism is specifically:
a1, starting a main core CPU0, and initializing a Linux system through the main core CPU 0;
a2, enabling the Linux system to start working, creating a TCP network communication object through a main core CPU0, and adding the TCP network communication object into a thread pool to obtain a network communication thread;
a3, monitoring the network state through the network communication thread, judging whether a connection object exists, if so, receiving port data corresponding to the connection object, storing the port data into a cache, and entering the step A4, otherwise, repeating the step A3;
a4, judging whether the start of the network communication thread is based on the acquisition of the network communication data according to the port data, if so, the thread is in a ready state, does not operate and is ended, otherwise, the thread is converted from the ready state to a running state to carry out control instruction and shared memory management, and the step A5 is carried out;
a5, judging whether a slave core awakening instruction exists in a signal sent by a network communication thread through a drive management thread in the Linux system, if so, awakening the process of a slave core CPU1 through an interrupt device of a logic layer, and ending a master core management mechanism, otherwise, directly ending the master core management mechanism.
6. The AMP architecture-based inter-core communication manner of claim 5, wherein the slave core management mechanism is specifically: starting the slave core CPU1, judging whether the process is awakened or not through the slave core CPU1, if so, establishing a thread through the slave core CPU1, converting the ready state into an operation state, performing data processing, feeding back information to the master core CPU0, entering the ready state after the data processing is finished, waiting for awakening, and otherwise, not performing operation;
the data interaction between the master core CPU0 and the slave core CPU1 adopts a shared memory mode.
7. The inter-core communication method based on the AMP architecture of claim 1, wherein the specific step of calling the driver layer interface to establish the communication request between the master core and the slave core in step S4 is as follows:
b1, starting application program operation, calling a drive layer interface in an application layer through a main core CPU0, and sending an interrupt signal;
b2, calling a copy _ from _ uesr () function through a driver layer according to the interrupt signal to acquire the memory address of the application program operation under the application layer;
b3, judging whether the memory address is in the address range set by the logic layer, if so, calling an IOwrite32() function to write the address, carrying out interrupt response by the slave core CPU1, and proceeding to step B4, otherwise, not operating, and feeding back information of calling drive interface failure to the master core CPU 0;
b4, establishing a thread by the slave core CPU1, converting from a ready state to a running state, starting data processing, and feeding back information to the master core CPU 0;
b5, the main core CPU0 judges whether feedback information is wrong, no feedback information exists or the waiting time is overtime, if yes, the communication request is abnormal, the step B1 is returned, the inter-core communication application is carried out again, and if not, the communication request flow is judged to be correct, and the communication request is successful.
8. The AMP architecture-based inter-core communication manner of claim 1, wherein in step S4, the communication between the master core and the slave core comprises a master core communication flow and a slave core communication flow, and the master core communication flow and the slave core communication flow share a memory.
9. The AMP architecture-based inter-core communication manner of claim 8, wherein the main core communication flow is specifically as follows:
c1, monitoring the network data through the application layer, and performing command analysis on the monitored network data;
c2, acquiring a slave core CPU1 memory access mark corresponding to the command, and judging whether the slave core CPU1 memory access mark is false, if so, modifying the slave core CPU1 memory access mark to be true, calling a data access driver to store the data in a shared memory, entering the step C3, otherwise, repeating the step C2;
c3, sending an interrupt communication application to the slave core CPU1, and acquiring a memory access mark of the master core CPU 0;
and C4, judging whether the main core CPU0 memory access mark is false, if so, judging that the process of the slave core CPU1 does not feed back correct information or the interrupt communication application fails, repeating the step C3 after the waiting time is overtime, otherwise, judging that the data interaction of the master core and the slave core is successful, setting the memory access mark of the main core CPU0 to be false, and finishing the communication flow of the main core.
10. The AMP architecture-based inter-core communication manner of claim 8, wherein the slave core communication flow is specifically:
d1, receiving an interrupt signal uploaded by the logic layer from the core CPU1, starting a data processing process, and acquiring a memory access mark of the slave core CPU 1;
d2, determining whether the memory access flag of the slave CPU1 is false, if so, repeating step D2, otherwise, setting the memory access flag of the slave CPU1 to be false, and proceeding to step D3;
d3, acquiring data from the shared memory by the slave CPU1 and processing the data;
d4, obtaining the memory access flag of the master CPU0 and determining whether it is true, if so, repeating step D4 after the waiting time is overtime, otherwise, setting the memory access flag of the master CPU0 to false, and completing the slave core communication process.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112765091A (en) * | 2021-02-04 | 2021-05-07 | 南方电网科学研究院有限责任公司 | SoC inter-core communication method and device |
| CN112764917A (en) * | 2020-12-29 | 2021-05-07 | 福建万润新能源科技有限公司 | Method for master-slave-free parallel operation and task cooperation among multi-unit systems |
| CN113538767A (en) * | 2021-06-01 | 2021-10-22 | 浪潮金融信息技术有限公司 | Half-duplex drive layer change-making method, system and medium |
| CN115098173A (en) * | 2022-06-17 | 2022-09-23 | 电子科技大学 | Dual-core AMP framework-based method for identifying friend or foe identification signals at high speed |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101025697A (en) * | 2007-04-05 | 2007-08-29 | 杭州华为三康技术有限公司 | Method, system and master core and slave core for realizing user configuration |
| CN101216814A (en) * | 2007-12-26 | 2008-07-09 | 杭州华三通信技术有限公司 | Communication method and system of multi-nuclear multi-operating system |
| CN101354693A (en) * | 2008-09-11 | 2009-01-28 | 重庆邮电大学 | Communication scheduling system and method among cores of isomerization multi-core processor |
| CN101662551A (en) * | 2008-08-29 | 2010-03-03 | 深圳市东进通讯技术股份有限公司 | Enterprise converged communication system |
| CN102270189A (en) * | 2011-06-17 | 2011-12-07 | 西安电子科技大学 | Inter-core communication method based on FPGA (Field Programmable Gate Array) multi-core system |
| CN102770853A (en) * | 2009-12-23 | 2012-11-07 | 思杰***有限公司 | Systems and methods for managing large cache services in a multi-core system |
| CN102929834A (en) * | 2012-11-06 | 2013-02-13 | 无锡江南计算技术研究所 | Many-core processor and inter-core communication method thereof and main core and auxiliary core |
| US20140297920A1 (en) * | 2013-03-27 | 2014-10-02 | Kabushiki Kaisha Toshiba | Multi-core processor and control method |
| CN111427817A (en) * | 2020-03-23 | 2020-07-17 | 深圳震有科技股份有限公司 | Method for sharing I2C interface by dual cores of AMP system, storage medium and intelligent terminal |
| CN111427814A (en) * | 2020-03-05 | 2020-07-17 | 深圳震有科技股份有限公司 | Inter-core communication method based on AMP system, terminal and storage medium |
-
2020
- 2020-08-28 CN CN202010883181.2A patent/CN111913822B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101025697A (en) * | 2007-04-05 | 2007-08-29 | 杭州华为三康技术有限公司 | Method, system and master core and slave core for realizing user configuration |
| CN101216814A (en) * | 2007-12-26 | 2008-07-09 | 杭州华三通信技术有限公司 | Communication method and system of multi-nuclear multi-operating system |
| CN101662551A (en) * | 2008-08-29 | 2010-03-03 | 深圳市东进通讯技术股份有限公司 | Enterprise converged communication system |
| CN101354693A (en) * | 2008-09-11 | 2009-01-28 | 重庆邮电大学 | Communication scheduling system and method among cores of isomerization multi-core processor |
| CN102770853A (en) * | 2009-12-23 | 2012-11-07 | 思杰***有限公司 | Systems and methods for managing large cache services in a multi-core system |
| CN102270189A (en) * | 2011-06-17 | 2011-12-07 | 西安电子科技大学 | Inter-core communication method based on FPGA (Field Programmable Gate Array) multi-core system |
| CN102929834A (en) * | 2012-11-06 | 2013-02-13 | 无锡江南计算技术研究所 | Many-core processor and inter-core communication method thereof and main core and auxiliary core |
| US20140297920A1 (en) * | 2013-03-27 | 2014-10-02 | Kabushiki Kaisha Toshiba | Multi-core processor and control method |
| CN111427814A (en) * | 2020-03-05 | 2020-07-17 | 深圳震有科技股份有限公司 | Inter-core communication method based on AMP system, terminal and storage medium |
| CN111427817A (en) * | 2020-03-23 | 2020-07-17 | 深圳震有科技股份有限公司 | Method for sharing I2C interface by dual cores of AMP system, storage medium and intelligent terminal |
Non-Patent Citations (2)
| Title |
|---|
| XIAORUI WANG 等: "Design of communications model in double systems based on multi-core platform" * |
| 高珂 等: "多核***共享内存资源分配和管理研究" * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112764917A (en) * | 2020-12-29 | 2021-05-07 | 福建万润新能源科技有限公司 | Method for master-slave-free parallel operation and task cooperation among multi-unit systems |
| CN112764917B (en) * | 2020-12-29 | 2023-06-20 | 福建万润新能源科技有限公司 | Multi-unit system non-master-slave parallel operation and task cooperation method |
| CN112765091A (en) * | 2021-02-04 | 2021-05-07 | 南方电网科学研究院有限责任公司 | SoC inter-core communication method and device |
| CN112765091B (en) * | 2021-02-04 | 2024-05-03 | 南方电网科学研究院有限责任公司 | SoC inter-core communication method and device |
| CN113538767A (en) * | 2021-06-01 | 2021-10-22 | 浪潮金融信息技术有限公司 | Half-duplex drive layer change-making method, system and medium |
| CN113538767B (en) * | 2021-06-01 | 2023-10-27 | 浪潮金融信息技术有限公司 | Half-duplex driving layer change-making method, system and medium |
| CN115098173A (en) * | 2022-06-17 | 2022-09-23 | 电子科技大学 | Dual-core AMP framework-based method for identifying friend or foe identification signals at high speed |
| CN115098173B (en) * | 2022-06-17 | 2024-04-26 | 电子科技大学 | Method for identifying friend and foe identifying signal at high speed based on dual-core AMP architecture |
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