CN111834322B - Clamp structure for semiconductor package and semiconductor package comprising same - Google Patents

Clamp structure for semiconductor package and semiconductor package comprising same Download PDF

Info

Publication number
CN111834322B
CN111834322B CN202010089653.7A CN202010089653A CN111834322B CN 111834322 B CN111834322 B CN 111834322B CN 202010089653 A CN202010089653 A CN 202010089653A CN 111834322 B CN111834322 B CN 111834322B
Authority
CN
China
Prior art keywords
layer
main metal
metal layer
functional layer
jig structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010089653.7A
Other languages
Chinese (zh)
Other versions
CN111834322A (en
Inventor
崔伦华
金泳勋
李泰宪
赵廷焄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jmj Korea Co ltd
Original Assignee
Jmj Korea Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jmj Korea Co ltd filed Critical Jmj Korea Co ltd
Publication of CN111834322A publication Critical patent/CN111834322A/en
Application granted granted Critical
Publication of CN111834322B publication Critical patent/CN111834322B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49527—Additional leads the additional leads being a multilayer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Die Bonding (AREA)

Abstract

The present utility model relates to a jig structure for semiconductor packaging, and more particularly, to a jig structure for semiconductor packaging which is formed of metal layers of different materials, is suitable for semiconductor packaging, is not formed of a single metal, and is capable of reducing the cost of a semiconductor package manufactured by using a metal of a low cost and light weight, which has not been conventionally suitable for use, and is capable of realizing weight reduction. That is, in the semiconductor package according to the present utility model, there is provided a jig structure for electrically connecting the package structure, the jig structure comprising: a main metal layer for maintaining the shape of the jig structure; a first functional layer laminated on one side surface of the main metal layer and adapted to be used with a metal of a different type from the main metal layer; the first bonding layer is formed between the first functional layer and the main metal layer, and is suitable for bonding the first functional layer to the metal of the main metal layer.

Description

Clamp structure for semiconductor package and semiconductor package comprising same
Technical Field
The present utility model relates to a jig structure for semiconductor packaging and a semiconductor package including the same, and more particularly, to a jig structure for semiconductor packaging and a semiconductor package including the same, which are capable of reducing the cost of a semiconductor package manufactured by applying a metal of a low cost and light weight material, which has not been applied conventionally, by forming a material of a jig structure suitable for semiconductor packaging from metal layers of different materials, instead of forming a single metal.
Background
Generally, a semiconductor package includes a semiconductor chip, a lead frame, and a package body, the semiconductor chip is attached to a pad of the lead frame, and wires and leads of the lead frame are bonded (bonded) to achieve electrical connection.
However, since the conventional stack package of wires is used to exchange electrical signals with wires, the speed is low, and a large number of wires are used, so that the electrical characteristics of each chip are deteriorated. In addition, since the substrate needs to have an additional area to form the wires, the size of the package is increased, and a Gap (Gap) for bonding the wires to the bonding pads of the respective chips is required, there is a problem in that the entire height of the package is unnecessarily increased.
Accordingly, a clip (clip) structure using metal is provided in korean patent No. 1208332, korean patent No. 0482370, korean patent No. 1669902 and korean patent No. 1631232, which are disclosed by the present inventors, to provide a package structure having superior electrical connection performance, good thermal stability, and easy and effective heat release, compared to a semiconductor package using conventional wire.
In addition, although the conventional jig structure is made of copper for welding, the cost and weight of the jig are high due to the characteristics of copper. This problem is related to the increase in manufacturing costs of various electronic products using semiconductor chip packages, and the weight of the jig is a very important problem for products that are much invested in weight as smart phones.
Disclosure of Invention
The present utility model has been made to solve the above-described problems, and an object of the present utility model is to provide a jig structure for semiconductor packaging, which can reduce the cost and weight of a semiconductor package by applying a low-cost, lightweight metal to a main metal layer and applying a metal having excellent conductivity to a portion where electrical connection is achieved, and which can improve the electrical connection characteristics, and a semiconductor package including the jig structure.
In the semiconductor package according to the present utility model, there is provided a jig structure for electrically connecting the package structure, comprising: a main metal layer for maintaining the shape of the jig structure; a first functional layer laminated on one side surface of the main metal layer and adapted to be used with a metal of a different type from the main metal layer; the first bonding layer is formed between the first functional layer and the main metal layer, and is suitable for bonding the first functional layer to the metal of the main metal layer.
In the present utility model, the thickness of the first functional layer is smaller than the thickness of the main metal layer.
In the present utility model, the main metal layer is formed of a single metal of aluminum (Al).
The present utility model is characterized in that in the main metal layer, aluminum (Al) is formed of 50% or more based on the total weight ratio of the main metal layer, and the balance is a metal alloy containing one or more of copper (Cu), magnesium (Mg), nickel (Ni), palladium (Pd), silver (Ag), gold (Au), manganese (Mn), zinc (Zn), silicon (Si), chromium (Cr), and titanium (Ti).
In the present utility model, the first functional layer is formed of a single metal of copper (Cu).
In the first functional layer, copper (Cu) is formed of 50% or more based on the total weight ratio of the first functional layer, and the balance is a metal alloy containing one or more of aluminum (Al), silver (Ag), iron (Fe), gold (Au), palladium (Pd), nickel (Ni), tin (Sn), and lead (Pb).
The present utility model is characterized in that nickel (Ni) or titanium (Ti) is applied to the first bonding layer.
The present utility model is characterized by further comprising: a second functional layer laminated on the other side surface of the main metal layer and adapted to be used with a metal of a different type from the main metal layer; and a second bonding layer formed between the second functional layer and the main metal layer, wherein the second bonding layer is made of a metal capable of bonding the second functional layer to the main metal layer.
A semiconductor package according to an embodiment of the present utility model is characterized by comprising: a lead frame composed of one or more pads and one or more lead terminals; more than one semiconductor chip mounted on the pad; a clamp structure for electrically connecting the semiconductor chip and the lead terminal; and a package body capable of protecting the periphery of the semiconductor chip by molding, wherein the jig structure is the jig structure for semiconductor packaging.
In the present utility model, when the clamp structure is formed, the material of the main metal layer is applied with low-cost and light-weight metal, and the part of the functional layer laminated on the main metal layer for realizing electric connection is applied with metal with excellent conductivity, so that the cost and weight of the semiconductor package are reduced, and the effect of excellent electric connection characteristic is achieved.
The present utility model has an effect of firmly maintaining the bonding state of the functional layers by providing a bonding layer for facilitating bonding between the two metal layers between the main metal layer containing aluminum as a main component and the functional layer containing copper as a main component.
Drawings
Fig. 1 is a view showing a jig structure for semiconductor package according to the present utility model.
Fig. 2 is a view showing an example in which the jig structure of the present utility model is applied to a semiconductor package.
Fig. 3 is a view showing another embodiment of the jig structure for semiconductor package of the present utility model.
Description of the reference numerals
10: clamp structure 20: lead frame
30: semiconductor chip 40: package body
100: main metal layer 200: first functional layer
300: first bonding layer 400: second functional layer
500: a second bonding layer
Detailed Description
Hereinafter, preferred embodiments of the present utility model will be described in detail with reference to the accompanying drawings. In describing the present utility model, a detailed description of the related known functions or configurations will be omitted when it is determined that the gist of the present utility model may be unnecessarily obscured.
In the semiconductor package of the present utility model, a jig structure 10 for electrically connecting the package structure, the jig structure 10 includes: a main metal layer 100 for maintaining the shape of the jig structure 10; a first functional layer 200 laminated on one side surface of the main metal layer 100 and adapted to be used with a metal of a different type from the main metal layer 100; the first bonding layer 300 is formed between the first functional layer 200 and the main metal layer 100, and is made of a metal that can bond the first functional layer 200 to the main metal layer 100.
The present utility model is characterized in that a low-cost and lightweight metal is applied to the material of the main metal layer 100 that maintains the overall shape, and a metal having excellent conductivity is applied to the portion of the first functional layer 200 that realizes electrical connection, thereby reducing the price and weight of the semiconductor package and improving the electrical connection characteristics.
Therefore, the thickness of the first functional layer 200 is thinner than that of the main metal layer 100. Preferably, the thickness of the main metal layer 100 is formed to be 25 μm (micrometers) to 2mm (millimeters), and the first functional layer 200 is preferably formed to be thinner than 0.05 μm (micrometers) to 15 μm (micrometers).
The main metal layer 100 may be made of a single metal of aluminum (Al), including the most aluminum (Al), and may be formed as a mixture with another metal. That is, aluminum (Al) may be formed of 50% or more based on the total weight ratio of the main metal layer 100, and the remainder may be formed of a metal alloy including one or more of copper (Cu), magnesium (Mg), nickel (Ni), palladium (Pd), silver (Ag), gold (Au), manganese (Mn), zinc (Zn), silicon (Si), chromium (Cr), and titanium (Ti).
In this way, when the main metal layer 100 is composed of aluminum as a main component, the cost of the jig structure 10 can be reduced and weight can be reduced as compared with the conventional technique in which the jig structure is composed of only copper. However, the problem that the main metal layer 100 made of aluminum is difficult to weld due to the characteristics of the material and the electrical connection characteristics are poor has not been applied at all so far, and the problem is solved by the first functional layer 200 of the present utility model.
The first functional layer 200 may be formed of a single metal of copper (Cu), including at most copper, and may be formed as a mixture with another metal. That is, copper (Cu) may be formed of 50% or more based on the total weight ratio of the first functional layer 200, and the remainder may be formed of a metal alloy including one or more of aluminum (Al), silver (Ag), iron (Fe), gold (Au), palladium (Pd), nickel (Ni), tin (Sn), and lead (Pb). The first functional layer 200 may be formed of a single material or may be formed of 2 or more layers of different materials.
The first bonding layer 300 is formed between the first functional layer 200 and the main metal layer 100, and can easily bond the first functional layer 200 to the metal layer of the main metal layer 100. The first functional layer 200 containing copper as a main component and the main metal layer 100 containing aluminum as a main component cannot be bonded due to the characteristics of the materials, and therefore the first bonding layer 300 must be formed.
The first bonding layer 300 is preferably made of nickel (Ni) or titanium (Ti), and preferably has a thickness thinner than that of the first functional layer 200. The thickness of the first bonding layer 300 is preferably 0.01 to 4 μm (micrometers).
If the first functional layer 200 is made of a single metal such as nickel instead of copper as the main component, there is no problem in forming the first functional layer 200 even if an additional bonding layer is not present, but when the first functional layer 200 is made of only a metal such as nickel, there is a problem in that the nickel layer is peeled off when the package main body 40 is made by EMC molding in the next step.
In a preferred first embodiment of the material constituting the jig structure 10 of the present utility model, aluminum is used for the main metal layer 100, copper is used for the first functional layer 200, and nickel is used for the first bonding layer 300. Also, in the preferred second embodiment, the main metal layer 100 is aluminum, the first functional layer 200 is copper, and the first bonding layer 300 is titanium.
The jig structure 10 thus formed may be applied to a semiconductor package including: a lead frame 20 composed of a pad and a plurality of lead terminals; one or more semiconductor chips 30 mounted on the pads; a clamp structure for electrically connecting the semiconductor chip 30 and the lead terminal; and a package body 40 for protecting the periphery of the semiconductor chip 30 by molding. The above-described structure is an example of a jig structure to which the present utility model is applied, and is applicable to various types of package structures.
Further, since the conventional jig structure 10 is made of copper, there is a problem in that silver (Ag) or gold (Au) plating must be added to the upper portion of the jig structure 10 in advance in order to join the bonding wires, but the present utility model has an advantage in that the bonding wires (B-W) can be easily joined without additional silver/gold plating since the main metal layer 100 is made of aluminum.
Fig. 3 shows another embodiment of the present utility model, which is characterized by further comprising: a second functional layer 400 which is laminated on the other side surface of the main metal layer 100 and is made of a metal different from the main metal layer 100; the second bonding layer 500 is formed between the second functional layer 400 and the main metal layer 100, so that a metal that can bond the second functional layer 400 to the main metal layer 100 is applied.
The above embodiment is an embodiment in which the second functional layer 400 is further included on the opposite side of the first functional layer 200, and is an embodiment suitable for use when another package structure is connected to the upper portion of the main metal layer 100. The second functional layer 400 also has the same structural features as the first functional layer 200, and is formed by bonding the second functional layer 400 between the second functional layer 400 and the main metal layer 100 through the second bonding layer 500.
That is, the second functional layer 400 may be formed to be mixed with other metals using a single metal of copper (Cu) or copper (Cu) as a main component, and nickel (Ni) or titanium (Ti) may be used for the second bonding layer 500. The second functional layer 400 may be formed of a single material or may be formed of 2 or more layers of different materials.
Since the structural features of the second functional layer 400 and the second bonding layer 500 are the same as those of the first functional layer 200 and the first bonding layer 300, the functional description and the repetitive description about the applicable materials are omitted.
The present utility model is described as being applied to the jig structure 10 having a remarkable structural effect, but the structures of the main metal layer 100, the first functional layer 200, and the first bonding layer 300 of the present utility model can be still applied to a lead frame made of only a conventional copper material.
The present utility model has been described above with reference to the above embodiments, and it is apparent that various modifications can be made within the scope of the technical idea of the present utility model.

Claims (7)

1. A jig structure for semiconductor packaging (10) for electrically connecting structures of packages in semiconductor packages, characterized in that the jig structure for semiconductor packaging (10) comprises:
a main metal layer (100) that maintains the shape of the jig structure (10);
a first functional layer (200) which is laminated on one side surface of the main metal layer (100) and which is made of a metal of a different type from the main metal layer (100);
a first bonding layer (300) formed between the first functional layer (200) and the main metal layer (100) and adapted to be used with a metal capable of bonding the first functional layer (200) to the main metal layer (100),
wherein the thickness of the first functional layer (200) is thinner than that of the main metal layer (100),
in the main metal layer (100), aluminum is formed by 50% or more based on the total weight ratio of the main metal layer (100),
in the first functional layer (200), copper is formed by 50% or more based on the total weight ratio of the first functional layer (200) so that the main metal layer (100) is formed of a lightweight material as compared with the first functional layer (200),
the first bonding layer (300) is suitably nickel or titanium.
2. The jig structure for semiconductor packaging according to claim 1, wherein the main metal layer (100) is formed of a single metal of aluminum material.
3. The jig structure for semiconductor encapsulation according to claim 1, wherein the main metal layer (100) is a metal alloy, and the remainder other than aluminum is one or more selected from the group consisting of copper, magnesium, nickel, palladium, silver, gold, manganese, zinc, silicon, chromium, and titanium.
4. The jig structure for semiconductor encapsulation according to claim 1, wherein the first functional layer (200) is formed of a single metal of copper material.
5. The jig structure for semiconductor encapsulation according to claim 1, wherein the first functional layer (200) is a metal alloy, and the remainder other than copper is one or more selected from the group consisting of aluminum, silver, iron, gold, palladium, nickel, tin, and lead.
6. The jig structure for semiconductor encapsulation according to claim 1, further comprising:
a second functional layer (400) which is laminated on the other side surface of the main metal layer (100) and which is made of a metal of a different type from the main metal layer (100);
and a second bonding layer (500) formed between the second functional layer (400) and the main metal layer (100), wherein a metal capable of bonding the second functional layer (400) to the main metal layer (100) is used.
7. A semiconductor package, characterized in that,
comprising the following steps:
a lead frame composed of one or more pads and one or more lead terminals;
more than one semiconductor chip mounted on the pad;
a clamp structure for electrically connecting the semiconductor chip and the lead terminal; and
a package body capable of protecting the periphery of the semiconductor chip by molding,
the jig structure is the jig structure for semiconductor packaging according to any one of claims 1 to 6.
CN202010089653.7A 2019-04-17 2020-02-12 Clamp structure for semiconductor package and semiconductor package comprising same Active CN111834322B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020190044642A KR102216738B1 (en) 2019-04-17 2019-04-17 Metal Clip for Semiconductor package
KR10-2019-0044642 2019-04-17

Publications (2)

Publication Number Publication Date
CN111834322A CN111834322A (en) 2020-10-27
CN111834322B true CN111834322B (en) 2024-03-22

Family

ID=72913374

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010089653.7A Active CN111834322B (en) 2019-04-17 2020-02-12 Clamp structure for semiconductor package and semiconductor package comprising same

Country Status (2)

Country Link
KR (1) KR102216738B1 (en)
CN (1) CN111834322B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11705387B2 (en) * 2020-09-02 2023-07-18 Infineon Technologies Ag Multi-layer interconnection ribbon

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1851914A (en) * 2006-05-29 2006-10-25 朱冬生 Lead-frame and semi-conductor device with same
CN101345275A (en) * 2007-07-10 2009-01-14 晶元光电股份有限公司 Luminous element
CN101488463A (en) * 2008-01-17 2009-07-22 阿克泰克萨特株式会社 Production method of substrate for semiconductor parcage, and metal plating produced by the same
CN101488539A (en) * 2008-01-17 2009-07-22 晶元光电股份有限公司 Light emitting element
CN102354722A (en) * 2008-05-26 2012-02-15 晶元光电股份有限公司 High-power light-emitting device
CN105845672A (en) * 2016-06-15 2016-08-10 南通富士通微电子股份有限公司 Package structure
KR20180084588A (en) * 2017-01-17 2018-07-25 주식회사 네패스 Method of manufacturing semiconductor package

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014112581A (en) * 2012-12-05 2014-06-19 Nippon Micrometal Corp Bonding wire and bonding ribbon
KR20190007936A (en) * 2017-07-14 2019-01-23 제엠제코(주) Multiple Combination clip structure and Semiconductor package with clip structure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1851914A (en) * 2006-05-29 2006-10-25 朱冬生 Lead-frame and semi-conductor device with same
CN101345275A (en) * 2007-07-10 2009-01-14 晶元光电股份有限公司 Luminous element
CN101488463A (en) * 2008-01-17 2009-07-22 阿克泰克萨特株式会社 Production method of substrate for semiconductor parcage, and metal plating produced by the same
CN101488539A (en) * 2008-01-17 2009-07-22 晶元光电股份有限公司 Light emitting element
CN102354722A (en) * 2008-05-26 2012-02-15 晶元光电股份有限公司 High-power light-emitting device
CN105845672A (en) * 2016-06-15 2016-08-10 南通富士通微电子股份有限公司 Package structure
KR20180084588A (en) * 2017-01-17 2018-07-25 주식회사 네패스 Method of manufacturing semiconductor package

Also Published As

Publication number Publication date
KR20200122439A (en) 2020-10-28
CN111834322A (en) 2020-10-27
KR102216738B1 (en) 2021-02-18

Similar Documents

Publication Publication Date Title
US9666501B2 (en) Semiconductor device including a lead frame
US9349675B2 (en) Semiconductor device and method of manufacturing the same
US7508012B2 (en) Electronic component and method for its assembly
US20240088087A1 (en) Electronic device with multi-layer contact and system
WO2006072031A1 (en) Lead-free and multi-layers preplated leadframe
US8399996B2 (en) Chip carrier
US6087712A (en) Lead frame containing leads plated with tin alloy for increased wettability and method for plating the leads
CN111834322B (en) Clamp structure for semiconductor package and semiconductor package comprising same
US8125060B2 (en) Electronic component with layered frame
US10535589B2 (en) Clip structure and semiconductor package using the same
JP2005019922A (en) Lead frame for semiconductor packages
US8110931B2 (en) Wafer and semiconductor package
US10896889B2 (en) Multilayer clip structure attached to a chip
CN209843696U (en) Semiconductor package using conductive metal structure
KR102222146B1 (en) Low-Cost Semiconductor package with metal structure
US20210166997A1 (en) Semiconductor package using conductive metal structure
US11189550B2 (en) Low-cost semiconductor package using conductive metal structure
CN107591382B (en) Enhanced solder pad
US20110241026A1 (en) Light-emitting diode chip and package structure thereof
KR100437821B1 (en) semiconductor package and metod for fabricating the same
JP2602161B2 (en) High heat dissipation integrated circuit package
JPS6232622B2 (en)
KR100544274B1 (en) Layered metal architecture of substrate for stud bump
TWI250628B (en) Leadframe, semiconductor package and method for manufacturing the same
JP3540249B2 (en) Method of connecting external lead of semiconductor device package to external electrode

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant