CN101488463A - Production method of substrate for semiconductor parcage, and metal plating produced by the same - Google Patents
Production method of substrate for semiconductor parcage, and metal plating produced by the same Download PDFInfo
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- CN101488463A CN101488463A CNA2008100062731A CN200810006273A CN101488463A CN 101488463 A CN101488463 A CN 101488463A CN A2008100062731 A CNA2008100062731 A CN A2008100062731A CN 200810006273 A CN200810006273 A CN 200810006273A CN 101488463 A CN101488463 A CN 101488463A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention relates to a methd of manufacturing semiconductor package substrate and metallic coating made therefrom, particularly to a manufacturing method using bonded or erosive conductive release film, which is easy to remove the part provided with a semiconductor chip and a bonding pad pattern on the metallic film without excessively etching, thereby increasing working procedure speed and manufacturing environmental friendly semiconductor package substrate brought by minimum etching amount; and introducing Cu-Sn layer onto a bonding pad metal layer of a semiconductor base plate, thereby having non-magnetism and preventing a metallic coating from the diffused semiconductor base plate of a copper layer. According to the invention, environmental pollution brought by etching of a carrier frame in the past method of manufacturing the semiconductor package substrate is monimized, efficiency is increased through simplifying working procedure, and cost is decreased through reclaiming and reusing the used carrier frame. In addition, alloy layer is applied to replace Ni in the metallic coating of the semiconductor package substrate, thereby providing non magnetic metal layer.
Description
Technical field
The present invention relates to the manufacture method of semiconductor-sealing-purpose substrate and utilize the coat of metal that it makes, in more detail, relate to the conductivity release film that a kind of utilization can be bonding and be peeled off, do not need etching exceedingly just can easily remove the position that is formed with semiconductor chip and welding disk pattern on the metallic film, thereby when improving operation speed, can make the manufacture method that minimizes the semiconductor-sealing-purpose substrate of the environment-friendly type of bringing by etch quantity; And import the Cu-Sn layer, thereby have non magnetic and prevent the semiconductor substrate coat of metal from the diffusion of copper metal layer to the pad metal layer that is formed on the semiconductor substrate.
Background technology
Recently,, the semiconductor device of the semiconductor device of plastic packaging type etc. is required high-density mounting, thereupon, advance the small-sized and slimming of semiconductor device for the miniaturization of corresponding electronic equipment.Particularly, along with advancing small-sized, slim and spininess pinization, require highdensity small-sized, slim and plastic packaging N-type semiconductor N device.
Generally, semiconductor packages forms by the method that installation semiconductor chip on the substrate that is formed with certain lead or welding disk pattern carries out plastic packaging.Usually, so-called semiconductor packages means semiconductor chip is connected electrically on the substrate and with it and seals with seal body material, thereby semiconductor chip stably is installed on the motherboard.Here, aforesaid substrate has inside and outside lead function that is electrically connected semiconductor packages and the function that supports semiconductor element.
QFP (Quad Flat Pack: quad flat package) use inner pin as the method for packaging semiconductor that uses in the past as the projection that the semiconductor element bond pad is carried out wire-bonded.This inner pin need be used to make leadframe to maintain the plastic packaging fixed part of fixed position in utilizing the driving fit process of moulding resin.Therefore, this inner pin has from external pin and is bent downwardly and forms, and being assemblied in the structure on the motherboard, but this structure becomes the reason that reduces packaging density.
In order to address the above problem a little, recently as the semiconductor packages of surface installation type, develop and on the bottom surface is formed with the carrier of outer electrode, carry after semiconductor chip is electrically connected, its carrier upper surface is carried out the semiconductor packages of resin-sealed type.The spherical point contacts array package) or LGA (Land GridArray: contact array encapsulation) can enumerate BGA (Ball Grid Array: as the example of this device.Such semiconductor package is contained in its bottom surface side and has the structure of installing with motherboard, and the semiconductor packages of this surface installation type will form main flow backward.
As the example of the semiconductor packages of above-mentioned surface installation type, used the semiconductor packages of eliminating leadframe as shown in Figure 6.Figure is the vertical cross-section diagram of the above-mentioned semiconductor packages of expression.
As shown in Figure 6, above-mentioned semiconductor packages 100 has following structure: semiconductor chip 120 is set on semiconductor-sealing-purpose substrate 110, after metal fine 130 connection semiconductor chips 120 and substrate 110 formation electrical connections, seal with moulding resin 140.
Here, the substrate 110 tube core contact pad 112 and the contact pad 113 that comprise carrier frame 111, be formed on the carrier frame 111 and constitute by the conductive metal layer with certain pattern form.
The metal electrode that is made of the conductive metal layer constitutes and comprises that tube core contact pad 112 that semiconductor chip 120 is installed and the metal electrode that disposes and be electrically connected by semiconductor chip 120 and metal fine 130 in the mode around tube core contact pad 112 are the structure of contact pad 113.
If observe the manufacture method of the semiconductor packages of surface installation type with said structure, then carry out: be the surface applied photoresist of carrier frame 111 at the resin bed that is formed with the copper film according to following process, carry out after the exposure imaging, carry out plating in the zone of removing photoresist with gold/nickel, copper etc., form pattern and make substrate 110.Then, follow semiconductor chip 120 is installed on the tube core contact pad 112 on the substrate 110, connect contact pad 113 and semiconductor chips 120 with metal fine 130, and with the process of semiconductor chip 120, metal fine 130 and metal electrode 112,113 sealings.
When finishing above-mentioned semiconductor packages 100, to carry out etching and remove carrier frame 111 at last, so that expose the bottom surface of tube core contact pad 112 and contact pad 113.By exposing of above-mentioned metal electrode 112,113, can keep being chapped from the cold of position, bottom surface sealing resin, owing to guaranteed direct hot path from the tube core contact pad 112 that exposes to motherboard, thus improve thermal characteristics.And,, then, when forming the structure of stacked above-mentioned semiconductor packages, have the advantage that can form to high-density thus owing to not existing inner pin to reduce the height of semiconductor packages if utilize the structure of the semiconductor packages that does not have above-mentioned leadframe.
But, cause the etch quantity of thicker copper carrier frame 111 to increase by above-mentioned etching step, then not only can increase the waste of copper resource, also cause environmental pollution problems, thereby become the factor that reduces operation speed.
In addition, in the metal as the stacking material of the metal electrode that uses in the past, used nickel (Ni) in order to improve corrosion resistance, this Ni metal helps to improve corrosion resistance, but clearly be to make human body cause irritated poisonous metal recently, thereby forbidden the use of nickel plating (Ni) ornaments in Europe, started to develop the stainless steel of not nickeliferous (Ni) in Japan.
And then, when ferromagnetic Ni metal is used as the barrier layer (barrierlayer) of metal electrode, because because of the Ni metal forms eddy current and heating and consequent magnetic variation shape and magnetic field, the possibility that the circuit of adjacency is impacted is very big, and being badly in need of exploitation, to replace the material non magnetic, environment-friendly type of Ni metal be truth.
Summary of the invention
The present invention makes in order to address the above problem a little, the objective of the invention is to, a kind of manufacture method of semiconductor-sealing-purpose substrate is provided, the conductivity release film is applied on the carrier frame, the problem of environmental pollution that etching by above-mentioned carrier frame is brought minimizes, raise the efficiency recovery that can be by carrier frame and be used to again curtail expenditure to simplify by operation.
And, according to the present invention, its purpose is, adopt to replace being applied in the past copper-Xi (Cu-Sn) alloy-layer of Ni metal of the coat of metal of semiconductor-sealing-purpose substrate, make owing to form the minimizing possibility that eddy current and heating and consequent magnetic variation shape and magnetic field impact the circuit of adjacency because of the Ni metal.
The present invention relates to the manufacture method of semiconductor-sealing-purpose substrate in order to solve above-mentioned problem, and comprising: framework provides step, the conductivity release film is placed between carrier frame and the metallic film make frame parts; Pattern step is utilized photoresist a plurality of metal levels of plating on above-mentioned metallic film, thereby forms predetermined pattern; Encapsulation forms step, on above-mentioned metal level semiconductor chip is set, and seals above-mentioned semiconductor chip and metal level with moulding resin; And strip step, utilize above-mentioned conductivity release film, peel off release film of above-mentioned conductivity and carrier frame from above-mentioned metallic film.
Here, preferred above-mentioned carrier frame has utilized metal or engineering plastics.
Here, the thickness of above-mentioned metallic film is 3 μ m to 20 μ m, compares economy with whole carrier frames of thickness more than the etching 100 μ m in past, and has the effect that improves operation speed, and is therefore preferred.
And in above-mentioned pattern step, metal level can provide preferred on the nonmagnetic metal level this point with the order of Au layer, Cu-Sn alloy-layer, Au layer or with the sequential cascade of Au layer, Cu-Sn alloy-layer, Cu layer, Cu-Sn alloy-layer, Au layer.
In addition, in above-mentioned pattern step, can be metal level with the order of Au layer, Ni layer, Au layer or with the sequential cascade of Au layer, Ni layer, Cu layer, Ni layer, Au layer.
And then, in above-mentioned pattern step, can be metal level with the order of Au layer, Pd layer, Cu-Sn alloy-layer, Pd layer or with the sequential cascade of Au layer, Pd layer, Ni layer, Pd layer.
And the semiconductor-sealing-purpose coat of metal of the present invention is characterised in that the above-mentioned coat of metal comprises the Cu-Sn alloy.
In addition, the above-mentioned coat of metal forms with the order of Au layer, Cu-Sn alloy-layer, Au layer or with the sequential cascade of Au layer, Cu-Sn alloy-layer, Cu layer, Cu-Sn alloy-layer, Au layer, and is preferred on as the Au layer this point of underseal (Etching resist) in flexible Application.
In addition, the preferred above-mentioned coat of metal constitutes with the sequential cascade of Au layer, Pd layer, Cu-Sn alloy-layer, Pd layer.
And then the alloy ratio of above-mentioned Cu-Sn alloy is that the weight ratio of 15-55 weight %, Sn is that 45-85 weight % constitutes according to the weight ratio of Cu, form on the best alloy ratio this point preferred.
According to the present invention, a kind of manufacture method is provided, the problem of environmental pollution that the etching by carrier frame in the manufacture method of semiconductor-sealing-purpose substrate is in the past caused minimizes, simplify implementation efficiency based on operation and improve, recovery that can be by employed carrier frame and be used to again curtail expenditure.
And, according to the present invention, use to replace being applied in the past the alloy-layer of the Ni metal in the coat of metal of semiconductor-sealing-purpose substrate, nonmagnetic metal level can be provided.
Description of drawings
Fig. 1 is the precedence diagram that illustrates based on the manufacture method of the semiconductor-sealing-purpose substrate of one embodiment of the invention.
Fig. 2 a is the sectional view that illustrates successively based on the manufacture method of the semiconductor-sealing-purpose substrate of one embodiment of the invention to Fig. 2 e.
Fig. 3 is that two of Cu-Sn alloy maintains state diagram.
Fig. 4 is the magnetic resume curve by the semiconductor-sealing-purpose substrate coating of embodiment 1 and comparative example manufacturing.
Fig. 5 is the curve chart by the coefficient of thermal expansion of the semiconductor-sealing-purpose substrate coating of embodiment 1 and comparative example manufacturing.
Fig. 6 illustrates the sectional view of conventional semiconductor packages with substrate.
Embodiment
Below, with reference to description of drawings based on the manufacture method of semiconductor-sealing-purpose substrate of the present invention and utilize the coat of metal that its makes.
Fig. 1 is the precedence diagram that illustrates based on the manufacture method of the semiconductor-sealing-purpose substrate of one embodiment of the present of invention, and Fig. 2 a to Fig. 2 e is the sectional view that illustrates successively based on the manufacture method of the semiconductor-sealing-purpose substrate of one embodiment of the present of invention.
As shown in Figure 1, comprise that based on the manufacture method of the semiconductor-sealing-purpose substrate of one embodiment of the present of invention framework provides step S10, pattern step S20, encapsulation to form step S30, and strip step S40 and constituting.Here, the order of exchange encapsulation formation step S30 and strip step S40 is also harmless.
Shown in Fig. 2 a, it is the step of making the frame parts 10 that stacks gradually carrier frame 11, conductivity release film 12, metallic film 13 that framework provides step S10.
Particularly, it is coating electrically conductive release film 12 on carrier frame 11 that framework provides step S10, thereon crimping metallic film 13 and make the operation of frame parts 10.
The frame parts 11 of Shi Yonging has the function of carrying semiconductor chip described later and metal electrode and supporting in the present invention, its material preferably is made of common copper (Cu) or copper alloy, can also be made of the engineering plastics of the metal of in addition iron (Fe) or ferroalloy etc. or FR4 (glass-epoxide resin type), polyimides (PI), PETG (PET), epoxy (Epoxy) etc.
Particularly, utilize under the situation of above-mentioned engineering plastics, compare with the metallic carrier framework, hardness is higher, when can reach the material deformation that prevents to cause,, has the advantage that can also obtain saving raw-material effect to increase operability by the plating stress that produces in the pattern plating process.
As the method for separating conductivity release film 12 and metallic film 13, can utilize the method for cleaning with appropriate solvent, based on the stripping means of laser, based on the mechanicalness stripping means of vacuum, use the stripping means of plasma etc., conductivity release film 12 can utilize by the synthetic resin that is suitable for various stripping meanss or comprise release film or the release liners that the material of silicon constitutes.
The material of metallic film 13 can be made of copper or copper alloy, iron or ferroalloy.
Pattern step S20 is the operation at the electroplating surface metal electrode pattern of the metallic film 13 of the superiors that constitute above-mentioned carrier frame parts 10.
Composition operation S20 carries out by following process shown in Fig. 2 b: at frame parts 10, be surface applied photoresist A at metallic film 13 accurately, utilize ultraviolet ray that photoresist A is exposed, after developing, the surperficial B that like that is removed the metallic film 13 that exposes by development shown in Fig. 2 c goes up electroplated metal layer 20 and carries out stacked, finish when electroplating, remove employed photoresist A.The metal level 20 that forms by above-mentioned pattern step S20 becomes tube core contact pad 21 and contact pad 22 in semiconductor packages, it stacks gradually different kinds of metals and constitutes.
Fig. 2 c illustrates the accompanying drawing of finishing metal level ordered state behind the pattern step S20.
Shown in Fig. 2 c, the execution mode of the semiconductor-sealing-purpose coat of metal 20 of the present invention is not particularly limited, but can be divided into A-1, two kinds of A-2.
The execution mode of A-1 is gold (Au), copper-Xi (Cu-Sn) alloy, gold (Au); The execution mode of A-2 is gold (Au), copper-Xi (Cu-Sn) alloy, copper (Cu), copper-Xi (Cu-Sn) alloy, gold (Au).
Here; after finishing the semiconductor packages operation, carry out when being used to remove the etching work procedure of metal remained film 13; Au coating uses as the underseal of the remaining coat of metal of protection in etching solution, uses for the corrosion resistance that reaches the coating pattern as the Cu-Sn alloy-layer of barrier layer (barrier layer).
Particularly, used the Cu-Sn alloy as barrier layer in the present invention, it is used to replace Ni layer in the past, has nonmagnetic feature.About by the above-mentioned non magnetic characteristic of bringing, will narrate in the back.
The execution mode of above-mentioned A-1 and A-2 only is the part in the illustration preferred implementation of the present invention, should understand the barrier layer that the present invention can also use in the past in the same old way and electroplate/the laminated metal layer except above-mentioned execution mode.For example, can be presented as following numerous embodiments: the mode of gold (Au)-nickel (Ni)-Jin (Au) and gold (Au)-nickel (Ni)-copper (Cu)-nickel (Ni)-Jin (Au), perhaps palladium (Pd)-nickel (Ni)-palladium (Pd) and palladium (Pd)-nickel (Ni)-copper (Cu)-nickel (Ni)-palladium (Pd), gold (Au)-palladium (Pd)-signal bronze layer (Cu-Sn alloy-layer)-palladium (Pd)-Jin (Au) and gold (Au)-palladium (Pd)-nickel (Ni)-palladium (Pd) etc.
Here, should think by the metal level that the metal or metal alloy of above-mentioned Au, Pd, Cu, Ni, Cu-Sn alloy etc. constitutes, it not only comprises above-mentioned metal or metal alloy with the situation that 100% content constitutes, and comprises that also comprising above-mentioned metal or metal alloy can have the above situation of the content of function of coating of semiconductor-sealing-purpose substrate, promptly also comprise situation as other material of trace impurity in above-mentioned metal level except above-mentioned metallics.
Fig. 2 d illustrates the accompanying drawing that encapsulation forms step S30.Shown in Fig. 2 d, encapsulation forms step S30 and carries out as follows: at the tube core contact pad 21 that is formed by the pattern step S20 contact semiconductor chip 30 that powers on, be electrically connected after contact pads 22 and the semiconductor chip 30 with metal fine 40, seal the encapsulation that comprises semiconductor chip 30 and metal level 20, metal fine 40 with moulding resin 50 together.
Then, observe strip step S40.Shown in Fig. 2 e, strip step S40 utilizes to provide the conductivity release film of using among the step S10 12 at framework, peels off the step of the carrier frame 11 that comprises conductivity release film 12 from the metallic film 13 that is formed with semiconductor packages on the surface.By this step, the thickness of the semiconductor packages of integral body can be fabricated to below the 200 μ m.
As mentioned above, above-mentioned strip step S40 can utilize by appropriate solvent clean the method peeled off, based on the stripping means of laser, based on the mechanicalness stripping means of vacuum, use isoionic stripping means etc.
It is feature of the present invention that utilization provides the importing of the strip step S40 of the conductivity release film 12 that step S10 provides by framework.
In the past, the engraving method of carrier frame such as U.S. Register patent US6,635, such shown in 957 grades, the method of coming the exposed pad metal level by the thicker carrier frame of etching is shown, in Korea S openly speciallys permit communique 2001-62734 number, discloses the grinding component that utilizes grinder etc. grinds the chassis body that is positioned at its bottom surface to the frame parts after resin-sealed method.
But, utilize said method, then producing the raw-material waste of carrier frame reaches owing to excessively using etching solution to cause environmental pollution problems, more very be the problem that operation speed descends, but the present invention can address the above problem a little by adopting the mode of peeling off carrier frame 11 and metallic film 12 easily.
And after strip step S40, the carrier frame 11 that is recovered can utilize again, so be remarkable manufacture method to curtailing expenditure.And then, after strip step S40, the operation of metal remained film 13 is removed in execution by etching, the bottom surface of metal level 20 is exposed, but the thickness of above-mentioned metallic film 13 only is 3-20 μ m, so, saving time and aspect such as resource demonstrates remarkable effect with respect to the carrier frame layer of the etching 130-200 μ m in past.
Have a look the situation of using copper-Xi (Cu-Sn) alloy as the part of above-mentioned metal level 20 below.
When copper-ashbury metal is used as barrier layer, prevent by human body harmful's property problem of using Ni to bring, prevent to constitute the diffusion of the copper of carrier frame 11 or other metal level 20, prevent because the eddy current that uses the Ni as ferromagnetic substance to bring forms, heating and the problem that produces magnetic variation shape, magnetic field thus.
At first, form, studied Cu-Sn two and maintained state diagram for the best of learning the Cu-Sn alloy.Fig. 3 illustrates the accompanying drawing that Cu-Sn two maintains state diagram.
As shown in Figure 3, in the Cu-Sn alloy, the preferred Cu content of the composition content of each element is weight ratio 15-55 weight %, and Sn is 45-85 weight %, and more preferably the zone that is shown in broken lines among Fig. 3 is that Cu content is the interval of weight ratio 25-35 weight % (Sn is 65-75 weight %).
Between the dashed region of above-mentioned Fig. 3, fusing point is 550-690 ℃, along with variations in temperature, has at least five kinds of different phases (L, ε, η, η ', Sn) respectively or simultaneously.In this zone, a plurality of distributions stably in than the scope of broad are therefore along with the phase change in the alloy of exterior temperature change is less relatively.
Below, by embodiment and comparative example, the characteristic variations separately the when metal level of the semiconductor-sealing-purpose substrate that utilizes above-mentioned manufacture method manufacturing is used Cu-Sn alloy and Ni respectively describes.
Embodiment 1
In pattern step S20 based on the manufacture method of above-mentioned semiconductor-sealing-purpose substrate, mode by plating coating copper film (thin film plating) is handled the surface of metallic film 13, and on the surface of metallic film 13, from the inside to surface order successively plating and stacked thickness be the Cu-Sn alloy, the Au of 0.3 μ m of Cu, 5 μ m of Cu-Sn alloy, the 50 μ m of Au, the 5 μ m of 0.3 μ m, finished metal level 20.
Except not carrying out surface treatment, formed metal level 20 by the method identical with embodiment 1 based on plating coating copper film mode.
Comparative example
Replace the Cu-Sn alloy and used beyond the Ni metal, formed metal level 20 by the method identical with embodiment 1.
Evaluating characteristics to them is as follows, and the result of wire-bonded, cementability, corrosion resistance, magnetic characteristic is organized in (table 1).
The wire-bonded test
Utilize wire-bonded device engagement examination detailed after, utilize to engage pull test instrument (bondingpull tester) and carried out gold wire and engage experiment.
The cementability experiment
With sample after 170 ℃ of following plastic packagings of plastic packaging temperature 90 seconds, 175 ℃ of following heat treatments 6 hours, use by MRT (test of Moisture Resistance Test moisture-proof) enforcement epoxy-plastic packaging compound and semiconductor device manufacturing after the cementability experiment of substrate, by SAT (ScanningAcoustic: the sound wave sweep test) check and make the cementability of using between the substrate.
Corrosion resistance test
Test according to KS M 8012 neutral salt spray spray testing methods, the concentration of sodium chloride is 40g/l, and pressure of compressed air is 1.2kgf/cm
2, spray amount is 1.51ml/80cm
3/ h, saturation of the air actuator temperature are 47 ℃, and the temperature of saline slot is 35 ℃, and the test flume temperature is 35 ℃.Anti-fragility resistance change rate be 10% with interior, when not having short circuit, insulation breakdown, be evaluated as outstanding.
Magnetic characteristic
To each metal level of making by embodiment 1 and comparative example, utilize VSM (VibratingSample Magnetometer Lakeshore 7407: vibrating specimen magnetometer), apply under the 20kOe of magnetic field in maximum and to measure.If have magnetizability, then be expressed as zero, do not detect magnetizability, then be expressed as *.This be the results are shown in Fig. 4 a and Fig. 4 b.Fig. 4 a is that Fig. 4 b illustrates the magnetic resume curve chart of the metal level of making by comparative example by the magnetic resume curve of the metal level of embodiment 1 manufacturing.
Coefficient of thermal expansion
For the metal level of making by embodiment 1 and comparative example respectively, promptly 100 ℃ of the general operating limit temperature from normal temperature to the semiconductor element, (Thermo-MechanicalAnalysis: thermomechanical analyzer) analysis is measured by TMA.
This be the results are shown in Fig. 5 a and Fig. 5 b.Fig. 5 a is the curve chart by the coefficient of thermal expansion of the wiring pattern of embodiment 1 manufacturing, and Fig. 5 b is the curve chart by the coefficient of thermal expansion of the wiring pattern of comparative example manufacturing.
(table 1)
Zero: magnetizability is arranged, *: no magnetizability
If observe the result of the test that obtains by above-mentioned attribute testing, aspect wire-bonded characteristic, cementability, corrosion resistance, embodiment 1,2 and comparative example all illustrate identical characteristic, but aspect magnetizability, under the situation of comparative example, as was expected illustrates the characteristic that coating is magnetized.To this, the magnetic resume curve of comparison diagram 4a and Fig. 4 b describes particularly.
Magnetic resume curve shown in comparison diagram 4a and Fig. 4 b, under the situation of the comparative example shown in Fig. 4 b, demonstrate the resume curve of typical ferromagnetism body, opposite, under the situation of embodiment 1 shown in Fig. 4 a and embodiment 2, the characteristic that demonstrates typical normal magnetic is promptly non magnetic.
Based on this result, can expect that the coating of semiconductor-sealing-purpose substrate of the present invention generates heat because of external electromagnetic field or the possibility of signal obstacle is a lot of less.
In addition, from the coefficient of thermal expansion curve shown in Fig. 5 a and Fig. 5 b as can be known, lower than routine based on the comparison coefficient of thermal expansion based on the coefficient of thermal expansion of embodiment.This result is illustrated in the situation of using the Cu-Sn alloy in the final semiconductor packages assembling process and compares with the situation of using Ni, and stress generation and the distortion that causes thus or the possibility of being chapped from the cold are littler.
Interest field of the present invention is not limited to the foregoing description, can be presented as the embodiment of multiple mode in appended Patent right requirement scope.In the Patent right requirement scope, the those of ordinary skill of the technical field under the present invention does not break away from the purport of the present invention of being asked and deformable scope also should be interpreted as to be included in the request scope of the present invention.
Claims (14)
1. the manufacture method of a semiconductor-sealing-purpose substrate is utilized release film, it is characterized in that, comprising:
Framework provides step, the conductivity release film is placed between carrier frame and the metallic film make frame parts;
Pattern step is utilized photoresist a plurality of metal levels of plating on above-mentioned metallic film, thereby forms predetermined pattern;
Encapsulation forms step, on above-mentioned metal level semiconductor chip is set, and seals above-mentioned semiconductor chip and metal level with moulding resin; And
Strip step is utilized above-mentioned conductivity release film, peels off above-mentioned conductivity release film and carrier frame from above-mentioned metallic film.
2. the manufacture method of semiconductor-sealing-purpose substrate as claimed in claim 1 is characterized in that, above-mentioned carrier frame utilizes metal or engineering plastics.
3. the manufacture method of semiconductor-sealing-purpose substrate as claimed in claim 1 is characterized in that,
The thickness of above-mentioned metallic film is 3 μ m to 20 μ m.
4. the manufacture method of semiconductor-sealing-purpose substrate as claimed in claim 1 is characterized in that,
In above-mentioned pattern step, metal level is with the sequential cascade of Au layer, Cu-Sn alloy-layer, Au layer.
5. the manufacture method of semiconductor-sealing-purpose substrate as claimed in claim 1 is characterized in that,
In above-mentioned pattern step, metal level is with the sequential cascade of Au layer, Cu-Sn alloy-layer, Cu layer, Cu-Sn alloy-layer, Au layer.
6. the manufacture method of semiconductor-sealing-purpose substrate as claimed in claim 1 is characterized in that,
In above-mentioned pattern step, metal level is with the sequential cascade of Au layer, Ni layer, Au layer.
7. the manufacture method of semiconductor-sealing-purpose substrate as claimed in claim 1 is characterized in that,
In above-mentioned pattern step, metal level is with the sequential cascade of Au layer, Ni layer, Cu layer, Ni alloy-layer, Au layer.
8. the manufacture method of semiconductor-sealing-purpose substrate as claimed in claim 1 is characterized in that,
In above-mentioned pattern step, metal level is with the sequential cascade of Au layer, Pd layer, Cu-Sn alloy-layer, Pd layer.
9. the manufacture method of semiconductor-sealing-purpose substrate as claimed in claim 1 is characterized in that,
In above-mentioned pattern step, metal level is with the sequential cascade of Au layer, Pd layer, Ni layer, Pd layer.
10. a semiconductor-sealing-purpose coat of metal is formed a plurality of electrodes by plating on metallic film, it is characterized in that,
The above-mentioned coat of metal comprises the Cu-Sn alloy.
11. the semiconductor-sealing-purpose coat of metal as claimed in claim 10 is characterized in that,
The above-mentioned coat of metal forms with the sequential cascade of Au layer, Cu-Sn alloy-layer, Au layer.
12. the semiconductor-sealing-purpose coat of metal as claimed in claim 10 is characterized in that,
The above-mentioned coat of metal forms with the sequential cascade of Au layer, Cu-Sn alloy-layer, Cu layer, Cu-Sn alloy-layer, Au layer.
13. the semiconductor-sealing-purpose coat of metal as claimed in claim 10 is characterized in that,
The above-mentioned coat of metal forms with the sequential cascade of Au layer, Pd layer, Cu-Sn alloy-layer, Pd layer.
14. any one the described semiconductor-sealing-purpose coat of metal as in the claim 10 to 13 is characterized in that,
The alloy ratio of above-mentioned Cu-Sn alloy is that the weight ratio of 15-55 weight %, Sn is that 45-85 weight % constitutes according to the weight ratio of Cu.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080005286A KR100930965B1 (en) | 2008-01-17 | 2008-01-17 | Method of manufacturing substrate for semiconductor package and metal plating layer manufactured using same |
| KR1020080005286 | 2008-01-17 |
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| Publication Number | Publication Date |
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| CN101488463A true CN101488463A (en) | 2009-07-22 |
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| CNA2008100062731A Pending CN101488463A (en) | 2008-01-17 | 2008-02-04 | Production method of substrate for semiconductor parcage, and metal plating produced by the same |
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| KR (1) | KR100930965B1 (en) |
| CN (1) | CN101488463A (en) |
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| WO2019076321A1 (en) * | 2017-10-19 | 2019-04-25 | 京东方科技集团股份有限公司 | Package structure and packaging method, electronic device and packaging film recycling method |
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|---|---|---|---|---|
| JP3650596B2 (en) * | 2001-09-03 | 2005-05-18 | 新光電気工業株式会社 | Manufacturing method of semiconductor device |
| JP5113346B2 (en) * | 2006-05-22 | 2013-01-09 | 日立電線株式会社 | Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof |
-
2008
- 2008-01-17 KR KR1020080005286A patent/KR100930965B1/en not_active IP Right Cessation
- 2008-02-04 CN CNA2008100062731A patent/CN101488463A/en active Pending
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Also Published As
| Publication number | Publication date |
|---|---|
| KR100930965B1 (en) | 2009-12-10 |
| KR20090079370A (en) | 2009-07-22 |
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