CN111834322B - 半导体封装用夹具结构体及包括其的半导体封装件 - Google Patents

半导体封装用夹具结构体及包括其的半导体封装件 Download PDF

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CN111834322B
CN111834322B CN202010089653.7A CN202010089653A CN111834322B CN 111834322 B CN111834322 B CN 111834322B CN 202010089653 A CN202010089653 A CN 202010089653A CN 111834322 B CN111834322 B CN 111834322B
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main metal
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jig structure
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CN111834322A (zh
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崔伦华
金泳勋
李泰宪
赵廷焄
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Jmj Korea Co ltd
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Abstract

本发明涉及半导体封装用夹具结构体，更具体地，涉及由相互不同的材质的金属层构成适用于半导体封装的夹具结构体的材质，而不由单一金属构成，从而降低将以往无法适用的低费用、轻量材质的金属适用而制造的半导体封装件的价格，并可实现轻量化的半导体封装用夹具结构体。即，在本发明的半导体封装件内将封装件的结构进行电连接的夹具结构体，其特征在于，上述夹具结构体包括：主金属层，维持夹具结构体的形状；第一功能层，层叠于上述主金属层的一侧面，并适用与主金属层不同的种类的金属；第一接合层，形成于上述第一功能层与主金属层之间，适用可使第一功能层接合于主金属层的金属。

Description

半导体封装用夹具结构体及包括其的半导体封装件
技术领域
本发明涉及半导体封装用夹具结构体及包括其的半导体封装件，更具体地，涉及由相互不同的材质的金属层构成适用于半导体封装的夹具结构体的材质，而不由单一金属构成，从而降低将以往无法适用的低费用、轻量材质的金属适用而制造的半导体封装件的价格，并可实现轻量化的半导体封装用夹具结构体及包括其的半导体封装件。
背景技术
通常，半导体封装件包括半导体芯片、引线框架、封装件本体而构成，半导体芯片附着于引线框架的垫上，并将金属丝和引线框架的引脚进行键合(bonding)来实现电连接。
但是，利用以往的金属丝的堆栈封装通过金属丝实现电信号交换，因而速度慢，并使用多数的金属丝，从而各个芯片中发生电特性劣化。并且，为了形成金属丝，基板需要追加面积，从而增加封装的大小，并需要用于在各个芯片的键合垫键合金属丝的间隙(Gap)，因而存在封装的整体高度不必要地变高的问题。
因此，在由本发明人公开的韩国授权专利第1208332号、韩国授权实用新型第0482370号、韩国授权专利第1669902号及韩国授权专利第1631232号中提供利用金属的夹具(clip)结构体相比于利用以往的金属丝的半导体封装件更优秀的电连接性能、热稳定性好，热释放容易并有效的封装结构。
并且，现有的夹具结构体为了焊接而适用铜材质，但是因铜材质特性而存在夹具的成本高且重量大的问题。这种问题与使用半导体芯片封装件的各种电子产品的制造费用上涨有关，夹具的重量对于如同智能手机一样在轻量化方面上投资很多费用的产品而言是非常重要的问题。
发明内容
本发明是为了解决如上所述的问题而提出的，涉及构成夹具结构体时，将主金属层的材质适用低费用、轻量化的金属，在实现电连接的部分适用导电性优秀的金属来降低半导体封装件的价格及重量，并使电连接特性变好的半导体封装用夹具结构体及包括其的半导体封装件。
在本发明的半导体封装件内将封装件的结构进行电连接的夹具结构体，其特征在于，上述夹具结构体包括：主金属层，维持夹具结构体的形状；第一功能层，层叠于上述主金属层的一侧面，并适用与主金属层不同的种类的金属；第一接合层，形成于上述第一功能层与主金属层之间，适用可使第一功能层接合于主金属层的金属。
并且，本发明的特征在于，上述第一功能层的厚度薄于主金属层的厚度。
并且，本发明的特征在于，上述主金属层由铝(Al)材质的单一金属形成。
并且，本发明的特征在于，在上述主金属层中，铝(Al)以主金属层的总重量比为基准由50％以上形成，剩余为包含铜(Cu)、镁(Mg)、镍(Ni)、钯(Pd)、银(Ag)、金(Au)、锰(Mn)、锌(Zn)、硅(Si)、铬(Cr)、钛(Ti)中的一种以上的金属合金。
并且，本发明的特征在于，上述第一功能层由铜(Cu)材质的单一金属形成。
并且，本发明的特征在于，在上述第一功能层中，铜(Cu)以第一功能层的总重量比为基准由50％以上形成，剩余为包含铝(Al)、银(Ag)、铁(Fe)、金(Au)、钯(Pd)、镍(Ni)、锡(Sn)、铅(Pb)中的一种以上的金属合金。
并且，本发明的特征在于，上述第一接合层适用镍(Ni)或钛(Ti)。
并且，本发明的特征在于，还包括：第二功能层，层叠于上述主金属层的另一侧面，并适用与主金属层不同的种类的金属；第二接合层，形成于上述第二功能层与主金属层之间，适用可使第二功能层接合于主金属层的金属。
根据本发明一实施例的半导体封装件，其特征在于，包括：引线框架，由一个以上的垫和一个以上的引线端子构成；一个以上的半导体芯片，安装于上述垫；夹具结构体，将上述半导体芯片与上述引线端子进行电连接；以及封装件本体，能够通过成型保护上述半导体芯片的周边，上述夹具结构体为前述的半导体封装用夹具结构体。
本发明在构成夹具结构体时，将主金属层的材质适用低费用、轻量化的金属，层叠于主金属层的功能层的实现电连接的部分适用导电性优秀的金属，由此具有降低半导体封装件的价格及重量，且电连接特性优秀的效果。
并且，本发明在将铝作为主成分的主金属层与将铜作为主成分的功能层之间设置用于使两个金属层之间容易接合的接合层，从而具有可坚固地维持功能层的接合状态的效果。
附图说明
图1为表示本发明的半导体封装用夹具结构体的图。
图2为表示本发明的夹具结构体适用于半导体封装件的示例的图。
图3为表示本发明的半导体封装用夹具结构体的另一实施例的图。
附图标记的说明
10：夹具结构体 20：引线框架
30：半导体芯片 40：封装件本体
100：主金属层 200：第一功能层
300：第一接合层 400：第二功能层
500：第二接合层
具体实施方式
以下，参照附图，如下详细说明本发明的优选实施例。并且，在说明本发明的过程中，当判断相关公知功能或结构的具体说明有可能不必要地混淆本发明的要旨时，省略其详细说明。
在本发明的半导体封装件内将封装件的结构进行电连接的夹具结构体10，其特征在于，上述夹具结构体10的结构包括：主金属层100，维持夹具结构体10的形状；第一功能层200，层叠于上述主金属层100的一侧面，并适用与主金属层100不同的种类的金属；第一接合层300，形成于上述第一功能层200与主金属层100之间，适用可使第一功能层200接合于主金属层100的金属。
本发明的技术特征为将维持整体形状的主金属层100的材质适用低费用、轻量化的金属，在第一功能层200的实现电连接的部分适用导电性优秀的金属来降低半导体封装件的价格及重量，并使电连接特性变好的技术。
因此，上述第一功能层200的厚度薄于主金属层100的厚度。优选地，上述主金属层100的厚度由25μm(微米)至2mm(毫米)的厚度形成，上述第一功能层200由薄于其的0.05μm(微米)至15μm(微米)的厚度形成为宜。
上述主金属层100的材质可由铝(Al)材质的单一金属形成，包含最多的铝(Al)，并可与另一金属形成为混合物。即，铝(Al)能够以主金属层100的总重量比为基准由50％以上形成，剩余可由包含铜(Cu)、镁(Mg)、镍(Ni)、钯(Pd)、银(Ag)、金(Au)、锰(Mn)、锌(Zn)、硅(Si)、铬(Cr)、钛(Ti)中的一种以上的金属合金形成。
像这样，将铝作为主成分构成主金属层100时，与仅由铜材质形成的现有技术相比，可降低夹具结构体10的价格，且可实现轻量化。但是，铝材质的主金属层100因材质的特性而难以焊接，且电连接特性差的问题，至今根本未被适用，通过本发明的第一功能层200解决这种问题。
上述第一功能层200可由铜(Cu)材质的单一金属形成，包含最多的铜，并可与另一金属形成为混合物。即，铜(Cu)能够以第一功能层200的总重量比为基准由50％以上形成，剩余可由包含铝(Al)、银(Ag)、铁(Fe)、金(Au)、钯(Pd)、镍(Ni)、锡(Sn)、铅(Pb)中的一种以上的金属合金形成。并且，上述第一功能层200可由单一材质形成或者由不同的材质的2层以上形成。
并且，上述第一接合层300为形成于第一功能层200与主金属层100之间，可使第一功能层200容易接合于主金属层100的金属层。由于材质的特性，无法接合将铜作为主成分的第一功能层200和将铝作为主成分的主金属层100，因而必须要构成第一接合层300。
上述第一接合层300适用镍(Ni)或钛(Ti)，优选地，其厚度薄于第一功能层200。上述第一接合层300的厚度由0.01至4μm(微米)形成为宜。
若由镍之类的单一金属构成第一功能层200，而不是将铜作为主成分时，即使额外的接合层不存在，形成第一功能层200时也不存在问题，但在仅由镍之类的金属构成第一功能层200的情况下，在下一工序中通过EMC成型构成封装件本体40时，产生镍层被剥离的问题。
在构成本发明的夹具结构体10的材质的优选第一个实施例中，主金属层100适用铝，第一功能层200适用铜，第一接合层300适用镍。并且，在优选第二个实施例中，主金属层100适用铝，第一功能层200适用铜，第一接合层300适用钛。
如此形成的夹具结构体10如图2所示可适用于如下半导体封装件，其包括：引线框架20，由垫和多个引线端子构成；一个以上的半导体芯片30，安装于上述垫；夹具结构体，将上述半导体芯片30与引线端子进行电连接；以及封装件本体40，可通过成型保护上述半导体芯片30的周边。上述的结构为适用本发明的夹具结构体的一例，尽管适用于多种形态的封装结构。
而且，由于以往的夹具结构体10的材质为铜，因而为了在夹具结构体10上部接合键合金属丝，则存在必须仅对接合部分先行追加的镀银(Ag)或镀金(Au)的问题，但是本发明由于主金属层100由铝材质形成，因而具有在无需额外的镀银/镀金的情况下容易实现键合金属丝(B-W)的接合的优点。
图3表示本发明的另一实施例，上述实施例的特征在于，还包括：第二功能层400，层叠于上述主金属层100的另一侧面，并适用与主金属层100不同的种类的金属；第二接合层500，形成于上述第二功能层400与主金属层100之间，从而适用可使第二功能层400接合于主金属层100的金属。
上述实施例为在第一功能层200的相反侧还包括第二功能层400的实施例，是在主金属层100上部连接另一封装结构时适用的实施例。上述第二功能层400也具有与第一功能层200相同的结构特征，是在第二功能层400与主金属层100之间通过第二接合层500接合第二功能层400的结构。
即，上述第二功能层400可将铜(Cu)材质的单一金属或铜(Cu)作为主成分，并与其他金属形成为混合物，上述第二接合层500适用镍(Ni)或钛(Ti)。并且，上述第二功能层400可由单一材质形成或者由不同的材质的2层以上形成。
由于上述第二功能层400及第二接合层500的结构特征与第一功能层200及第一接合层300相同，因而省略功能性说明及与适用材质相关的重复说明。
本发明适用于结构效果突出的夹具结构体10而说明，但对于仅由以往的铜材质形成的引线框架而言，也可依然适用本发明的主金属层100、第一功能层200及第一接合层300的结构。
以上，参照上述实施例来说明本发明，显然，在本发明的技术思想范围内可实施多种变形。

Claims (7)

1.一种半导体封装用夹具结构体，其为在半导体封装件的内部将封装件的结构进行电连接的夹具结构体(10)，其特征在于，所述半导体封装用夹具结构体(10)包括：
主金属层(100)，维持夹具结构体(10)的形状；
第一功能层(200)，层叠于所述主金属层(100)的一侧面，并适用与主金属层(100)不同的种类的金属；
第一接合层(300)，形成于所述第一功能层(200)与主金属层(100)之间，适用能够使第一功能层(200)接合于主金属层(100)的金属，
其中，所述第一功能层(200)的厚度薄于主金属层(100)的厚度，
在所述主金属层(100)中，铝以主金属层(100)的总重量比为基准由50％以上形成，
在所述第一功能层(200)中，铜以第一功能层(200)的总重量比为基准由50％以上形成，使得所述主金属层(100)相比于所述第一功能层(200)以轻量材质构成，
所述第一接合层(300)适用镍或钛。
2.根据权利要求1所述的半导体封装用夹具结构体，其特征在于，所述主金属层(100)由铝材质的单一金属形成。
3.根据权利要求1所述的半导体封装用夹具结构体，其特征在于，在所述主金属层(100)是金属合金，其中除了铝以外的剩余为包含铜、镁、镍、钯、银、金、锰、锌、硅、铬、钛中的一种以上。
4.根据权利要求1所述的半导体封装用夹具结构体，其特征在于，所述第一功能层(200)由铜材质的单一金属形成。
5.根据权利要求1所述的半导体封装用夹具结构体，其特征在于，在所述第一功能层(200)是金属合金，其中除了铜以外的剩余为包含铝、银、铁、金、钯、镍、锡、铅中的一种以上。
6.根据权利要求1所述的半导体封装用夹具结构体，其特征在于，还包括：
第二功能层(400)，层叠于所述主金属层(100)的另一侧面，并适用与主金属层(100)不同的种类的金属；
第二接合层(500)，形成于所述第二功能层(400)与主金属层(100)之间，适用能够使第二功能层(400)接合于主金属层(100)的金属。
7.一种半导体封装件，其特征在于，
包括：
引线框架，由一个以上的垫和一个以上的引线端子构成；
一个以上的半导体芯片，安装于所述垫；
夹具结构体，将所述半导体芯片与所述引线端子进行电连接；以及
封装件本体，能够通过成型保护所述半导体芯片的周边，
所述夹具结构体为权利要求1至6中任一项所述的半导体封装用夹具结构体。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1851914A (zh) * 2006-05-29 2006-10-25 朱冬生 一种引线框架以及具有所述引线框架的半导体器件
CN101345275A (zh) * 2007-07-10 2009-01-14 晶元光电股份有限公司 发光元件
CN101488463A (zh) * 2008-01-17 2009-07-22 阿克泰克萨特株式会社 半导体封装用基板的制造方法及利用它来制造的金属镀层
CN101488539A (zh) * 2008-01-17 2009-07-22 晶元光电股份有限公司 发光元件
CN102354722A (zh) * 2008-05-26 2012-02-15 晶元光电股份有限公司 高功率发光装置
CN105845672A (zh) * 2016-06-15 2016-08-10 南通富士通微电子股份有限公司 封装结构
KR20180084588A (ko) * 2017-01-17 2018-07-25 주식회사 네패스 반도체 패키지의 제조 방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014112581A (ja) * 2012-12-05 2014-06-19 Nippon Micrometal Corp ボンディングワイヤ及びボンディングリボン
KR20190007936A (ko) * 2017-07-14 2019-01-23 제엠제코(주) 복합 클립 구조체 및 이를 이용한 반도체 패키지

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1851914A (zh) * 2006-05-29 2006-10-25 朱冬生 一种引线框架以及具有所述引线框架的半导体器件
CN101345275A (zh) * 2007-07-10 2009-01-14 晶元光电股份有限公司 发光元件
CN101488463A (zh) * 2008-01-17 2009-07-22 阿克泰克萨特株式会社 半导体封装用基板的制造方法及利用它来制造的金属镀层
CN101488539A (zh) * 2008-01-17 2009-07-22 晶元光电股份有限公司 发光元件
CN102354722A (zh) * 2008-05-26 2012-02-15 晶元光电股份有限公司 高功率发光装置
CN105845672A (zh) * 2016-06-15 2016-08-10 南通富士通微电子股份有限公司 封装结构
KR20180084588A (ko) * 2017-01-17 2018-07-25 주식회사 네패스 반도체 패키지의 제조 방법

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