CN111830330A - Detection circuit for specific frequency signal - Google Patents
Detection circuit for specific frequency signal Download PDFInfo
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- CN111830330A CN111830330A CN202010492423.5A CN202010492423A CN111830330A CN 111830330 A CN111830330 A CN 111830330A CN 202010492423 A CN202010492423 A CN 202010492423A CN 111830330 A CN111830330 A CN 111830330A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0276—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being rise time
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Abstract
The application provides a detection circuit of specific frequency signal, includes: the processing module is used for processing the specific frequency signal to be detected based on the preset clock signal and the preset width setting signal and outputting a forming signal. The detection module is used for detecting the rising edge or the falling edge of the forming signal and outputting a rising edge effective signal or a falling edge effective signal. The timing module is used for counting the number of the periods of the preset clock signals correspondingly received by the adjacent rising or falling edge effective signals in the forming signals and is matched with the timing holding module to output a timing holding value. The judging module is used for determining whether the output frequency judging signal is effective or not according to the timing holding value and the set threshold value. The counting processing module is used for delaying a preset clock signal period to receive the frequency judgment signal at the effective signal of the rising edge or the falling edge, and determining whether the output frequency detection result is effective or not according to the frequency judgment signal and the preset detection period value.
Description
Technical Field
The present invention relates to the field of signal detection technology, and in particular, to a detection circuit for a specific frequency signal.
Background
The low-power-consumption specific frequency signal comprises one or more high-level pulses in a half period, the high-level duration of each pulse is not fixed, but the high-level duration of at least one pulse is larger than Ts; and the low power consumption specific frequency signal is always at a high level at the beginning of a half period and is always at a low level at the end of the half period.
One period of the low power consumption specific frequency signal is shown in fig. 1, where a-c represents a length of a half period, and a-d represents a length of one period (referred to as Tp). The length between a-b is called Th, which represents the maximum length that a high level pulse may have. I.e. there may be high pulses between a-b in the high representation method and there must not be high pulses between b-c. The low level in the specific frequency signal indicates that no high level pulse exists in a half period.
The detection of the low-power specific frequency signal is an urgent problem to be solved at present.
Disclosure of Invention
In view of this, it is necessary to provide a detection circuit capable of detecting the low-power consumption specific frequency signal.
A detection circuit for a specific frequency signal, comprising:
the input end of the processing module is used for inputting a specific frequency signal to be detected, and is used for processing the specific frequency signal to be detected based on a preset clock signal and a preset width setting signal and outputting a forming signal;
the detection module is electrically connected with the processing module and used for detecting the rising edge or the falling edge of the forming signal according to the preset clock signal and outputting a rising edge or falling edge effective signal;
the timing module is electrically connected with the detection module and used for counting the number of the periods of the preset clock signals correspondingly received by the adjacent effective signals of the rising edge or the falling edge in the forming signals and outputting a first count value;
the timing and holding module is respectively electrically connected with the timing module and the detection module and is used for receiving and storing the first count value when the effective signal of the rising edge or the falling edge is effective based on the preset clock signal and outputting the stored timing and holding value;
the judging module is electrically connected with the timing holding module and is used for determining whether the output frequency judging signal is valid or not according to the timing holding value and a set threshold value; and
and the counting processing module is respectively electrically connected with the judging module and the detecting module and is used for delaying one preset clock signal period based on the effective signal of the preset clock signal on the rising edge or the falling edge to receive the frequency judging signal and determining whether the output frequency detection result is effective according to whether the frequency judging signal is effective and a preset detection period value.
In one embodiment, if the frequency decision signal received by the count processing module is a valid signal, a second count value of the count processing module is added up;
and if the frequency judgment signal received by the counting processing module is an invalid signal, clearing a second count value of the counting processing module.
In one embodiment, when the second count value of the counting module reaches the preset detection period value, the frequency detection result output by the counting module is valid.
In one embodiment, the counting module is electrically connected with the timing module;
the timing module is further configured to determine whether the first count value exceeds a maximum countable range thereof, and if the first count value exceeds the maximum countable range, the timing module outputs a timing value invalid signal to the timing keeping module and the count processing module.
In one embodiment, when the timing holding module receives the timing value invalid signal, the timing holding module clears the timing holding value;
when the counting processing module receives the timing value invalid signal, the counting processing module clears the second counting value.
In one embodiment, when the timing keeping module receives the first count value or the timing module outputs the timing value invalid signal, the timing module clears the first count value and counts again.
In one embodiment, the judging module receives the timing keeping value and determines whether the timing keeping value is within the set threshold value range;
if the timing holding value is determined to be within the set threshold range, the frequency judgment signal output by the judgment module is valid;
if the timing holding value is determined not to be within the set threshold range, the frequency judgment signal output by the judgment module is invalid;
and the set threshold is set according to the cycle length setting signal and the cycle fault tolerance setting signal of the specific frequency signal to be detected.
In one embodiment, the processing module comprises:
the buffer module comprises N cascaded D triggers, and is used for shifting and buffering the specific frequency signal to be detected through each level of D triggers according to the rising edge or the falling edge of the preset clock signal and outputting a tap signal delayed by each level of D triggers; and
a first input end of the high-level widening module is electrically connected with an output end of the cache module, and a second input end of the high-level widening module is used for inputting the preset width setting signal and outputting the forming signal according to the tap signals of each level and the preset width setting signal;
and N is an integer greater than N, and is greater than the ratio of the period of the specific frequency signal to be detected to the period of the preset clock signal.
In one embodiment, the detection module comprises:
a first input end of the trigger is electrically connected with an output end of the processing module, and a second input end of the trigger is used for inputting the preset clock signal;
the input end of the NOT gate is electrically connected with the output end of the trigger; and
and the first input end of the AND gate is electrically connected with the output end of the processing module, the second input end of the AND gate is electrically connected with the output end of the NOT gate, and the output end of the AND gate is used for outputting the effective rising or falling edge signal to the timing module.
In one embodiment, the count processing module includes:
a delay module, a first input end of which is electrically connected to an output end of the detection module, a second input end of which is used for inputting the preset clock signal, and which is used for delaying the effective rising or falling edge signal by one preset clock signal period based on the preset clock signal and outputting the effective rising or falling edge delay signal; and
and the counting module is respectively electrically connected with the judging module and the output end of the delay module, and is used for receiving the frequency judging signal when the rising edge effective delay signal or the falling edge effective delay signal is effective based on the preset clock signal and determining whether the output frequency detection result is effective according to whether the frequency judging signal is effective and the preset detection period value.
Compared with the prior art, the detection circuit of the specific frequency signal processes the specific frequency signal to be detected through the processing module based on the preset clock signal and the preset width setting signal and outputs the forming signal to the detection module, and the detection module is used for detecting the rising edge or the falling edge of the forming signal and outputting a rising edge or falling edge effective signal; counting the number of periods of the preset clock signals correspondingly received by the adjacent rising or falling edge effective signals in the forming signals through a timing module, and outputting a timing holding value to a judging module by matching with the timing holding module so as to determine whether the frequency judging signal is effective or not; and then, determining whether the output frequency detection result is effective or not through the counting processing module according to whether the frequency judgment signal is effective or not and the preset detection period value, thereby realizing the power consumption detection function of the low specific frequency signal.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a specific frequency signal according to an embodiment of the present application;
fig. 2 is a circuit block diagram of a specific frequency signal detection circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of a cache module according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of a high-level stretching module according to an embodiment of the present application;
FIG. 5 is a schematic circuit diagram of a detection module according to an embodiment of the present disclosure;
fig. 6 is a circuit diagram of a delay module according to an embodiment of the present application.
Description of reference numerals:
10 specific frequency signal detection circuit
100 processing module
110 cache module
111D trigger
120 high level widening module
121 OR gate circuit
122 selection circuit
200 detection module
210 flip-flop
220 NOT gate
230 AND gate
300 timing module
400 timing keeping module
500 judging module
600 count processing module
610 delay module
620 counting module
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the embodiments disclosed below.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 2, an embodiment of the present application provides a circuit 10 for detecting a specific frequency signal, including: the system comprises a processing module 100, a detection module 200, a timing module 300, a timing keeping module 400, a judgment module 500 and a counting processing module 600. The input end of the processing module 100 is used for inputting a specific frequency signal to be detected. The processing module 100 is configured to process the specific frequency signal to be detected based on a preset clock signal and a preset width setting signal and output a forming signal. The detection module 200 is electrically connected to the processing module 100. The detection module 200 is configured to detect a rising edge or a falling edge of the molding signal according to the preset clock signal and output a rising edge or a falling edge valid signal. The timing module 300 is electrically connected to the detection module 200. The timing module 300 is configured to count the number of periods of the preset clock signal correspondingly received by the adjacent rising or falling edge valid signal in the molding signal, and output a first count value.
The timing maintaining module 400 is electrically connected to the timing module 300 and the detecting module 200, respectively. The timing keeping module 400 is configured to receive and keep the first count value when the rising or falling edge valid signal is valid based on the preset clock signal, and output a kept timing value. The determination module 500 is electrically connected to the timing keeping module 400. The judging module 500 is configured to determine whether the output frequency decision signal is valid according to the timing hold value and a set threshold. The counting processing module 600 is electrically connected to the judging module 500 and the detecting module 200, respectively. The counting processing module 600 is configured to delay the receiving of the frequency decision signal by one preset clock signal period based on the valid signal of the preset clock signal on the rising or falling edge, and determine whether the output frequency detection result is valid according to whether the frequency decision signal is valid and a preset detection period value.
It is understood that the specific structure of the processing module 100 is not limited as long as the processing module has the function of processing the signal with the specific frequency to be detected and outputting a forming signal based on a preset clock signal and a preset width setting signal. In one embodiment, the processing module 100 may include a buffer module 110 and a high-level stretching module 120. Specifically, as shown in fig. 3, the cache module 110 may include N cascaded D flip-flops 111. And N is an integer greater than 1 and is greater than the ratio of the period of the specific frequency signal to be detected to the period of the preset clock signal.
In one embodiment, the buffer module 110 may be triggered by an edge (i.e., a rising edge or a falling edge) of the predetermined clock signal. When the preset clock signal is input to the buffer module 110, that is, when the D flip-flops 111 at each stage all receive the edge trigger signal of the preset clock signal, the D flip-flops 111 at each stage shift and buffer the specific frequency signal to be detected, and the D flip-flops 111 at each stage output delayed tap signals corresponding to the specific frequency signal. Specifically, as shown in fig. 3, each stage of the D flip-flop 111 outputs a tap signal corresponding thereto. For example, D flip-flop 1 outputs tap signal 1 and D flip-flop 2 outputs tap signal 2 … … D flip-flop N outputs tap signal N.
In one embodiment, a first input terminal of the high-level stretching module 120 is electrically connected to an output terminal of the buffer module 110. A second input end of the high-level widening module 120 is configured to input the preset width setting signal. The high-level widening module 120 is configured to output the forming signal according to the tap signal at each level and the preset width setting signal. In one embodiment, as shown in fig. 4, the high-level stretching module 120 may include a plurality of or gates 121 and a selection circuit 122. In one embodiment, the or gate circuit 121 may be a logic or gate.
Specifically, two input terminals of any one of the or gates 121 of the plurality of or gates 121 receive the tap signal 1 and the tap signal 2, respectively. Each of the other or gate circuits 121 has one input terminal connected to the output terminal of the adjacent or gate circuit 121, the other input terminal receiving a tap signal, and the tap signal received by each or gate circuit 121 is different. The outputs of the plurality of or gates 121 are each electrically connected to a selection circuit 122, while the selection circuit 122 also directly receives the tap signal 1. For example, an input terminal of the or gate 1 receives the tap signal 1, another input terminal thereof receives the tap signal 2, and an output terminal thereof is electrically connected to the input terminal 2 of the selection circuit 122, an input terminal of the or gate 2 receives the tap signal 3, another input terminal thereof is electrically connected to the output terminal of the or gate 1, an output terminal of the or gate 2 is electrically connected to the input terminal 3 of the selection circuit 122 … …, an input terminal of the or gate N-1 receives the tap signal N, another input terminal thereof is electrically connected to the output terminal of the or gate N-2, and an output terminal of the or gate N-1 is electrically connected to the input terminal N of the selection. Input 1 of selection circuit 122 receives tap signal 1 directly.
In one embodiment, the selection circuit 122 is further configured to receive the preset width setting signal, and determine which of the tap signals is the output shaping signal according to the preset width setting signal. For example, if the preset width setting signal received by the selection circuit 122 is 3, the molding signal output by the output terminal of the selection circuit 122 is the signal received by the input terminal 3 of the selection circuit 122. If the preset width setting signal received by the selection circuit 122 is N, the forming signal output by the output end of the selection circuit 122 is the signal received by the input end N of the selection circuit 122. In an embodiment, a value corresponding to the preset width setting signal should be greater than a difference between a maximum length of a high-level pulse in the specific frequency signal to be detected and a period of the preset clock signal. In one embodiment, the selection circuit 122 is a one-out-of-many selector.
It is understood that the specific structure of the detection module 200 is not limited as long as it has the function of detecting the rising or falling edge of the molding signal and outputting a rising or falling edge valid signal. In one embodiment, the detection module 200 may be composed of a D flip-flop, a not gate, and an and gate. In one embodiment, the detection module 200 may also consist of a rising or falling edge detector. In one embodiment, the detection module 200 may be triggered by an edge (i.e., a rising edge or a falling edge) of the preset clock signal.
In one embodiment, the timing module 300 may be triggered by an edge (i.e., a rising edge or a falling edge) of the predetermined clock signal. When the detection module 200 outputs the rising or falling edge valid signal to the timing module 300, the timing module 300 may count the number of periods of the preset clock signal correspondingly received by the adjacent rising or falling edge valid signal in the molding signal. That is, the timing module 300 may count the number of cycles of the preset clock signal received by the timing module 300 in a time period corresponding to the adjacent effective rising or falling edge signal. Specifically, in a time period corresponding to an adjacent effective rising or falling edge signal in the molding signal, the timing module 300 may count the rising edge or the falling edge of the received preset clock signal and output a first count value.
In one embodiment, the timing and holding module 400 may be triggered by an edge (i.e., a rising edge or a falling edge) of the preset clock signal. When the rising or falling edge valid signal received by the timing and holding module 400 is valid, the timing and holding module 400 may sample and store the first count value output by the timing module 300, and at this time, the timing module 300 automatically clears the first count value and counts again. Meanwhile, the timing keeping module 400 outputs the saved timing keeping value to the determining module 500.
In one embodiment, the determining module 500 receives the timing hold value output by the timing hold module 400, and determines whether the output frequency decision signal is valid according to the timing hold value and the set threshold. Specifically, the determining module 500 may determine whether the timing keeping value is within the set threshold range. If it is determined that the timing hold value is within the set threshold range, the frequency decision signal output by the determining module 500 is valid. If it is determined that the timing hold value is not within the set threshold range, the frequency decision signal output by the determining module 500 is invalid. In one embodiment, the setting threshold may be set according to a period length setting signal and a period fault tolerance setting signal of the specific frequency signal to be detected. Specifically, the range of the set threshold may be from a difference between the period length setting signal and the period fault-tolerant setting signal to a sum of the period length setting signal and the period fault-tolerant setting signal. In one embodiment, the period length setting signal and the period fault tolerance setting signal may be set in advance in the determination module 500 according to actual requirements.
In one embodiment, the count processing module 600 may be composed of a delay and a counter. In one embodiment, the count processing module 600 may be triggered by an edge (i.e., a rising edge or a falling edge) of the preset clock signal. Specifically, after the counting module 600 is triggered, the counting module 600 may receive the frequency decision signal after the rising or falling valid signal is delayed by one period of the predetermined clock signal. If the frequency decision signal received by the count processing module 600 is a valid signal, the second count value in the count processing module 600 is added by 1. If the frequency decision signal received by the count processing module 600 is an invalid signal, the second count value in the count processing module 600 is cleared.
In one embodiment, the preset detection period value may be stored in the count processing module 600 in advance. When the second count value in the counting module 600 reaches the preset detection cycle number, that is, the second count value is equal to the preset detection cycle number, it indicates that the detection circuit 10 of the specific frequency signal detects an effective specific frequency signal, and at this time, the frequency detection result output by the counting module 600 is effective. On the contrary, when the second count value is smaller than the preset detection period value, it indicates that the detection circuit 10 of the specific frequency signal does not detect an effective specific frequency signal, and the frequency detection result output by the count processing module 600 is invalid at this time.
The detection circuit can realize low-power consumption detection of specific frequency signals. The wireless wake-up circuit can be used as a demodulation and decoding circuit to be applied to circuits which need wireless low-power wake-up functions, such as the field of wireless sensor end design in the Internet of things and the Internet of vehicles.
In this embodiment, the processing module 100 processes the signal to be detected with a specific frequency based on the preset clock signal and the preset width setting signal and outputs the forming signal to the detecting module 200, and the detecting module 200 detects the rising or falling edge of the forming signal and outputs a rising or falling edge valid signal; counting the number of cycles of the preset clock signal correspondingly received by the adjacent rising or falling edge effective signal in the forming signal through the timing module 300, and outputting a timing hold value to the judging module 500 in cooperation with the timing hold module 400, thereby determining whether the frequency judging signal is effective; and then, the counting processing module 600 determines whether the output frequency detection result is valid according to whether the frequency judgment signal is valid or not and the preset detection period value, thereby realizing the power consumption detection function of the low specific frequency signal.
In one embodiment, the count processing module 600 is electrically connected to the timing module 300. The timing module 300 is also used to determine whether the first count value exceeds its maximum countable range. If the first count value exceeds the maximum countable range, the timing module 300 outputs a timing value invalid signal to the timing keeping module 400 and the count processing module 600, and the timing module 300 clears the first count value. When the timing holding module 400 receives the timing value invalid signal, the timing holding module 400 clears the saved timing holding value. Meanwhile, when the count processing module 600 receives the timing value invalid signal, the count processing module 600 also clears the second count value. That is, as long as the timer module 300 determines that the first count value exceeds the maximum countable range, the timer module 300, the timer keeping module 400, and the count processing module 600 all clear their respective counts.
Referring to fig. 5, in one embodiment, the detection module 200 includes: flip-flop 210, not gate 220, and gate 230. A first input of the flip-flop 210 is electrically connected to an output of the processing module 100. A second input terminal of the flip-flop 210 is configured to input the preset clock signal. An input terminal of the not-gate 220 is electrically connected to an output terminal of the flip-flop 210. A first input of the and gate 230 is electrically connected to an output of the processing module 100. A second input of the and gate 230 is electrically connected to an output of the not gate 220. The output of the and gate 230 is used for outputting the rising or falling edge valid signal to the timing module 300.
In one embodiment, the flip-flop 210 may be a D flip-flop. In one embodiment, the flip-flop 210 may be triggered by an edge (i.e., a rising edge or a falling edge) of the preset clock signal. In this embodiment, through the cooperation of the flip-flop 210, the not gate 220 and the and gate 230, the rising edge or the falling edge of the forming signal can be detected, and finally the rising edge or the falling edge valid signal is output to the timing module 300.
In one embodiment, the count processing module 600 includes: a delay module 610 and a count module 620. A first input of the delay module 610 is electrically connected to an output of the detection module 200. A second input terminal of the delay module 610 is configured to input the preset clock signal. The delay module 610 is configured to delay the effective rising or falling edge signal by one period of the preset clock signal based on the preset clock signal, and output the effective rising or falling edge delayed signal. The counting module 620 is electrically connected to the output terminals of the judging module 500 and the delaying module 610, respectively. The counting module 620 is configured to receive the frequency decision signal when the rising or falling edge valid delay signal is valid based on the preset clock signal, and determine whether the output frequency detection result is valid according to whether the frequency decision signal is valid and the preset detection period value.
In one embodiment, the delay module 610 and the count module 620 may both be triggered by an edge (i.e., a rising edge or a falling edge) of the preset clock signal. In one embodiment, after the delay module 610 is triggered by the predetermined clock signal, the delay module 610 may delay the valid rising or falling edge signal output by the detection module 200 by one period of the predetermined clock signal and output the valid rising or falling edge delayed signal to the counting module 620. As shown in fig. 6, the delay module 610 may be formed by a D flip-flop.
After the counting module 620 is triggered by the preset clock signal, the counting module 620 may receive the frequency decision signal when the rising or falling edge valid delay signal is valid, and add 1 to a second count value in the counting module 620 in an accumulated manner if the frequency decision signal received by the counting module 620 is a valid signal. If the frequency decision signal received by the counting module 620 is an invalid signal, the second count value in the counting module 620 is cleared.
When the second count value in the counting module 620 reaches the preset detection cycle number, that is, the second count value is equal to the preset detection cycle number, it indicates that the detection circuit 10 of the specific frequency signal detects an effective specific frequency signal, and at this time, the frequency detection result output by the counting module 620 is effective. On the contrary, when the second count value is smaller than the preset detection period value, it indicates that the detection circuit 10 of the specific frequency signal does not detect a valid specific frequency signal, and the frequency detection result output by the counting module 620 is invalid at this time.
Since the buffer module 110, the detection module 200, the timing module 300, the timing keeping module 400, the delay module, and the counting module 620 are all awakened by using the preset clock signal, the power consumption of the detection circuit 10 for the specific frequency signal can be reduced when detecting the specific frequency signal, so that the low power consumption detection function for the specific frequency signal can be realized.
To sum up, the processing module 100 processes the signal to be detected with a specific frequency based on the preset clock signal and the preset width setting signal and outputs the forming signal to the detecting module 200, and the detecting module 200 detects the rising or falling edge of the forming signal and outputs the effective signal of the rising or falling edge; counting the number of cycles of the preset clock signal correspondingly received by the adjacent rising or falling edge effective signal in the forming signal through the timing module 300, and outputting a timing hold value to the judging module 500 in cooperation with the timing hold module 400, thereby determining whether the frequency judging signal is effective; and then, the counting processing module 600 determines whether the output frequency detection result is valid according to whether the frequency judgment signal is valid or not and the preset detection period value, thereby realizing the power consumption detection function of the low specific frequency signal.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A circuit for detecting a signal at a specific frequency, comprising:
the processing module (100), an input end of the processing module (100) is used for inputting a specific frequency signal to be detected, and is used for processing the specific frequency signal to be detected based on a preset clock signal and a preset width setting signal and outputting a forming signal;
the detection module (200) is electrically connected with the processing module (100) and is used for detecting the rising or falling edge of the molding signal according to the preset clock signal and outputting a rising or falling edge effective signal;
the timing module (300) is electrically connected with the detection module (200) and is used for counting the number of periods of the preset clock signal correspondingly received by the adjacent rising or falling edge effective signal in the forming signal and outputting a first count value;
the timing keeping module (400) is respectively electrically connected with the timing module (300) and the detection module (200), and is used for receiving and saving the first count value based on the preset clock signal when the rising or falling edge effective signal is effective, and outputting the saved timing keeping value;
the judging module (500) is electrically connected with the timing holding module (400) and is used for determining whether the output frequency judging signal is valid according to the timing holding value and a set threshold value; and
and the counting processing module (600) is respectively electrically connected with the judging module (500) and the detecting module (200), and is used for delaying one preset clock signal period based on the effective signal of the preset clock signal on the rising edge or the falling edge to receive the frequency judging signal and determining whether the output frequency detection result is effective according to whether the frequency judging signal is effective and a preset detection period value.
2. The circuit for detecting a specific frequency signal according to claim 1, wherein if the frequency decision signal received by the count processing module (600) is a valid signal, the second count value of the count processing module (600) is added by 1;
and if the frequency judgment signal received by the counting processing module (600) is an invalid signal, clearing a second count value of the counting processing module (600).
3. The circuit for detecting a specific frequency signal according to claim 2, wherein when the second count value of the counting module (600) reaches the predetermined detection period value, the frequency detection result outputted by the counting module (600) is valid.
4. The detection circuit of a specific frequency signal according to claim 2, wherein the count processing module (600) is electrically connected to the timing module (300);
the timing module (300) is further configured to determine whether the first count value exceeds a maximum countable range thereof, and if the first count value exceeds the maximum countable range, the timing module (300) outputs a timing value invalid signal to the timing keeping module (400) and the count processing module (600).
5. The detection circuit of a specific frequency signal according to claim 4, wherein when said timer hold module (400) receives said timer value invalid signal, said timer hold module (400) clears said timer hold value;
when the count processing module (600) receives the timing value invalid signal, the count processing module (600) clears the second count value.
6. The detection circuit of a specific frequency signal according to claim 4, wherein when the timing hold module (400) receives the first count value or the timing module (300) outputs the timing value disable signal, the timing module (300) clears the first count value and re-counts.
7. The detection circuit of a specific frequency signal according to claim 1, wherein said decision module (500) receives said timing hold value and determines whether said timing hold value is within said set threshold range;
if the timing holding value is determined to be within the set threshold range, the frequency judgment signal output by the judgment module (500) is valid;
if the timing holding value is determined not to be within the set threshold range, the frequency judgment signal output by the judgment module (500) is invalid;
and the set threshold is set according to the cycle length setting signal and the cycle fault tolerance setting signal of the specific frequency signal to be detected.
8. The detection circuit of a specific frequency signal according to claim 1, characterized in that said processing module (100) comprises:
the buffer module (110) comprises N cascaded D flip-flops (111), and the buffer module (110) is used for shifting and buffering the specific frequency signal to be detected through each stage of the D flip-flops (111) according to the rising edge or the falling edge of the preset clock signal and outputting a tap signal delayed by each stage of the D flip-flops (111); and
a high-level widening module (120), a first input end of the high-level widening module (120) being electrically connected to an output end of the cache module (110), and a second input end of the high-level widening module (120) being configured to input the preset width setting signal, and being configured to output the molding signal according to the tap signal of each stage and the preset width setting signal;
and N is an integer greater than 1 and is greater than the ratio of the period of the specific frequency signal to be detected to the period of the preset clock signal.
9. The detection circuit of a specific frequency signal according to claim 1, characterized in that said detection module (200) comprises:
a flip-flop (210), wherein a first input terminal of the flip-flop (210) is electrically connected with an output terminal of the processing module (100), and a second input terminal of the flip-flop (210) is used for inputting the preset clock signal;
an inverter (220), wherein the input end of the inverter (220) is electrically connected with the output end of the trigger (210); and
and the first input end of the AND gate (230) is electrically connected with the output end of the processing module (100), the second input end of the AND gate (230) is electrically connected with the output end of the NOT gate (220), and the output end of the AND gate (230) is used for outputting the rising or falling edge valid signal to the timing module (300).
10. The detection circuit of a specific frequency signal according to any one of claims 1 to 9, wherein the count processing module (600) comprises:
a delay module (610), a first input terminal of the delay module (610) being electrically connected to an output terminal of the detection module (200), a second input terminal of the delay module (610) being configured to input the preset clock signal, the delay module (610) being configured to delay the effective rising or falling edge signal by one period of the preset clock signal based on the preset clock signal and output a effective rising or falling edge delay signal; and
and the counting module (620) is respectively electrically connected with the output ends of the judging module (500) and the delay module (610), and is used for receiving the frequency judging signal when the rising edge effective delay signal or the falling edge effective delay signal is effective based on the preset clock signal, and determining whether the output frequency detection result is effective according to whether the frequency judging signal is effective and the preset detection period value.
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