CN111817705B - Self-induction self-acceleration bidirectional level conversion circuit - Google Patents
Self-induction self-acceleration bidirectional level conversion circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
- H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/001—Arrangements for reducing power consumption in bipolar transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/01759—Coupling arrangements; Interface arrangements with a bidirectional operation
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Abstract
The invention discloses a self-induction self-acceleration bidirectional level conversion circuit, and belongs to the technical field of electronic circuits. The circuit has simple structure, good working performance under the common CMOS process, high conversion speed and higher working frequency; the power supply can be converted between specific two-way power supply voltages and has a wider voltage conversion range; the built-in independent direction control bidirectional conversion function can enable the device to sense and control the direction of data flow without direction control pins. Not only can the low voltage be switched to the high voltage, but also the high voltage can be switched to the low voltage. The digital level conversion and matching work among most of the systems at present can be well completed. The circuit is less affected by temperature, supply voltage and process. Therefore, the self-induction self-acceleration bidirectional level conversion circuit applied to the signal transmission field can greatly improve the level conversion efficiency and has important application value.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a self-induction self-acceleration bidirectional level conversion circuit.
Background
As modern electronic systems operate at faster and faster speeds and with larger and larger amounts of parallel processed data, a variety of low voltage powered core processor systems have been developed in order to reduce the power consumption of the core processor. For information transmission between systems using two different logic standards, corresponding logic level conversion circuits are required to realize data conversion between chips with different power supply voltages.
The circuit of the conventional level shifter is shown in fig. 1, wherein an input in has a high level of vdd, and an output out has a high level of vdd. When the input in is changed from vss to vdd, the MOS transistors MN1 and MP2 are turned on, the MOS transistors MN2 and MP1 are turned off, and the output out level is pulled up to vdd by MP 2. The conversion from the vdd level to the vdd level is realized; when the input in level is changed from vdd to vss, the MOS transistors MN1 and MP2 are turned off, the MOS transistors MN2 and MP1 are turned on, and the output out level is pulled down to vss by MN 2. And low-level transmission is realized. The traditional circuit structure is widely applied, but can only perform unidirectional conversion between fixed levels.
Disclosure of Invention
The invention aims to provide a self-induction self-acceleration bidirectional level conversion circuit, which is used for solving the problem that the conventional level conversion circuit can only realize unidirectional conversion between levels.
To solve the above technical problem, the present invention provides a self-induction self-acceleration bidirectional level shifter circuit, comprising:
the direction self-induction module enables the device to automatically sense and control the flowing direction of data without a direction control pin;
the direction self-induction module is used for automatically sensing and detecting the level switching direction;
the transmission tube is used for transmitting signals;
and the pull-up path is used for pulling up the port level.
Optionally, the self-acceleration module includes a self-acceleration module a and a self-acceleration module B, which have the same structure and respectively include a nor gate, a nand gate, a resistor R1 and a capacitor C1; one input end of the NOR gate is connected with the control signal 3T _ EN, the other input end of the NOR gate is simultaneously connected with the resistor R1 and the capacitor C1, and the output end of the NOR gate is connected with one input end of the NAND gate; the resistor R1 and the other input end of the NAND gate are simultaneously connected with the point A; when the voltage of the point A is changed from low to high, a low-voltage pulse signal is generated at the output end VPLUS of the NAND gate and is output; the time width of the low-voltage pulse is adjusted by adjusting a resistor R1 and a capacitor C1; the circuit is controlled by a control signal 3T _ EN, and when the control signal 3T _ EN is low, low-voltage pulses are normally generated to work; when the control signal 3T _ EN is high, the output end VPLUS of the NAND gate is in a normal high state.
Optionally, the pull-up passage comprises pull-up pipes P1-P4;
a source electrode of a pull-up tube P1 is connected with a source electrode of a pull-up tube P3, a grid electrode of a pull-up tube P1 is connected with the self-acceleration module A, a grid electrode of a pull-up tube P3 is connected with a control signal 3T _ EN, and drain electrodes of a pull-up tube P1 and a pull-up tube P3 are connected with an interface IOVL;
the source electrode of the pull-up tube P2 is connected with the source electrode of the pull-up tube P4; the grid of the pull-up tube P2 is connected with the self-acceleration module B, the grid of the pull-up tube P4 is connected with the control signal 3T _ EN, and the drains of the pull-up tube P2 and the pull-up tube P4 are connected with the port IOVCC.
Optionally, the direction self-induction module includes:
an IOVCC signal detection circuit that recognizes a level signal from the port IOVCC; and outputting the corresponding O or VCC level to the self-acceleration module A;
the IOVL signal detection circuit identifies a signal from the port IOVL and converts the signal into an O or VCC level;
the IOVCC signal detection circuit comprises PMOS tubes MP1, MP2, an NMOS tube MN1 and an inverter INV 1; the source electrode of the PMOS tube MP1 is connected with the drain electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP1 is connected with the grid electrode of the NMOS tube MN1, the drain electrode of the PMOS tube MP1 and the drain electrode of the NMOS tube MN1 are both connected with the input end of an inverter INV1, and the output end of the inverter INV1 is connected with the acceleration module A;
the IOVL signal detection circuit comprises a PMOS tube MP3, a resistor R0, an NMOS tube MN2 and an inverter INV 2; the drain of the PMOS transistor MP3 is connected with the drain of the NMOS transistor MN2 through a resistor R0, the input end of the inverter INV2 is connected between the resistor R0 and the drain of the NMOS transistor MN2, and the output end of the inverter INV2 is connected with the acceleration module B.
Optionally, the self-induction self-acceleration bidirectional level conversion circuit further includes a gate voltage VG generating circuit, which provides a gate voltage meeting the requirement for the pass transistor.
Optionally, the transmission tube is an NMOS tube for transmitting signals.
The self-induction self-acceleration bidirectional level conversion circuit provided by the invention has the advantages of simple structure, good working performance under the common CMOS process, high conversion speed and higher working frequency; the power supply can be converted between specific two-way power supply voltages and has a wider voltage conversion range; the built-in independent direction control bidirectional conversion function can enable the device to sense and control the direction of data flow without direction control pins. Not only can the low voltage be switched to the high voltage, but also the high voltage can be switched to the low voltage. The digital level conversion and matching work among most of the systems at present can be well completed. The circuit is less affected by temperature, supply voltage and process. Therefore, the self-induction self-acceleration bidirectional level conversion circuit applied to the signal transmission field can greatly improve the level conversion efficiency and has important application value.
Drawings
FIG. 1 is a schematic diagram of a conventional level shifter architecture;
FIG. 2 is a schematic diagram of a self-induced self-accelerating bidirectional level shift circuit according to the present invention;
FIG. 3 is a schematic diagram of a circuit structure of the self-acceleration module;
fig. 4 is a schematic diagram of a gate voltage VG generating circuit.
Detailed Description
The self-induced self-accelerating bidirectional level shifting circuit provided by the invention is further described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a self-induction self-acceleration bidirectional level switching circuit, which is characterized in that a self-acceleration module is arranged to perform transient rapid pull-up on port voltage to realize rapid level switching; the built-in direction self-induction module can enable the device to sense and control the flowing direction of data without a direction control pin; the power supply can be converted between specific two-way power supply voltages and has a wider voltage conversion range; not only can the low voltage be switched to the high voltage, but also the high voltage can be switched to the low voltage.
As shown in fig. 2, the self-induced self-accelerated bidirectional level shift circuit includes a self-acceleration module, a direction self-induction module, a pass tube, a pull-up path, and a gate voltage VG generating circuit. The self-acceleration module performs transient fast pull-up on the port voltage to realize fast level conversion; the direction self-induction module automatically senses and detects the level conversion direction; the transmission tube is an NMOS tube and is used for transmitting signals; the pull-up path pulls up the port level; the grid voltage VG generating circuit provides grid voltage meeting the requirement for the transmission tube.
The self-acceleration module generates a low-voltage pulse signal to control a transient pull-up tube to open and pull up, so that the rapid conversion from 0 level to high level of a port is realized, and the conversion efficiency is improved, and the self-acceleration module comprises a self-acceleration module A and a self-acceleration module B which have the same structure and respectively comprise a NOR gate, a NAND gate, a resistor R1 and a capacitor C1 as shown in FIG. 3; one input end of the NOR gate is connected with the control signal 3T _ EN, the other input end of the NOR gate is simultaneously connected with the resistor R1 and the capacitor C1, and the output end of the NOR gate is connected with one input end of the NAND gate; the resistor R1 and the other input end of the NAND gate are simultaneously connected with the point A; when the voltage at the point A changes from low to high, the voltage at the point C changes from high to low after a period of time due to the delay action of the resistor R1 and the capacitor C1, and a low-voltage pulse signal is generated at the output end VPLUS of the NAND gate after passing through the NAND gate; the time width of the low-voltage pulse is adjusted by adjusting a resistor R1 and a capacitor C1; the circuit is controlled by a control signal 3T _ EN, and when the control signal 3T _ EN is low, low-voltage pulses are normally generated to work; when the control signal 3T _ EN is high, the output end VPLUS of the NAND gate is in a normal high state.
The upward pulling passage comprises upward pulling pipes P1-P4; a source electrode of a pull-up tube P1 is connected with a source electrode of a pull-up tube P3, a grid electrode of a pull-up tube P1 is connected with the self-acceleration module A, a grid electrode of a pull-up tube P3 is connected with a control signal 3T _ EN, and drain electrodes of a pull-up tube P1 and a pull-up tube P3 are connected with an interface IOVL; the source electrode of the pull-up tube P2 is connected with the source electrode of the pull-up tube P4; the grid of the pull-up tube P2 is connected with the self-acceleration module B, the grid of the pull-up tube P4 is connected with the control signal 3T _ EN, and the drains of the pull-up tube P2 and the pull-up tube P4 are connected with the port IOVCC.
Referring to fig. 2, the self-induced self-accelerated bi-directional level shifter circuit includes a direction self-induction module, which allows the device to automatically recognize and control the signal transmission direction without an additional direction control pin. The direction self-induction module comprises an IOVCC signal detection circuit and an IOVL signal detection circuit; the IOVCC signal detection circuit identifies a level signal from a port IOVCC and outputs a corresponding O or VCC level to an auto-acceleration module A; the IOVCC signal detection circuit comprises PMOS tubes MP1, MP2, an NMOS tube MN1 and an inverter INV 1; the source electrode of the PMOS tube MP1 is connected with the drain electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP1 is connected with the grid electrode of the NMOS tube MN1, the drain electrode of the PMOS tube MP1 and the drain electrode of the NMOS tube MN1 are both connected with the input end of an inverter INV1, and the output end of the inverter INV1 is connected with the acceleration module A. The IOVL signal detection circuit identifies a signal from a port IOVL and converts the signal into an O or VCC level; the IOVL signal detection circuit comprises a PMOS tube MP3, a resistor R0, an NMOS tube MN2 and an inverter INV 2; the drain of the PMOS transistor MP3 is connected with the drain of the NMOS transistor MN2 through a resistor R0, the input end of the inverter INV2 is connected between the resistor R0 and the drain of the NMOS transistor MN2, and the output end of the inverter INV2 is connected with the acceleration module B. And under the control of the enable signal, when the 3T _ EN is at a high level, the gate voltage VG is 0, and the direction self-induction module is turned off.
The self-induction self-acceleration bidirectional level conversion circuit comprises two paths of power supply voltages, the voltage range of a working power supply is wide, the low voltage of the power supply is low, and the requirement on the grid voltage VG of a transmission tube is high. If the grid voltage VG is too low, the transmission efficiency of the circuit is low, and the circuit does not work under high frequency; when the gate voltage VG is too high, there is a problem of leakage across the pass transistor. Therefore, the gate voltage VG needs to satisfy VTH < VG < (VL + VTH), VTH is the threshold voltage of the NMOS transistor MN5, and VL is the power supply voltage. For this purpose, a gate voltage VG generating circuit that varies with the power supply voltage VL is provided, as shown in fig. 4. In fig. 4, a mirror branch is formed by a PMOS transistor MP1, an NMOS transistor MN1, an NMOS transistor MN2, a PMOS transistor MP2, and a PMOS transistor MP3, and provides bias current for the branch where the PMOS transistor MP3 and the PNP1 are located; the other mirror image branch consists of a PMOS tube MP4, an NMOS tube MN3 and an NMOS tube MN4, and provides bias current for the branches of the PMOS tube MP5, the PMOS tube MP6, the NMOS tube MN9 and the NMOS tube MN 4. The power voltage VL is input by an NMOS tube MN5, and is transmitted through a channel formed by an NMOS tube MN5, an NMOS tube MN9 and a PNP1 tube, and then the gate voltage VG is output. The threshold voltage VTH of the NMOS tube MN5 and the VPN is a PN junction voltage of the PNP1 tube, and finally VG is approximately equal to VL-VTH + VPN. The resistor R1 mainly plays a role in shunting, and can ensure the normal opening of the PMOS transistor MP 6. Meanwhile, V1, V2 are enable control signals, when both are high level, PMOS pipe MP1, PMOS pipe MP4, PMOS pipe MP5 are turned off, NMOS pipe MN6, NMOS pipe MN7, NMOS pipe MN8 are turned on, so that the whole module is turned off, and low power consumption is realized.
In fig. 2, 3T _ EN is a circuit operation mode control signal, and the control circuit is in two different operation modes: a level conversion mode and a 3-state output mode. 3-state output mode: the control signal 3T _ EN is high, the pull-up tubes P3 and P4 and the transmission tube M0 are turned off, the ports IOVL and IOVCC output high impedance states, and the power consumption of the whole circuit is zero. Normal level conversion mode: the control signal 3T _ EN is low, and the pull-up pipes P3, P4 and the transmission pipe M0 are conducted.
Level conversion process analysis: referring to fig. 2, when the level of the port IOVL changes from 0 to VL, the voltage at the point B changes from 0 to VCC, the self-acceleration module B generates a low-voltage pulse signal to control the pull-up tube P2 to be instantly turned on and pulled up, the potential of the port IOVCC rises to VCC rapidly, then the pull-up tube P2 is turned off, and the pull-up tube P4 pulls up to maintain the high level of the port IOVCC, thereby completing the high level transition from the port IOVL to the port IOVCC. On the contrary, the principle of low level conversion from the port IOVCC to the port IOVL is the same. The transmission direction of the port signal can be automatically sensed and identified without an additional direction control module. When the two ends need to transmit low level, the self-accelerating module does not work, and the low level rapid transmission conversion can be realized by completely depending on the transmission pipe M0.
The self-induction self-acceleration bidirectional level conversion circuit comprises two paths of power supply voltages VL and VCC, and can realize bidirectional level conversion of VL level and VCC level (VL is less than VCC); by adding the self-acceleration module, the port level is pulled up quickly in a transient state, so that the conversion efficiency is improved, and quick level conversion is realized.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (5)
1. A self-induced, self-accelerating bi-directional level shift circuit, comprising:
the self-acceleration module is used for performing transient rapid pull-up on the port voltage to realize rapid level conversion;
the direction self-induction module enables the device to automatically sense and control the flowing direction of data without a direction control pin;
the transmission tube is used for transmitting signals;
a pull-up path for pulling up the port level;
the self-acceleration module comprises a self-acceleration module A and a self-acceleration module B, the self-acceleration module A and the self-acceleration module B have the same structure and respectively comprise a NOR gate, a NAND gate, a resistor R1 and a capacitor C1; one input end of the NOR gate is connected with the control signal 3T _ EN, the other input end of the NOR gate is simultaneously connected with the resistor R1 and the capacitor C1, and the output end of the NOR gate is connected with one input end of the NAND gate; the resistor R1 and the other input end of the NAND gate are simultaneously connected with the point A; when the voltage of the point A is changed from low to high, a low-voltage pulse signal is generated at the output end VPLUS of the NAND gate and is output; the time width of the low-voltage pulse is adjusted by adjusting a resistor R1 and a capacitor C1; the circuit is controlled by a control signal 3T _ EN, and when the control signal 3T _ EN is low, low-voltage pulses are normally generated to work; when the control signal 3T _ EN is high, the output end VPLUS of the NAND gate is in a normal high state.
2. The self-induced self-accelerating bi-directional level shifter circuit of claim 1, wherein the pull-up paths include pull-up transistors P1-P4;
a source electrode of a pull-up tube P1 is connected with a source electrode of a pull-up tube P3, a grid electrode of a pull-up tube P1 is connected with the self-acceleration module A, a grid electrode of a pull-up tube P3 is connected with a control signal 3T _ EN, and drain electrodes of a pull-up tube P1 and a pull-up tube P3 are connected with an interface IOVL;
the source electrode of the pull-up tube P2 is connected with the source electrode of the pull-up tube P4; the grid of the pull-up tube P2 is connected with the self-acceleration module B, the grid of the pull-up tube P4 is connected with the control signal 3T _ EN, and the drains of the pull-up tube P2 and the pull-up tube P4 are connected with the port IOVCC.
3. The self-induced, self-accelerated bi-directional level shifting circuit of claim 2, wherein the direction self-induction module comprises:
an IOVCC signal detection circuit that recognizes a level signal from the port IOVCC; and outputs the corresponding 0 or VCC level to the self-accelerating module A;
the IOVL signal detection circuit identifies a signal from the port IOVL and converts the signal into a 0 or VCC level;
the IOVCC signal detection circuit comprises PMOS tubes MP1, MP2, an NMOS tube MN1 and an inverter INV 1; the source electrode of the PMOS tube MP1 is connected with the drain electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP1 is connected with the grid electrode of the NMOS tube MN1, the drain electrode of the PMOS tube MP1 and the drain electrode of the NMOS tube MN1 are both connected with the input end of an inverter INV1, and the output end of the inverter INV1 is connected with the acceleration module A;
the IOVL signal detection circuit comprises a PMOS tube MP3, a resistor R0, an NMOS tube MN2 and an inverter INV 2; the drain of the PMOS transistor MP3 is connected with the drain of the NMOS transistor MN2 through a resistor R0, the input end of the inverter INV2 is connected between the resistor R0 and the drain of the NMOS transistor MN2, and the output end of the inverter INV2 is connected with the acceleration module B.
4. The self-induced self-accelerating bi-directional level shift circuit as claimed in claim 1, further comprising a gate voltage VG generating circuit for providing a gate voltage satisfying a requirement for the pass transistor.
5. The self-induced self-accelerating bi-directional level shift circuit of claim 1, wherein the pass transistor is an NMOS transistor for transmitting signals.
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| CN113507285B (en) * | 2021-07-13 | 2023-08-01 | 中国电子科技集团公司第五十八研究所 | Low-voltage high-speed bidirectional logic level conversion circuit |
| CN113611245B (en) * | 2021-08-17 | 2022-08-26 | 深圳市绿源半导体技术有限公司 | Bidirectional transmission device and control method |
| CN114884489A (en) * | 2022-05-13 | 2022-08-09 | 甘肃省科学院传感技术研究所 | Wide power supply voltage range input level detection circuit |
| CN115208381B (en) * | 2022-09-06 | 2022-11-22 | 中国电子科技集团公司第五十八研究所 | High-speed level conversion structure supporting preset bits |
| CN118074701B (en) * | 2024-04-17 | 2024-07-12 | 瓴科微(上海)集成电路有限责任公司 | Automatic edge detection voltage level conversion circuit |
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