CN111816624A - 一种晶圆级芯片封装结构及其封装工艺 - Google Patents

一种晶圆级芯片封装结构及其封装工艺 Download PDF

Info

Publication number
CN111816624A
CN111816624A CN202010698631.0A CN202010698631A CN111816624A CN 111816624 A CN111816624 A CN 111816624A CN 202010698631 A CN202010698631 A CN 202010698631A CN 111816624 A CN111816624 A CN 111816624A
Authority
CN
China
Prior art keywords
wafer
metal
level chip
metal contact
plastic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010698631.0A
Other languages
English (en)
Inventor
严邦杰
冯驰
林远
陈祥盼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ningbo Liyuan Technology Co ltd
Original Assignee
Ningbo Liyuan Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ningbo Liyuan Technology Co ltd filed Critical Ningbo Liyuan Technology Co ltd
Priority to CN202010698631.0A priority Critical patent/CN111816624A/zh
Publication of CN111816624A publication Critical patent/CN111816624A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/111Manufacture and pre-treatment of the bump connector preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开了晶圆级芯片封装结构,包括晶圆,晶圆上设有金属焊垫,金属焊垫上对应设有金属触点,晶圆及金属焊垫外包覆有塑封层,金属触点部分位于塑封层外。本发明还公开了晶圆级芯片封装工艺,包括如下步骤:在载物板上设置晶圆,在晶圆表面设置至少两个间隔的金属焊垫;在金属焊垫上植入焊球;使焊球融化形成金属触点;在晶圆上切割形成凹槽;对晶圆上的凹槽、金属焊垫及金属触点塑封;对晶圆上部的第一塑封层打磨减薄,以露出部分金属触点;对晶圆的下部打磨减薄以形成减薄晶圆;对晶圆的下部塑封处理以形成第二塑封层。能实现多个芯片的封装,提高了封装效率;在现有设备的基础上,缩小了芯片的封装厚度,减低了成本。

Description

一种晶圆级芯片封装结构及其封装工艺
技术领域
本发明涉及晶圆级芯片封装技术领域,具体涉及一种晶圆级芯片封装结构及其封装工艺。
背景技术
芯片封装的目的主要是为了安装半导体集成电路芯片用的外壳,起着安放、固定、密封、保护芯片和增强电热性能的作用,而且还是沟通芯片内部世界与外部电路的桥梁——芯片上的接点用导线连接到封装外壳的引脚上,这些引脚又通过印制板上的导线与其他器件建立连接。因此,封装对CPU和其他LSI集成电路都起着重要的作用。而晶圆级芯片封装技术是对整片晶圆进行封装测试后再切割得到单个成品芯片的技术,封装后的芯片尺寸与裸片一致,能大幅降低封装后的IC尺寸。
现有的常规芯片封装技术,由于设有引线且引出引脚,使得封装结构的厚度较大,对于一些对厚度有严格限制的领域,局限性越来越大。
发明内容
为解决上述技术缺陷,本发明采用的技术方案在于,提供一种晶圆级芯片封装结构,包括晶圆,所述晶圆上设有金属焊垫,所述金属焊垫上对应设有金属触点,所述晶圆外及金属焊垫外包覆有塑封层,所述金属触点部分位于塑封层外。
进一步地,所述金属触点的周侧包裹于塑封层内,且所述金属触点的上表面与塑封层的上表面位于同一水平面上。
进一步地,所述金属触点的上、下表面均为圆形,且上表面的直径大于下表面的直径。
本发明还提供了一种晶圆级芯片封装工艺,包括如下步骤:
S1:在载物板上设置晶圆,在所述晶圆的表面印刷形成至少两个间隔设置的金属焊垫;
S2:在所述金属焊垫上植入焊球并冷却;
S3:通过熔融处理使所述焊球熔化形成金属触点;
S4:在晶圆上切割形成凹槽;
S5:对晶圆上的凹槽、金属焊垫及所述金属触点塑封处理以形成第一塑封层;
S6:对晶圆上部的所述第一塑封层打磨减薄,以露出部分金属触点;
S7:对晶圆的下部打磨减薄以形成减薄晶圆;
S8:对所述减薄晶圆的下部塑封处理以形成第二塑封层。
进一步地,所述减薄晶圆的厚度为150-300um。
进一步地,所述金属焊垫的厚度为10-50um。
进一步地,减薄后的所述金属触点的厚度为40-60um。
进一步地,减薄后的所述第一塑封层的高度为50-110um,所述第二塑封层的高度为40-150um。
与现有技术比较本发明技术方案的有益效果为:
本发明提供的一种晶圆级芯片封装结构,能实现多个芯片的封装,提高了封装效率;采用现有设备的基础上,缩小了芯片的封装厚度,减低了成本;并将晶圆包裹于塑封层内,对晶圆芯片实现有效防护。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种晶圆级芯片封装结构的单个晶圆芯片的结构示意图;
图2是本发明实施例提供的一种晶圆级芯片封装工艺的流程图;
图3-图12是本发明实施例提供的一种晶圆级芯片封装工艺各步骤所对应的晶圆级芯片封装结构的示意图。
附图标记如下:
1、晶圆,1a、凹槽,2、金属焊垫,3、金属触点,4、塑封层,41、第一塑封层,42、第二塑封层,5、载物板,6、焊球。
具体实施方式
下面结合附图和具体实施例对本发明作进一步说明。
实施例1
请参阅图1-12所示,本发明提供的一种晶圆级芯片封装结构,包括晶圆1,晶圆1上设有多个金属焊垫2,每个金属焊垫2上对应设有金属触点3,晶圆1及金属焊垫2外包覆有塑封层4,金属触点3部分位于塑封层4外。
具体的,晶圆1为减薄晶圆,减薄晶圆的厚度d1为150-300um。具体的,金属焊垫2的厚度为10-50um。金属焊垫2的材质为锡膏、银胶等。
为避免金属焊垫2与金属触点3移位,且方便贴装,具体的,金属触点3的周侧包裹于塑封层4内,且金属触点3的上表面与塑封层4的上表面位于同一水平面上。金属触点3的上、下表面均为平面,金属触点3的周侧为弧面。金属触点3的上、下表面均为圆形,且上表面的直径大于下表面的直径。金属触点3由焊锡球制成,金属触点3的厚度为40-60um。相邻设置的两金属触点3之间的间距由单个晶圆芯片的大小所决定。
塑封层4的材质为环氧树脂。
本发明还提供了一种晶圆级芯片封装工艺,包括如下步骤:
S1:在载物板5上设置晶圆1,在晶圆1的表面印刷形成至少两个间隔设置的金属焊垫2;
S2:在金属焊垫2上植入焊球6并冷却;
S3:通过熔融处理使焊球6熔化形成金属触点3;
S4:在晶圆1表面上切割形成凹槽1a;
S5:对晶圆1上的凹槽1a、金属焊垫2及金属触点3塑封处理以形成第一塑封层41;
S6:对晶圆1上部的第一塑封层41打磨减薄,以露出部分金属触点3;
S7:对晶圆1的下部打磨减薄以形成减薄晶圆;
S8:翻转减薄晶圆,对减薄晶圆的下部塑封处理以形成第二塑封层42,最后将减薄晶圆切割成单个成品。
具体的,金属焊垫2的材质为锡膏、银胶等。通过锡膏将焊球6牢牢固定于晶圆1上。
具体的,熔融处理采用回流焊工艺,熔融温度与焊球6的熔化温度有关。
凹槽1a的深度为200-350um。切割设备采用金刚石切割刀,切割工艺采用半切透,以防止晶圆1移位。
金属焊垫2的厚度为10-50um。减薄前晶圆的厚度为380-635um,减薄晶圆的厚度d1为150-300um。打磨设备为砂轮,减薄后金属触点3的厚度为40-60um。减薄前的第一塑封层41的厚度为170-250um,减薄后的第一塑封层41的厚度d2为50-110um,第二塑封层42的厚度d3为40-150um。成品的厚度为240-560um。
以上所述仅是本发明的优选实施方式,本发明的保护范围并不仅局限于上述实施例,凡属于本发明思路下的技术方案均属于本发明的保护范围。应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理前提下的若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。

Claims (8)

1.一种晶圆级芯片封装结构,其特征在于:包括晶圆(1),所述晶圆(1)上设有金属焊垫(2),所述金属焊垫(2)上对应设有金属触点(3),所述晶圆(1)及金属焊垫(2)外包覆有塑封层(4),所述金属触点(3)部分位于塑封层(4)外。
2.如权利要求1所述的晶圆级芯片封装结构,其特征在于:所述金属触点(3)的周侧包裹于塑封层(4)内,且所述金属触点(3)的上表面与塑封层(4)的上表面位于同一水平面上。
3.如权利要求2所述的晶圆级芯片封装结构,其特征在于:所述金属触点(3)的上、下表面均为圆形,且上表面的直径大于下表面的直径。
4.一种晶圆级芯片封装工艺,其特征在于:包括如下步骤:
S1:在载物板(5)上设置晶圆(1),在所述晶圆(1)的表面印刷形成至少两个间隔设置的金属焊垫(2);
S2:在所述金属焊垫(2)上植入焊球(6)并冷却;
S3:通过熔融处理使所述焊球(6)熔化形成金属触点(3);
S4:在晶圆(1)上切割形成凹槽(1a);
S5:对晶圆(1)上的凹槽(1a)、金属焊垫(2)及所述金属触点(3)塑封处理以形成第一塑封层(41);
S6:对晶圆(1)上部的所述第一塑封层(41)打磨减薄,以露出部分金属触点(3);
S7:对晶圆(1)的下部打磨减薄以形成减薄晶圆;
S8:对所述减薄晶圆的下部塑封处理以形成第二塑封层(42)。
5.如权利要求4所述的晶圆级芯片封装工艺,其特征在于:所述减薄晶圆的厚度为150-300um。
6.如权利要求4所述的晶圆级芯片封装工艺,其特征在于:所述金属焊垫(2)的厚度为10-50um。
7.如权利要求4所述的晶圆级芯片封装工艺,其特征在于:减薄后的所述金属触点(3)的厚度为40-60um。
8.如权利要求4所述的晶圆级芯片封装工艺,其特征在于:减薄后的所述第一塑封层的高度为50-110um,所述第二塑封层的高度为40-150um。
CN202010698631.0A 2020-07-20 2020-07-20 一种晶圆级芯片封装结构及其封装工艺 Pending CN111816624A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010698631.0A CN111816624A (zh) 2020-07-20 2020-07-20 一种晶圆级芯片封装结构及其封装工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010698631.0A CN111816624A (zh) 2020-07-20 2020-07-20 一种晶圆级芯片封装结构及其封装工艺

Publications (1)

Publication Number Publication Date
CN111816624A true CN111816624A (zh) 2020-10-23

Family

ID=72866626

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010698631.0A Pending CN111816624A (zh) 2020-07-20 2020-07-20 一种晶圆级芯片封装结构及其封装工艺

Country Status (1)

Country Link
CN (1) CN111816624A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024113532A1 (zh) * 2022-11-28 2024-06-06 北京超材信息科技有限公司 声表面波器件的制造方法、声表面波器件以及射频模组

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681535A (zh) * 2012-09-01 2014-03-26 万国半导体股份有限公司 带有厚底部基座的晶圆级封装器件及其制备方法
CN104124176A (zh) * 2013-04-24 2014-10-29 万国半导体股份有限公司 制备应用在倒装安装工艺上的半导体器件的方法
CN107068628A (zh) * 2017-03-02 2017-08-18 上海长园维安微电子有限公司 一种实现tvs芯片wlcsp六面塑封的结构及工艺
CN110098160A (zh) * 2019-02-26 2019-08-06 上海朕芯微电子科技有限公司 一种晶圆级封装芯片及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681535A (zh) * 2012-09-01 2014-03-26 万国半导体股份有限公司 带有厚底部基座的晶圆级封装器件及其制备方法
CN104124176A (zh) * 2013-04-24 2014-10-29 万国半导体股份有限公司 制备应用在倒装安装工艺上的半导体器件的方法
CN107068628A (zh) * 2017-03-02 2017-08-18 上海长园维安微电子有限公司 一种实现tvs芯片wlcsp六面塑封的结构及工艺
CN110098160A (zh) * 2019-02-26 2019-08-06 上海朕芯微电子科技有限公司 一种晶圆级封装芯片及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024113532A1 (zh) * 2022-11-28 2024-06-06 北京超材信息科技有限公司 声表面波器件的制造方法、声表面波器件以及射频模组

Similar Documents

Publication Publication Date Title
US7772685B2 (en) Stacked semiconductor structure and fabrication method thereof
US7345361B2 (en) Stackable integrated circuit packaging
JP5420505B2 (ja) 半導体装置の製造方法
JP5215587B2 (ja) 半導体装置
US6724090B2 (en) Multi-chip package and method for manufacturing the same
JP2009212315A (ja) 半導体装置及びその製造方法
CN111816624A (zh) 一种晶圆级芯片封装结构及其封装工艺
US20090146299A1 (en) Semiconductor package and method thereof
JP2000040676A (ja) 半導体装置の製造方法
CN112185903A (zh) 电子封装件及其制法
US20080164620A1 (en) Multi-chip package and method of fabricating the same
CN111554630A (zh) 一种芯片封装方法
KR20080044518A (ko) 반도체 패키지 및 이의 제조 방법
CN111554629A (zh) 一种芯片封装方法
KR100564623B1 (ko) 크랙을 예방하는 반도체 패키지 및 그 제조방법
CN218996696U (zh) 提高芯片引脚密度的封装结构
US20090091041A1 (en) Stacked type chip package structure and method of fabricating the same
JP2011061055A (ja) 半導体装置の製造方法
KR100737217B1 (ko) 서브스트레이트리스 플립 칩 패키지와 이의 제조 방법
KR100328181B1 (ko) 플립칩이 스택된 패키지 및 그 제조방법
KR20100030496A (ko) 반도체 패키지 및 그의 제조 방법
KR100369394B1 (ko) 반도체패키지용 섭스트레이트 및 이를 이용한 반도체패키지의 제조방법
KR20010004041A (ko) 칩 사이즈 패키지의 제조 방법
CN115966537A (zh) 桥接芯片、扇出型封装结构以及相应的封装方法
KR20080029275A (ko) 박형 플립 칩 패키지 및 이의 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20201023