CN111799183A - 用于材料配合的连接的方法和装置 - Google Patents
用于材料配合的连接的方法和装置 Download PDFInfo
- Publication number
- CN111799183A CN111799183A CN202010254340.2A CN202010254340A CN111799183A CN 111799183 A CN111799183 A CN 111799183A CN 202010254340 A CN202010254340 A CN 202010254340A CN 111799183 A CN111799183 A CN 111799183A
- Authority
- CN
- China
- Prior art keywords
- pressure
- housing part
- module
- semiconductor module
- cooling module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 124
- 238000001816 cooling Methods 0.000 claims abstract description 86
- 238000005245 sintering Methods 0.000 claims abstract description 43
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 238000003825 pressing Methods 0.000 claims abstract description 3
- 238000007789 sealing Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 239000012530 fluid Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29007—Layer connector smaller than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75302—Shape
- H01L2224/7531—Shape of other parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75314—Auxiliary members on the pressing surface
- H01L2224/75315—Elastomer inlay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/75981—Apparatus chuck
- H01L2224/75982—Shape
- H01L2224/75984—Shape of other portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/8238—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/82399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/83095—Temperature settings
- H01L2224/83096—Transient conditions
- H01L2224/83097—Heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83209—Compression bonding applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明的对象是一种用于至少一个半导体模块与冷却模块的至少一个壳体件的材料配合的连接的方法,带有如下步骤:‑将至少一个烧结层施覆在冷却模块的至少一个壳体件上,‑将至少一个半导体模块定位在至少一个烧结层上,‑借助于压力单元将压力施加到至少一个半导体模块的背对冷却模块的至少一个壳体件的表面上,‑借助于反压单元将反压施加到冷却模块的至少一个壳体件的背对至少一个半导体模块的表面上,且‑借助于加热单元加热至少一个半导体模块、至少一个烧结层和冷却模块的至少一个壳体件以用于构造在至少一个半导体模块与冷却模块的至少一个壳体件之间的烧结连接。
Description
技术领域
本发明涉及一种用于至少一个半导体模块与冷却模块的至少一个壳体件的材料配合的连接的方法和装置。
背景技术
由现有技术已知如下,即,通过将半导体模块烧结到冷却模块上或者到冷却模块的壳体件上连接半导体模块与冷却模块的壳体件,其中,这通常通过将较高压力施加到半导体模块上且因此到冷却模块的壳体件上在同时较高加热半导体模块和壳体件的情形中实现。为了可反作用于在此形成的较高压应力,冷却模块的壳体件通常具有较高的强度和刚度,这可通过冷却模块的壳体件的较大的壁厚或者壁厚度来实现。该较高的壁厚度然而在半导体模块的运行中在半导体模块的方向上降低冷却模块的冷却功率。另外如下是已知的,即,使用封闭的经硬焊的冷却模块,其然而具有较小的刚度和强度且此外同样仅适度地适合用于被烧结。
发明内容
本发明因此基于如下任务,即,提供一种用于至少一个半导体模块与冷却模块的壳体件的材料配合的连接的方法以及装置供使用,在其中将半导体模块烧结到冷却模块上的过程可被使得成为可能或者被改善。在此,主要的挑战是半导体模块在较高压力和较高温度的情形中在尽可能薄壁的且易损的冷却器结构上的烧结。该薄壁的且易损的冷却器结构相反于尽可能刚性的且牢固的冷却器结构的要求,以便于确保最佳的烧结过程。
根据本发明的任务的解决方案以独立权利要求的特征来解决。本发明的优选的设计方案和改进方案在从属权利要求中进行说明。
根据本发明的方法具有如下步骤:
- 将至少一个烧结层施覆在冷却模块或半导体模块的至少一个壳体件上,
- 将至少一个半导体模块定位在至少一个烧结层上,
- 借助于压力单元将压力施加到至少一个半导体模块的背对冷却模块的至少一个壳体件的表面上,
- 借助于反压单元将反压施加到冷却模块的至少一个壳体件的背对至少一个半导体模块的表面上,且
- 借助于加热单元加热至少一个半导体模块、至少一个烧结层和冷却模块的至少一个壳体件以用于构造在至少一个半导体模块与冷却模块的至少一个壳体件之间的烧结连接。
用于至少一个半导体模块与冷却模块的至少一个壳体件的材料配合的连接的根据本发明的装置,其中,至少一个烧结层被施覆在冷却模块的至少一个壳体件上且至少一个半导体模块被定位在至少一个烧结层上,通过以下出众,该装置具有:压力单元,借助于其可将压力施加到至少一个半导体模块的背对冷却模块的至少一个壳体件的表面上;反压单元,借助于其反压可借助于反压单元施加到冷却模块的至少一个壳体件的背对至少一个半导体模块的表面上;和加热单元,借助于其可加热至少一个半导体模块、至少一个烧结层和冷却模块的至少一个壳体件以用于构造在至少一个半导体模块与冷却模块的至少一个壳体件之间的烧结连接。
根据本发明从现在起作如下设置,即,除了到半导体模块上且因此到冷却模块的至少一个壳体件上的压力产生以外可产生反压,其可由冷却模块的至少一个壳体件作用到半导体模块上。因此,在半导体模块到冷却模块的至少一个壳体件上的烧结过程期间可产生反作用于该压力的反压。借助于反压单元所施加的反压优选地相对借助于压力单元所施加的压力相同高,从而优选地可在烧结过程期间构造压力补偿单元。同样的适用于有效的压力面。通过反压的产生,在烧结期间作用到冷却模块的至少一个壳体件上的力且因此负荷可被减少,从而因此冷却模块的至少一个壳体件的壁厚或者壁厚度同样可被减少且因此热流且因此冷却模块的冷却效果在半导体模块的之后的运行中可被改善。通过冷却模块的至少一个壳体件的在烧结过程期间减少的负荷,此外从现在起可使用在其中集成有流体敞开的湍流板件结构的壳体件,因为该湍流板件结构在烧结过程期间的变形的风险可被显著减少。借助于根据本发明的方法,冷却模块在烧结的材料配合的接合过程中的变形或者损伤可被防止,即使当壳体件具有相对较小的壁厚时。此外,通过减少冷却模块的至少一个壳体件的变形的风险同样可减少被施覆在壳体件上的烧结层的变形的风险,从而可实现几乎无应力的烧结层,由此可实现在半导体模块与冷却模块的至少一个壳体件之间的良好的且稳定的材料配合的连接。半导体模块可例如是功率半导体模块、尤其IGBT半导体模块(IGBT=带有绝缘门电极的双极型晶体管)。借助于该方法,两个或多个半导体模块可同样同时被材料配合地烧结在冷却模块的至少一个壳体件上。
为了执行该方法,冷却模块的至少一个壳体件可被带入到反压单元中,其中,在反压单元中可构造至少一个压力腔用于产生反压。因此,壳体件为了烧结过程可被直接置入到反压单元中。反压单元可构造一种类型的支座装置。反压单元优选地如此构造,使得其可构造一个或多个压力腔,借助于其反压可被施加到冷却模块的壳体件上。所述一个或多个压力腔优选地直接布置在冷却模块的壳体件的背对半导体模块的表面处,从而压力腔可将反压直接施加到冷却模块的壳体件上。压力腔优选地如此布置和构造,使得在半导体模块与冷却模块之间的待构造的材料配合的连接的整个面上布置或者构造有一个或多个压力腔。
优选地,每个压力腔分别关联有至少一个密封元件,从而压力腔可分别经由密封元件来密封。通过该密封可确保恒定的反压的施加。例如,每个压力腔可借助于密封元件在其外周缘面处被包围,从而可确保各个压力腔的完全密封。
优选地可作如下设置,即,所构造的压力腔的数量可与待烧结的半导体模块的数量相符。因此,每个半导体模块可关联有压力腔,其中,优选地压力腔的尺寸或者面积大致与关联于其的半导体模块的尺寸或者面积相符。由此可实现借助于反压单元所施加的反压相对通过压力单元所施加的压力的特别良好的平衡。另外如下然而同样是可能的,即,所构造的压力腔的数量小于或高于待烧结的半导体模块的数量。
反压可借助于流体以如下方式来施加,即,反压单元的压力腔可经由流体被压力加载。该流体可以是液体、优选地液压液体,或气体、尤其液化气体。
反压的高度可优选地被液压控制。通过液压控制,相比于气动控制可实现更大的、更灵敏的且无损失的力传递。
压力单元优选地具有至少一个压力气缸、至少一个压力板和至少一个被放置在至少一个半导体模块的表面上的压力垫块。借助于压力气缸可构建压力,其可作用到半导体模块的背对冷却模块的至少一个壳体件的表面上。为了可实现压力到半导体模块的面上的均匀分配,优选地设置有至少一个压力板,其中,由压力气缸可将压力施加到压力板上。为了保护半导体模块,在压力板与半导体模块的表面之间可布置有压力垫块,其中,压力垫块优选地由硅酮构成且因此经由压力垫块可将在将压力施加到半导体模块上的情形中起作用的力还更好地均匀分配到半导体模块的整个面上。
为了即使在将压力施加到半导体模块上的情形中可实现尽可能大的、灵敏的且无损失的力传递,至少一个压力气缸可液压地或气动地经由流体来控制。
为了实现在半导体模块与冷却模块之间的尽可能稳定且耐用的材料配合的烧结连接,借助于加热单元可优选地实现至少一个半导体模块、至少一个烧结层和冷却模块的至少一个壳体件到>200℃的温度上、优选地在>240℃的温度上的加热。
为了构造至少一个烧结层可优选地使用呈粉末状的金属材料。特别优选地,作为烧结层可使用银材料。由银材料构造的烧结层通过特别良好的温度稳定性出众,从而在之后的运行中即使在较强波动的温度的情形中可确保在半导体模块与冷却模块之间的可靠且稳定的连接。另外,烧结层通过较高的热传导性和较高的耐久性出众,尤其在较强温度梯度的情形中。
附图说明
另外的改善本发明的措施在下文根据本发明的优选的设计方案的描述根据下面的附图来更详细示出。
其中:
图1显示了根据本发明的用于多个半导体模块与冷却模块的壳体件的材料配合的连接的装置和方法的示意性图示,
图2显示了根据本发明的用于多个半导体模块与冷却模块的壳体件的材料配合的连接的装置和方法的另一示意性图示,
图3显示了用于半导体模块与冷却模块的壳体件的材料配合的连接的另一装置和另一方法的示意性图示,且
图4显示了用于半导体模块与两个冷却模块的材料配合的连接的另一装置和另一方法的示意性图示。
具体实施方式
图1和2分别显示了用于实施一种用于半导体模块10,11,12在冷却模块的壳体件13处的材料配合的连接的方法的装置100。在图1和2中所显示的设计方案中,示例地三个半导体模块10,11,12借助于烧结过程被材料配合地固定在壳体件13的外面14处。
为了烧结,首先烧结层15,16,17被施覆到镀铜的或铜/银覆层的壳体件13的外面14上,其中,每个半导体模块10,11,12一个烧结层15,16,17被施覆到壳体件13的外面14上。因此,在图1和2中所显示的设计方案中,三个烧结层15,16,17被并排地施覆在壳体件13的外面14上。对于烧结层15,16,17而言可使用银材料。将各一个半导体模块10,11,12放置到烧结层15,16,17上,其应被固定在壳体件13处。半导体模块10,11,12可以是功率半导体模块,例如IGBT模块。半导体模块10,11,12分别被面型地如此地放置在烧结层15,16,17上,使得每个烧结层15,16,17完全由半导体模块10,11,12覆盖。
半导体模块10,11,12在冷却模块的壳体件13上的实际的烧结或者烧结上(Aufsintern)在供应热量的情形下且在施加压力的情形下实现,从而半导体模块10,11,12被按压到壳体件13上。为了实现这点,用于烧结的装置100具有压力单元18、反压单元19和加热单元20。加热单元可实施成箱式炉或实施成加热板。
借助于压力单元18,压力被施加到半导体模块10,11,12的背对冷却模块的壳体件13的表面21,22,23上。
在图1中所显示的设计方案中,压力单元18具有三个压力气缸(Druckzylinder)24,25,26、三个压力板27,28,29和三个压力垫块30,31,32,从而压力气缸24,25,26、压力板27,28,29和压力垫块30,31,32的数量与待烧结的半导体模块10,11,12的数量相符。
三个压力气缸24,25,26被液压控制,从而借助于流体压力可经由压力气缸24,25,26被施加到压力板27,28,29上。每个压力板27,28,29关联有压力气缸24,25,26。
压力板27,28,29此处具有与半导体模块10,11,12相同的宽度和长度,从而压力板27,28,29分别延伸经过半导体模块10,11,12的整个面。
在此,压力板27,28,29未直接放置在半导体模块10,11,12上,而是在半导体模块10,11,12与压力板27,28,29之间分别布置有压力垫块30,31,32,其例如可被填充以空气,以便于可实现压力由压力板27,28,29到半导体模块10,11,12上的均匀分配。压力垫块30,31,32的宽度和长度此处与压力板27,28,29的宽度和长度或者半导体模块10,11,12的宽度和长度相符。
借助于压力单元18,优选地大约25MPa的面压力可被施加到半导体模块10,11,12上且因此到在半导体模块10,11,12与冷却模块的壳体件13之间的待构造的材料配合的连接上。
除了压力单元18以外设置有反压单元19,借助于其相对借助于压力单元18施加压力同时施加反压到冷却模块的壳体件13的背对半导体模块10,11,12的表面33上。待施加的反压大致与由压力单元18所施加的压力相符,从而优选地可实现在压力与反压之间的力平衡或者压力平衡。通过反压单元19所施加的反压在逆着通过压力单元18所施加的压力的方向的方向上起作用。
对于烧结过程而言,冷却模块的壳体件13被带入到反压单元19中,如在图1和2中可被识别出的那样。为了产生反压,在反压单元9中构造有一个或多个压力腔34,35,36。
在图1中所显示的设计方案中,每个半导体模块10,11,12分别关联有压力腔34,35,36,从而此处压力腔34,35,36的数量与半导体模块10,11,12的数量相符。压力腔34,35,36直接布置在冷却模块的壳体件13的背对半导体模块10,11,12的表面33处,从而压力腔34,35,36可将反压直接施加到冷却模块的壳体件13上。压力腔34,35,36如此地布置且构造,使得在半导体模块10,11,12与壳体件13之间的待构造的材料配合的连接的整个面上布置或者构造有压力腔34,35,36。
在壳体件13中布置有湍流板件37,38,39,其直接布置在壳体件13的表面33处。在此设置有三个湍流板件37,38,39,从而每个半导体模块10,11,12关联有一个湍流板件37,38,39。压力腔34,35,36构造在湍流板件37,38,39的区域中,从而可直接在湍流板件37,38,39的区域中产生反压。
反压的高度以如下方式被液压控制,即,压力腔34,35,36借助于流体被压力加载。
每个压力腔34,35,36被以密封元件40,41,42密封,其中,密封元件40,41,42分别围绕压力腔34,35,36的外周缘面延伸。
除了压力单元18和反压单元19以外,装置100具有加热单元20,借助于其在烧结过程期间半导体模块10,11,12、烧结层15,16,17和冷却模块的壳体件13被加热到优选地多于200°C的温度上,以便于可构造在半导体模块10,11,12与冷却模块的壳体件13之间的烧结连接。
装置100的在图2中所显示的设计方案大致与在图1中所显示的设计方案相符,其中,此处然而压力单元18具有仅一个压力气缸24和压力板27,其中,压力板27延伸经过所有三个半导体模块10,11,12且同样延伸经过所有三个压力垫块30,31,32。
同样地,反压单元19具有仅一个压力腔34,其延伸经过所有三个半导体模块10,11,12。同样地,在壳体件13中布置有湍流板件37,其延伸经过壳体件13的整个面,在其上布置有半导体模块10,11,12。
用于半导体模块10,11,12与冷却模块的壳体件13的材料配合的连接的方法在其它方面与相对图1所描述的方法相符。
图3显示了一种设计方案,在其中压力单元18构造成位置固定的容纳单元,半导体模块10被置入到其中,从而半导体模块10由压力单元18或者容纳单元至少部分区域地包围。经由构造成位置固定的容纳单元的压力单元19,压力可被施加到半导体模块10的背对冷却模块的壳体件13的表面21上。
反压单元19具有压力腔34,在其中产生反压,其被施加到冷却模块的壳体件13的背对半导体模块10的表面33上。压力腔34此处具有可锁定的且可移动地被支承的壳体件43,其如以箭头49所显示的那样可在半导体模块10的方向上且由半导体模块10离开地被移动。在其压力上可调节的压力供给部48调节压力腔34的内压。
湍流板件37此处布置在呈盆状的容纳部44中。密封元件40布置在呈盆状的容纳部44与压力腔34的壳体件43之间,以便于可实现压力腔34朝向容纳部44的密封。
图4显示了一种设计方案,在其中半导体模块10布置在两个冷却模块之间且因此在各一个冷却模块的两个壳体件13之间。压力单元18和反压单元19此处相同地构造,其中,反压单元19且因此压力单元18在图4中所显示的设计方案中与在图3中所显示的设计方案相符。
在图4中所显示的设计方案中,因此压力单元18同样具有压力腔45。压力腔45具有可移动地被支撑的壳体件46,其如以箭头所显示的那样可在半导体模块10的方向上且由半导体模块10离开地被移动。通过壳体件46的移动,在压力腔45中的容积可被缩小或放大,以便于可调节和精调所产生的压力。同样地,反压单元19的压力腔34具有被可移动地支承的壳体件43,其如以箭头49所显示的那样可在半导体模块10的方向上且由半导体模块10离开地被移动。在其压力上可调节的压力供给部48调节压力腔34的内压。
两个冷却模块分别具有湍流板件37,其分别布置在呈盆状的容纳部44中。在压力单元18的情形中,密封元件47布置在呈盆状的容纳部44与压力腔45的壳体件46之间,以便于可实现压力腔45朝向容纳部44的密封。
不仅在压力单元18中而且在反压单元19中,压力或者反压被液压控制。
半导体模块10此处以夹层布置布置在两个冷却模块之间,其中,为了连接冷却模块与半导体模块10在半导体模块10的两个相对而置的侧面或者表面处布置有各一个烧结层15,其借助于各一个加热单元20与半导体模块10和两个壳体件13一起被加热,以便于构造烧结连接。
本发明在其实施方案中不限于上文所说明的优选的设计方案。相反,可设想一定数量的变型方案,其由所示出的解决方案同样在原则上另外形式的实施方案的情形中可用。所有由权利要求、说明书或附图得悉的特征和/或优点连同结构细节、空间布置和方法步骤不仅自身而且以极其不同的组合可能对于本发明而言是重要的。
附图标记列表
100 装置
10 半导体模块
11 半导体模块
12 半导体模块
13 壳体件
14 外面
15 烧结层
16 烧结层
17 烧结层
18 压力单元
19 反压单元
20 加热单元
21 表面
22 表面
23 表面
24 压力气缸
25 压力气缸
26 压力气缸
27 压力板
28 压力板
29 压力板
30 压力垫块
31 压力垫块
32 压力垫块
33 表面
34 压力腔
35 压力腔
36 压力腔
37 湍流板件
38 湍流板件
39 湍流板件
40 密封元件
41 密封元件
42 密封元件
43 壳体件
44 容纳部
45 压力腔
46 壳体件
47 密封元件
48 压力供给部
49 箭头。
Claims (10)
1.一种用于至少一个半导体模块(10,11,12)与冷却模块的至少一个壳体件(13)的材料配合的连接的方法,带有如下步骤:
- 将至少一个烧结层施覆在所述冷却模块或所述半导体模块的至少一个壳体件(13)上,
- 将所述至少一个半导体模块(10,11,12)定位在所述至少一个烧结层(15,16,17)上,
- 借助于压力单元(18)将压力施加到所述至少一个半导体模块(10,11,12)的背对所述冷却模块的至少一个壳体件(13)的表面(21,22,23)上,
- 借助于反压单元(19)将反压施加到所述冷却模块的至少一个壳体件(13)的背对所述至少一个半导体模块(10,11,12)的表面(33)上,且
- 借助于加热单元(20)加热所述至少一个半导体模块(10,11,12)、所述至少一个烧结层(15,16,17)和所述冷却模块的至少一个壳体件(13)以用于构造在所述至少一个半导体模块(10,11,12)与所述冷却模块的至少一个壳体件(13)之间的烧结连接。
2.根据权利要求1所述的方法,其特征在于,所述冷却模块的至少一个壳体件(13)被带入到所述反压单元(19)中,其中,在所述反压单元(19)中构造有至少一个用于产生所述反压的压力腔(34,35,36)。
3.根据权利要求2所述的方法,其特征在于,所述至少一个压力腔(34,35,36)借助于至少一个密封元件(40,41,42)密封。
4.根据权利要求2或3所述的方法,其特征在于,所构造的压力腔(34,35,36)的数量与待烧结的半导体模块(10,11,12)的数量相符。
5.根据权利要求1至4中任一项所述的方法,其特征在于,所述反压的高度被液压地或气动地控制。
6.根据权利要求1至5中任一项所述的方法,其特征在于,所述压力单元(18)具有至少一个压力气缸(24,25,26)、至少一个压力板(27,28,29)和至少一个被放置在所述半导体模块(10,11,12)的表面(21,22,23)上的压力垫块(30,31,32)。
7.根据权利要求6所述的方法,其特征在于,所述至少一个压力气缸(24,25,26)被液压地或气动地控制。
8.根据权利要求1至7中任一项所述的方法,其特征在于,借助于所述加热单元(20)实现所述至少一个半导体模块(10,11,12)、所述至少一个烧结层(15,16,17)和所述冷却模块的至少一个壳体件(13)到>200℃的温度上的加热。
9. 根据权利要求1至8中任一项所述的方法,其特征在于,作为烧结层(15,16,17)使用银材料。
10.一种用于至少一个半导体模块(10,11,12)与冷却模块的至少一个壳体件(13)的材料配合的连接的装置(100),其中,至少一个烧结层(15,16,17)被施覆在所述冷却模块的至少一个壳体件(13)上且所述至少一个半导体模块(10,11,12)被定位在所述至少一个烧结层(15,16,17)上,带有
压力单元(18),借助于其压力可被施加到所述至少一个半导体模块(10,11,12)的背对所述冷却模块的至少一个壳体件(13)的表面(21,22,23)上,
反压单元(19),借助于其反压可借助于反压单元(19)被施加到所述冷却模块的至少一个壳体件(13)的背对所述至少一个半导体模块(10,11,12)的表面(33)上,和
加热单元(20),借助于其可加热所述至少一个半导体模块(10,11,12)、所述至少一个烧结层(15,16,17)和所述冷却模块的至少一个壳体件(13)以用于构造在所述至少一个半导体模块(10,11,12)与所述冷却模块的至少一个壳体件(13)之间的烧结连接。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102019204683.5A DE102019204683A1 (de) | 2019-04-02 | 2019-04-02 | Verfahren und Vorrichtung zum stoffschlüssigen Verbinden mindestens eines Halbleitermoduls mit mindestens einem Gehäuseteil eines Kühlmoduls |
DE102019204683.5 | 2019-04-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111799183A true CN111799183A (zh) | 2020-10-20 |
Family
ID=72518402
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010254340.2A Pending CN111799183A (zh) | 2019-04-02 | 2020-04-02 | 用于材料配合的连接的方法和装置 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN111799183A (zh) |
DE (1) | DE102019204683A1 (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102021206698A1 (de) | 2021-05-26 | 2022-12-01 | Volkswagen Aktiengesellschaft | Verfahren zur Herstellung eines kühlbaren Elektronikmoduls |
WO2024042155A1 (de) * | 2022-08-25 | 2024-02-29 | Pink Gmbh Thermosysteme | Sintervorrichtung und verfahren |
CN116631917B (zh) * | 2023-07-19 | 2023-12-19 | 江苏快克芯装备科技有限公司 | 气压膜压接装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE643868A (zh) * | 1964-02-14 | 1964-08-14 | ||
DE3235038A1 (de) * | 1982-09-22 | 1984-03-22 | Josef 5000 Köln Buchholz | Verfahren und vorrichtung zum brikettieren von losen stoffen, insbesondere von faserigen abfallstoffen |
US20070131353A1 (en) * | 2005-12-09 | 2007-06-14 | Semikron Elektronik Gmbh & Co. Kg | Apparatus and clocked method for pressure-sintered bonding |
EP2061071A2 (de) * | 2007-11-16 | 2009-05-20 | SEMIKRON Elektronik GmbH & Co. KG | Verfahren zur Herstellung einer Halbleiterbaugruppe |
US20110017808A1 (en) * | 2008-02-15 | 2011-01-27 | Danfoss Silicon Power Gmbh | Method for the low-temperature pressure sintering |
EP2390914A1 (de) * | 2010-05-27 | 2011-11-30 | SEMIKRON Elektronik GmbH & Co. KG | Anordnung zweier Verbindungspartner mit einer Niedertemperatur-Drucksinterverbindung und Herstellungsverfahren hierzu |
CN208589435U (zh) * | 2018-01-30 | 2019-03-08 | 因芬尼昂技术股份公司 | 功率半导体模块 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006009159A1 (de) * | 2006-02-21 | 2007-08-23 | Curamik Electronics Gmbh | Verfahren zum Herstellen eines Verbundsubstrates sowie Verbundsubstrat |
US7525187B2 (en) * | 2006-10-13 | 2009-04-28 | Infineon Technologies Ag | Apparatus and method for connecting components |
DE102008005748A1 (de) * | 2008-01-24 | 2009-07-30 | Bayerische Motoren Werke Aktiengesellschaft | Leistungselektronikmodul |
DE102010020696B4 (de) * | 2010-05-17 | 2012-11-08 | Danfoss Silicon Power Gmbh | Verfahren zum NTV-Sintern eines drei-dimensionale Konturen aufweisenden Halbleiterbauelementes |
-
2019
- 2019-04-02 DE DE102019204683.5A patent/DE102019204683A1/de active Pending
-
2020
- 2020-04-02 CN CN202010254340.2A patent/CN111799183A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE643868A (zh) * | 1964-02-14 | 1964-08-14 | ||
DE3235038A1 (de) * | 1982-09-22 | 1984-03-22 | Josef 5000 Köln Buchholz | Verfahren und vorrichtung zum brikettieren von losen stoffen, insbesondere von faserigen abfallstoffen |
US20070131353A1 (en) * | 2005-12-09 | 2007-06-14 | Semikron Elektronik Gmbh & Co. Kg | Apparatus and clocked method for pressure-sintered bonding |
EP2061071A2 (de) * | 2007-11-16 | 2009-05-20 | SEMIKRON Elektronik GmbH & Co. KG | Verfahren zur Herstellung einer Halbleiterbaugruppe |
US20110017808A1 (en) * | 2008-02-15 | 2011-01-27 | Danfoss Silicon Power Gmbh | Method for the low-temperature pressure sintering |
EP2390914A1 (de) * | 2010-05-27 | 2011-11-30 | SEMIKRON Elektronik GmbH & Co. KG | Anordnung zweier Verbindungspartner mit einer Niedertemperatur-Drucksinterverbindung und Herstellungsverfahren hierzu |
CN208589435U (zh) * | 2018-01-30 | 2019-03-08 | 因芬尼昂技术股份公司 | 功率半导体模块 |
Also Published As
Publication number | Publication date |
---|---|
DE102019204683A1 (de) | 2020-10-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111799183A (zh) | 用于材料配合的连接的方法和装置 | |
US8794287B2 (en) | Wafer bonding apparatus | |
US8191599B2 (en) | Apparatus for laminating a solar module | |
JP4961342B2 (ja) | 2つのウエハの相互接触のための方法および装置 | |
JP5272348B2 (ja) | ウェハ接合装置 | |
US11820095B2 (en) | Sintering press for sintering electronic components on a substrate | |
CN105307452B (zh) | 一种热沉材料为底板超薄均热板的制造方法 | |
JP2013191840A (ja) | チップ圧着装置およびその方法 | |
CN106716614A (zh) | 一种特别用于热接合微机电部件的装置 | |
KR20160088426A (ko) | 정전척, 챔버 및 정전척의 제조 방법 | |
CN104145345A (zh) | 太阳能电池模块的制造方法及层压装置 | |
CN209880633U (zh) | 用于薄膜太阳能电池组件的热层压设备 | |
JP2013010330A (ja) | ラミネート装置用の熱板 | |
KR101363273B1 (ko) | 접합장치 및 접합방법 | |
KR101167626B1 (ko) | 진공확산접합장치 | |
JP2013138077A (ja) | 三次元実装装置 | |
TW202331863A (zh) | 用於連接至少一個電子組件之元件的擴散焊接和/或燒結裝置、工具及系統 | |
JP6137851B2 (ja) | 加熱加圧装置および加熱加圧方法 | |
US11984328B2 (en) | Semiconductor manufacturing apparatus and semiconductor manufacturing method | |
JP5560716B2 (ja) | 加圧装置およびデバイスの製造方法 | |
CN117650062A (zh) | 封装方法,以及半导体器件 | |
JP3564659B2 (ja) | 微粒子を用いた接着方法及び熱圧着装置 | |
TW202418414A (zh) | 燒結裝置及方法 | |
KR20240070454A (ko) | 웨이퍼 적재대 | |
KR101074262B1 (ko) | 반도체 칩 본딩 장치 및 그의 본딩 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |