CN111769078B - Method for manufacturing TSV passive interposer for system-in-package - Google Patents
Method for manufacturing TSV passive interposer for system-in-package Download PDFInfo
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- CN111769078B CN111769078B CN202010562314.6A CN202010562314A CN111769078B CN 111769078 B CN111769078 B CN 111769078B CN 202010562314 A CN202010562314 A CN 202010562314A CN 111769078 B CN111769078 B CN 111769078B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
Abstract
The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a method for preparing a TSV passive adapter plate for system-in-package. The invention extends a layer of SiGe material on a silicon substrate; and then, extending a layer of Si material on the surface of the SiGe material in an epitaxial manner, and then selectively removing the SiGe material, so that the top layer Si material is separated from the bottom silicon substrate, and the TSV passive adapter plate substrate is obtained. The manufacturing process is simplified, the silicon substrate does not need to be damaged, and the TSV passive adapter plate substrate with the thickness of only a few micrometers can be obtained.
Description
Technical Field
The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a method for manufacturing a TSV passive adapter plate for system-in-package.
Background
With the rapid development of integrated circuit technology, microelectronic packaging technology is becoming a major factor that restricts the development of semiconductor technology. In order to achieve high density of electronic packages, better performance and lower overall cost, the skilled person has developed a series of advanced packaging techniques. The three-dimensional system-in-package technology has good electrical performance and high reliability, can realize high packaging density, and is widely applied to various high-speed circuits and miniaturized systems. The Through Silicon Via (TSV) interposer technology is a new technology for realizing interconnection of stacked chips in a three-dimensional integrated circuit, and a plurality of vertical interconnection vias and subsequent Redistribution Layer (RDL) are manufactured on a Silicon wafer to realize electrical interconnection between different chips. In addition, the TSV interposer technology is divided into an active interposer and a passive interposer, wherein the active interposer has active devices, and the passive interposer lacks active devices. The TSV adapter plate technology can enable the stacking density of chips in the three-dimensional direction to be maximum, the interconnection line between the chips to be shortest, the overall dimension to be minimum, the chip speed and the performance of low power consumption to be greatly improved, and the TSV adapter plate technology is the most attractive technology in the electronic packaging technology at present.
In order to meet the overall thickness requirement of the package, an important step in the conventional TSV manufacturing process is silicon thinning. However, for thinning silicon wafers, mechanical grinding is usually adopted, and a considerable thickness of silicon material is removed and cannot be recycled, so that a great deal of waste of the silicon material is caused. Particularly, as the packaging technology is developed, the thickness of the silicon wafer is reduced to only a few micrometers, and the proportion of silicon materials to be stripped by adopting a traditional mechanical grinding method is increased to more than 90%.
Disclosure of Invention
The invention aims to provide a method for preparing a TSV passive adapter plate for system-in-package, which can conveniently thin the TSV passive adapter plate substrate.
The invention provides a method for preparing a TSV passive adapter plate for system-in-package, which comprises the following specific steps:
forming a sacrificial layer on the surface of a silicon substrate, then epitaxially growing a Si material on the sacrificial layer, forming a third insulating medium and a seed crystal layer on the surface of the Si material, and adhering a first carrier;
selectively corroding the sacrificial layer to separate the Si material from the silicon substrate to obtain a base;
photoetching and etching the Si material to form a through silicon via;
depositing a first insulating medium and a diffusion barrier layer on the side wall of the through silicon via and the lower surface of the substrate in sequence, and removing a third insulating medium at the bottom of the through silicon via through photoetching and etching;
forming conductive metal to completely fill the through silicon via;
forming an adhesion layer/seed layer laminated film at the bottom of the conductive metal, and forming a C4 bump on the laminated film;
adhering a second carrier below the substrate, removing the seed crystal layer and the first carrier above the substrate, forming an adhesion layer/seed layer laminated film on the top of the conductive metal, and forming a micro bump on the laminated film;
removing the second carrier.
In the preparation method, preferably, the thickness range of the Si material is 5-50 μm.
In the preparation method of the invention, preferably, the sacrificial layer is any one of SiGe, SiC, GaAs, InP and AlGaAs, or a combination of several of the SiGe, SiC, GaAs, InP and AlGaAs.
In the preparation method, preferably, the thickness range of the sacrificial layer is 1-5 μm.
In the preparation method of the present invention, preferably, the conductive metal is Cu.
In the preparation method of the invention, preferably, the seed crystal layer is at least one of Cu, Ru, Co, CuRu alloy and CuCo alloy.
In the preparation method of the invention, preferably, the diffusion impervious layer is TaN, TiN, ZrN, MnSiO3At least one of (1).
In the preparation method of the present invention, preferably, the first insulating medium is SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH.
In the preparation method of the present invention, preferably, the second insulating medium and the third insulating medium are Si3N4At least one of SiON and SiC. .
The manufacturing process is simplified, the silicon substrate does not need to be damaged, and the TSV passive adapter plate substrate with the thickness of only a few micrometers can be obtained.
Drawings
Fig. 1 is a process flow diagram of a TSV passive interposer manufacturing method for system-in-package according to the present invention.
Fig. 2 to 14 are schematic structural diagrams of steps of a TSV passive interposer manufacturing method for system-in-package.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
The technical scheme of the invention is further explained by combining the attached figures 1-14 and the embodiment. Fig. 1 is a flowchart of a TSV interposer manufacturing process for a system-in-package, and fig. 2 to 14 are schematic structural diagrams of steps of the TSV interposer manufacturing process for the system-in-package. As shown in fig. 1, the preparation method comprises the following specific steps:
step S1: and (3) extending SiGe and Si materials, and selectively removing the SiGe to obtain a substrate. Firstly, a layer of SiGe material 201 is used as a sacrificial layer on the surface of a monocrystalline silicon substrate 200 by adopting a molecular beam epitaxy process, the thickness range is 1-5 μm, and the obtained structure is shown as figure 2.
Then, a layer of Si material 202 is epitaxially grown on the surface of the SiGe material 201 by a molecular beam epitaxy process, wherein the thickness range is 5-50 μm, and the obtained structure is shown in fig. 3. In this embodiment, the SiGe and Si materials are epitaxial by a molecular beam epitaxy process, but the present invention is not limited thereto, and the two materials may be epitaxial by an ultra high vacuum chemical vapor deposition (UHV CVD) method. In this embodiment, a SiGe material is used as the sacrificial layer, but the present invention is not limited thereto, and any one or more of SiC, GaAs, InP, and AlGaAs may be used.
Then, a layer of Si is deposited on the surface of the Si material 202 by chemical vapor deposition3N4The film 203 is used as a third insulating medium and has a thickness of 200-300 nm. And then, depositing a Cu film 204 as a seed crystal layer by adopting a physical vapor deposition method, wherein the thickness range is 10-30 nm. Subsequently, a piece of ceramic film 205 is adhered to the surface of the Cu film 204 with an adhesive as a first carrier, and the resulting structure is shown in fig. 4. In this embodiment, Si is used3N4The thin film is used as the third insulating medium and the Cu thin film is used as the seed layer, but the present invention is not limited thereto and Si may be selected3N4At least one of SiON and SiC is used as an insulating medium, and at least one of Cu, Ru, Co, a CuRu alloy and a CuCo alloy is selected as a seed crystal layer.
Finally, HCl gas (at 500-600 deg.C) is usedoC) The selective etch removes the SiGe material 201 without etching other materials so that the silicon substrate 200 is separated from the Si material 202 and the resulting structure is shown in fig. 5. The Si material 202 is used as a substrate for making TSV passive interposers. In the present invention, high temperature HCl gas is used to etch and remove the SiGe material 201, but the present invention is not limited thereto, and HF (6%) may be used: h2O2（30%）：CH3COOH (99.8%) =1:2:3 mixed solution was subjected to etching.
Step S2: and forming a silicon through hole. Spin-coating a photoresist on the surface of the Si material 202 obtained aboveAnd defining the pattern of the through silicon via through exposure and development processes. The Si material 202 is then etched using a deep plasma etch (DRIE) process until the Si material 202 is through. The photoresist is then dissolved or ashed in a solvent to remove the photoresist and the resulting structure is shown in fig. 6. Wherein the adopted plasma can be selected from CF4、SF6At least one of (1). Since the silicon substrate 200 is not damaged, it can be continuously used.
Step S3: an insulating dielectric and a diffusion barrier layer are deposited. Firstly, a layer of SiO is deposited on the surface of the silicon through hole by adopting a chemical vapor deposition method2Film 206 serves as a first insulating medium; then, removing SiO deposited on the top of the silicon through hole by adopting photoetching and etching processes2Film 206, the resulting structure is shown in fig. 7.
Then, the physical vapor deposition method is adopted to deposit on the SiO2 A TaN film 207 is grown on the surface of the film 206 to be used as a diffusion barrier layer; the TaN film 207 deposited on top of the through-silicon via is then removed using photolithography and etching processes, and the resulting structure is shown in fig. 8.
Finally, removing Si at the top of the TSV through silicon via by adopting photoetching and etching processes3N4Film 203, the resulting structure is shown in fig. 9. SiO is used in the present embodiment2As the first insulating medium, TaN is used as a diffusion barrier layer, but the present invention is not limited thereto, and SiO may be selected2、Si3N4At least one of SiON, SiCOH and SiCOFH is used as a first insulating medium; TaN, TiN, ZrN and MnSiO can be selected3As a diffusion barrier. The growth mode of the first insulating medium and the diffusion barrier layer can be selected from physical vapor deposition, chemical vapor deposition, atomic layer deposition and the like.
Step S4: electroplating copper and forming contact bumps. First, a copper material 208 is electroplated inside the through-silicon via by using the copper film 204 as a seed layer and using an electroplating process, the through-silicon via is completely filled with the copper material, and the bottom of the copper material 208 is flush with the bottom of the Si material 202, and the resulting structure is as shown in fig. 10.
Then, removing the second surface of the through silicon via by photoetching and etching processesAn insulating dielectric 206 and diffusion barrier 207; then, a layer of Si is deposited by adopting a chemical vapor deposition method3N4The film 209 serves as a second insulating medium; subsequently, the Si on the surface of the copper material 208 is removed by adopting photoetching and etching processes3N4Film 209, the resulting structure is shown in FIG. 11.
Next, growing a laminated film 210 composed of a Ti film and a Cu film by using a physical vapor deposition method, wherein the Ti film and the Cu film are respectively used as an adhesion layer and a seed layer; further electroplating a laminated metal 211 formed by a Cu material and a Sn material on the surface of the adhesive layer/seed layer laminated film 210 by using an electroplating method to serve as a C4 bump; further, the stacked film 210 formed by the adhesion layer/seed layer is removed by photolithography and etching to ensure that no conduction exists between adjacent micro bumps, and the structure is shown in fig. 12.
Next, a piece of ceramic film 212 is adhered below the TSV silicon through hole by using an adhesive as a carrier; the ceramic film 205 and the copper film 204 above the TSV are further removed in sequence, and the resulting structure is shown in fig. 13.
Finally, a laminated film 213 consisting of a Ti film and a Cu film is grown by adopting a physical vapor deposition method, wherein the Ti film and the Cu film are respectively used as an adhesion layer and a seed layer; further adopting an electroplating method to electroplate laminated metal 214 formed by a Cu material and a Sn material on the surface of the adhesive layer/seed layer laminated film 213 as a micro bump; further removing the laminated film 213 formed by part of the adhesion layer/seed layer by adopting photoetching and etching methods to ensure that no conduction exists between the adjacent micro-bumps; the ceramic film 212 is further removed and the resulting structure is shown in fig. 14. Si is used in the present embodiment3N4As the second insulating medium, however, the present invention is not limited thereto, and Si may be selected3N4At least one of SiON and SiC as a second insulating medium; wherein the second insulating medium also acts as a diffusion barrier.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (9)
1. A method for preparing a TSV passive interposer for system-in-package is characterized by comprising the following specific steps:
forming a sacrificial layer (201) on the surface of a silicon substrate (200), then epitaxially growing a Si material (202) on the sacrificial layer (201), forming a third insulating medium (203) and a seed layer (204) on the surface of the Si material (202), and adhering a first carrier (205); selectively etching the sacrificial layer (201) to separate the Si material (202) from the silicon substrate (200) and to use the Si material (202) as a base;
photoetching and etching the Si material (202) to form a through silicon via;
sequentially depositing a first insulating medium (206) and a diffusion barrier layer (207) on the side wall of the through silicon via and the lower surface of the substrate, and removing a third insulating medium (203) on the top of the through silicon via through photoetching and etching;
forming a conductive metal (208) to completely fill the through silicon via; depositing a dielectric film (209) as a second insulating dielectric layer; subsequently, removing the dielectric film (209) on the surface of the conductive metal (208);
forming an adhesion layer/seed layer laminated film (210) at the bottom of the conductive metal (208), and forming a C4 bump (211) on the laminated film; adhering a second carrier (212) under the substrate, then removing the seed layer (204) and the first carrier (205) above the substrate, forming an adhesion layer/seed layer stack film (213) on top of the conductive metal (208), and forming a micro-bump (214) on the stack film;
removing the second carrier (212).
2. The method for manufacturing the TSV passive interposer for the system-in-package according to claim 1, wherein the thickness of the Si material is 5-50 μm.
3. The method of claim 1, wherein the sacrificial layer is any one of SiGe, SiC, GaAs, InP, AlGaAs, or a combination thereof.
4. The method for manufacturing the TSV passive interposer for the system-in-package according to claim 1, wherein the thickness of the sacrificial layer is 1-5 μm.
5. The method for manufacturing the TSV passive interposer for the system-in-package according to claim 1, wherein the conductive metal is Cu.
6. The method for manufacturing the TSV passive interposer for the system-in-package according to claim 5, wherein the seed layer is at least one of Cu, Ru, Co, CuRu alloy and CuCo alloy.
7. The method for manufacturing the TSV passive interposer for the system-in-package according to claim 1, wherein the diffusion barrier layer is TaN, TiN, ZrN, MnSiO3At least one of (1).
8. The method for preparing the TSV passive interposer for the system-in-package according to claim 1, wherein the first insulating medium is SiO2、Si3N4At least one of SiON, SiCOH and SiCOFH.
9. The method for manufacturing the TSV passive interposer for the system-in-package according to claim 1, wherein the second insulating medium and the third insulating medium are Si3N4At least one of SiON and SiC.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426847A (en) * | 2012-05-22 | 2013-12-04 | 三星电子株式会社 | Through-silicon via (TSV) semiconductor devices having via pad inlays |
| CN104347492A (en) * | 2013-08-09 | 2015-02-11 | 上海微电子装备有限公司 | Manufacturing methods for through hole structure with high depth-to-width ratio and multi-chip interconnection |
| CN106328584A (en) * | 2016-11-22 | 2017-01-11 | 武汉光谷创元电子有限公司 | Through-silicon-via forming method and chip with through-silicon-via |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426847A (en) * | 2012-05-22 | 2013-12-04 | 三星电子株式会社 | Through-silicon via (TSV) semiconductor devices having via pad inlays |
| CN104347492A (en) * | 2013-08-09 | 2015-02-11 | 上海微电子装备有限公司 | Manufacturing methods for through hole structure with high depth-to-width ratio and multi-chip interconnection |
| CN106328584A (en) * | 2016-11-22 | 2017-01-11 | 武汉光谷创元电子有限公司 | Through-silicon-via forming method and chip with through-silicon-via |
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