CN113035809A - Through silicon via structure, packaging structure and manufacturing method thereof - Google Patents
Through silicon via structure, packaging structure and manufacturing method thereof Download PDFInfo
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- CN113035809A CN113035809A CN202110240264.4A CN202110240264A CN113035809A CN 113035809 A CN113035809 A CN 113035809A CN 202110240264 A CN202110240264 A CN 202110240264A CN 113035809 A CN113035809 A CN 113035809A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a through silicon via structure, comprising: the silicon substrate is provided with a through hole, and an isolation medium is arranged between the inner side surface of the through hole and divides the through hole into a plurality of mounting holes at intervals; the diffusion barrier layer is arranged in the mounting hole and covers the isolation medium; a first seed crystal layer covering the diffusion barrier layer; and the conducting layer covers the first seed crystal layer, fills the mounting hole, and sequentially stacks the isolation medium, the diffusion barrier layer, the first seed crystal layer and the conducting layer to fill the through hole. The installation holes are formed by arranging the isolation medium in the through holes, so that the through silicon hole structure is more compact, the possible short circuit condition among the through silicon holes is avoided, and each installation hole can transmit electric signals in a parallel connection mode, so that when a part of the installation holes are short-circuited or damaged, the electric signals can still be transmitted, and the reliability of the through silicon hole structure is improved. In addition, the invention also provides a packaging structure and a manufacturing method thereof.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a through silicon via structure, a packaging structure and a manufacturing method thereof.
Background
With the rapid development of integrated circuit technology, microelectronic packaging technology is becoming a major factor that restricts the development of semiconductor technology. In order to achieve high density of electronic packages, better performance and lower overall cost, the skilled person has developed a series of advanced packaging techniques.
The three-dimensional packaging technology has good electrical performance and high reliability, can realize high packaging density, and is widely applied to various high-speed circuits and miniaturized systems. Through Silicon Via (TSV) technology is a new technology for realizing interconnection of stacked chips in a three-dimensional integrated circuit, and a plurality of vertical interconnection TSV structures are manufactured on a Silicon wafer to realize electrical interconnection between different chips. The TSV technology can maximize the stacking density of chips in the three-dimensional direction, minimize the interconnection lines among the chips, minimize the overall dimension, greatly improve the chip speed and the performance of low power consumption, and is the most attractive technology in the current electronic packaging technology.
However, the reliability of the current TSV structure still has a problem, such as when the TSV structure vertically interconnects the upper chip and the lower chip is broken or opened, which causes communication between the upper chip and the lower chip to be interrupted. Because the TSV structure is embedded in the silicon substrate, the TSV structure cannot be overhauled, and once the open circuit problem occurs, all paths passed by the TSV structure fail, so that the whole system is exposed to the risk of all failures.
The patent application with publication number CN112234143A discloses an on-chip integrated IPD package structure, a package method thereof, and a three-dimensional package structure, wherein the on-chip integrated IPD package structure includes a silicon substrate layer, a first metal wiring layer disposed on the upper and lower surfaces of the silicon substrate layer and connected through a through-silicon via penetrating through the silicon substrate layer, a dielectric layer disposed on the surface of the first metal wiring layer on the upper surface of the silicon substrate layer, a second metal wiring layer disposed on the surface of the first dielectric layer and stacked with the dielectric layer and the first metal wiring layer in sequence to form an on-chip integrated IPD, and a chip integrated on the silicon substrate layer. The silicon substrate is used as an integrated packaging substrate, passive components are integrated on the substrate, the component manufacturing and system integration are completed under the same process flow by adopting an integrated mode of packaging substrate integrated manufacturing, the components do not need to be processed and manufactured independently, the processing integration is simple, the 3D integration is easy to realize, the advantages of high precision and good consistency are achieved, the circuit area is saved, and the design is more flexible. But the reliability of the through-silicon via structure is still not guaranteed.
Therefore, it is necessary to provide a through silicon via structure, a package structure and a method for manufacturing the same, which solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a through silicon via structure, a packaging structure and a manufacturing method thereof, so that the through silicon via structure is simple and compact, and the reliability of the through silicon via structure is ensured.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a through-silicon via structure, comprising:
the silicon substrate is provided with a through hole;
the isolation medium is arranged between the inner side surface of the through hole and divides the through hole into a plurality of mounting holes at intervals;
the diffusion barrier layer is arranged in the mounting hole and covers the isolation medium;
a first seed layer covering the diffusion barrier layer;
and the conductive layer covers the first seed crystal layer, fills the mounting hole, and sequentially stacks the isolation medium, the diffusion barrier layer, the first seed crystal layer and the conductive layer to fill the through hole.
The through silicon via structure provided by the invention has the beneficial effects that: the silicon substrate is provided with the through hole, the isolation medium is arranged between the inner side surface of the through hole and the through hole, so that the through hole is divided into a plurality of mounting holes at intervals, then the diffusion barrier layer, the first seed crystal layer and the conducting layer are sequentially arranged in the mounting holes to form the silicon through hole structure, the mounting holes are formed through the isolation medium, the silicon through hole structure is more compact, the possible short circuit condition among the silicon through holes is avoided, each mounting hole can carry out electric signal transmission in a parallel connection mode, when a part of the mounting holes are internally short-circuited or damaged, the electric signal transmission can still be carried out, and the reliability of the silicon through hole structure is improved.
Preferably, the isolation medium includes a first isolation medium and a second isolation medium, the first isolation medium is disposed on the upper surface of the silicon substrate, the inner side surface of the through hole and between the through holes, and the second isolation medium is disposed on the lower surface of the silicon substrate. The beneficial effects are that: the upper surface and the lower surface of the silicon substrate and the inner side surface of the through hole are covered by the first isolation medium and the second isolation medium, so that the diffusion barrier layer is isolated from the silicon substrate, the adjacent mounting holes are separated by the first isolation medium, the short circuit between the mounting holes is avoided, and the reliability of the silicon through hole structure is further guaranteed.
Preferably, the adhesive further comprises a first adhesion layer, an upper end seed layer and a first metal convex part;
the first adhesion layer covers the diffusion barrier layer, the first seed crystal layer and the conductive layer exposed from one end of the mounting hole at intervals;
the upper end seed crystal layer is arranged on the first adhesion layer;
the first metal projection is disposed on the upper end seed crystal layer. The beneficial effects are that: through range upon range of setting first adhesion layer, upper end seed crystal layer and first metal convex part in proper order, the structure after the range upon range of forms the clearance with the isolation medium separation between the mounting hole, has realized that the area of contact of increase through-silicon via structure and air exists with parallelly connected form between the through-silicon via one end that forms, can effectively dispel the heat, has improved the life of through-silicon via structure.
Preferably, the adhesive further comprises a second adhesion layer, a lower end seed layer and a second metal convex part;
the second adhesion layer covers the diffusion barrier layer, the first seed crystal layer and the conductive layer exposed from the other end of the mounting hole at intervals;
the lower seed crystal layer is arranged on the second adhesion layer;
the second metal convex part is arranged on the lower end seed crystal layer. The beneficial effects are that: the second adhesion layer, the lower end seed crystal layer and the second metal convex part are sequentially stacked, and the stacked structure is separated by the isolation medium between the mounting holes to form a gap, so that the formed through silicon holes exist in a parallel connection mode, and the contact area of the through silicon hole structure and air is further increased for heat dissipation.
A packaging structure made of the through-silicon-via structure comprises:
the chip comprises a first chip and a second chip, wherein the first chip is arranged on the first metal convex part, and the second chip is arranged on the second metal convex part.
The packaging structure made of the through silicon via structure has the beneficial effects that: the packaging structure is manufactured by adopting the through silicon via structure, so that the reliability of electric signal transmission between the first chip and the second chip is guaranteed, and the reliability of the packaging structure is improved.
A manufacturing method of a packaging structure comprises the following steps:
s01: providing a silicon substrate;
s02: forming a through hole on the silicon substrate, and arranging an isolation medium between the inner side surface of the through hole and the through hole to divide the through hole into a plurality of mounting holes at intervals;
s03: sequentially arranging a diffusion barrier layer, a first seed crystal layer and a conductive layer in the mounting hole, and filling the mounting hole;
s04: and arranging a first chip and a second chip, wherein the first chip and the second chip are conducted through the conducting layer.
The manufacturing method of the packaging structure provided by the invention has the following beneficial effects: the through hole is formed on the silicon substrate, the isolation medium is arranged between the inner side surface of the through hole and the through hole, so that the through hole is divided into a plurality of mounting holes at intervals, then the diffusion barrier layer, the first seed crystal layer and the conducting layer are sequentially arranged in the mounting holes to form the through hole structure, the through hole structure is more compact due to the fact that the mounting holes are formed through the isolation medium, the possible short circuit condition among the through holes is avoided, and each mounting hole can carry out electric signal transmission in a parallel connection mode, so that when a part of the mounting holes are short-circuited or damaged, the electric signal transmission can still be carried out, and the reliability of the through hole structure is improved.
Preferably, in step S02, the isolation medium includes a first isolation medium and a second isolation medium, a metal assisted etching process is used to form a spaced groove in advance, and then the first isolation medium is disposed in the groove and on the upper surface of the silicon substrate. The beneficial effects are that: the narrow groove can be obtained by adopting a metal auxiliary etching process, so that the first isolation medium is arranged thinly, the proportion of the first isolation medium in the through silicon via structure is reduced, and the through silicon via structure is more compact and simpler.
Preferably, in step S03, a portion of the silicon material of the silicon substrate and the first isolation medium between adjacent grooves are removed to form the mounting hole, the diffusion barrier layer, the first seed layer and the conductive layer are sequentially deposited in the mounting hole, the mounting hole is filled, and then the diffusion barrier layer, the first seed layer and the conductive layer on the level of the first isolation medium are removed.
Preferably, the first adhesion layer is arranged on the first isolation medium, the diffusion barrier layer, the first seed crystal layer and the conductive layer which are exposed at the upper end;
then, sequentially arranging the upper end seed crystal layer and the first metal convex part on the first adhesion layer;
and finally, removing part of the first adhesion layer and the upper end seed crystal layer on the horizontal plane of the first isolation medium, so that the first adhesion layer, the upper end seed crystal layer and the first metal convex parts are arranged at intervals. The beneficial effects are that: gaps are formed among the adjacent first adhesion layers, the upper end seed crystal layer and the first metal convex part, so that the through silicon via structure is ensured to exist in a parallel connection mode, and heat dissipation is facilitated.
Preferably, the lower surface of the silicon substrate is removed, so that the first isolation medium, the diffusion barrier layer, the first seed layer and the conductive layer in the mounting hole are exposed at the lower end of the silicon substrate;
then arranging the second isolation medium at the lower end of the silicon substrate to separate the diffusion barrier layer from the silicon substrate;
and arranging the second adhesion layer at the lower ends of the exposed diffusion barrier layer, the first seed crystal layer and the exposed conductive layer, and finally sequentially arranging the lower end seed crystal layer and the second metal convex part on the second adhesion layer. The beneficial effects are that: gaps are formed among the adjacent second adhesion layers, the lower end seed crystal layer and the second metal convex part, so that the through silicon via structure is ensured to exist in a parallel connection mode, and heat dissipation is facilitated.
Preferably, in step S04, the first chip is provided on the first metal bump, and the second chip is provided on the second metal bump. The beneficial effects are that: the reliability of information transmission between the first chip and the second chip is guaranteed.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of a package structure of the present invention;
FIG. 2 is a flow chart illustrating a method for manufacturing a package structure according to the present invention;
FIG. 3 is a schematic diagram of a structure formed after a catalyst is disposed on a silicon substrate in the method for manufacturing a package structure according to the present invention;
FIG. 4 is a schematic diagram of a structure formed after a groove is formed in the method for manufacturing a package structure according to the present invention;
FIG. 5 is a schematic diagram of a structure formed after removing a catalyst in the manufacturing method of the package structure according to the present invention;
FIG. 6 is a schematic diagram of a structure formed after filling the recess in the method for manufacturing the package structure according to the present invention;
FIG. 7 is a schematic diagram of a structure formed after the mounting holes are formed in the method for manufacturing the package structure according to the present invention;
FIG. 8 is a schematic diagram of a structure formed after filling the mounting holes in the method for manufacturing the package structure according to the present invention;
FIG. 9 is a schematic diagram of a structure formed after chemical mechanical polishing in the method for manufacturing a package structure according to the present invention;
FIG. 10 is a schematic structural diagram of a package structure formed after a first adhesion layer and an upper seed layer are disposed in the method for manufacturing the package structure according to the present invention;
FIG. 11 is a schematic diagram of a structure formed after a trench is formed in the method for manufacturing a package structure according to the present invention;
FIG. 12 is a schematic structural diagram of a package structure formed after a first metal bump is disposed in the method for manufacturing a package structure according to the present invention;
FIG. 13 is a schematic diagram of a package structure formed after forming electrical connection bumps according to a method of fabricating a package structure of the present invention;
FIG. 14 is a schematic diagram of a silicon substrate structure with a desired thickness formed in the method for manufacturing a package structure according to the present invention;
FIG. 15 is a schematic diagram of a structure formed after a second isolation medium is disposed in the method for manufacturing a package structure according to the present invention;
FIG. 16 is a schematic structural diagram of a package structure formed after a second adhesion layer, a lower seed layer and a second metal protrusion are disposed in the method for manufacturing a package structure according to the present invention;
fig. 17 is a top view of one embodiment of a package structure of the present invention.
The reference numbers illustrate:
the chip comprises a silicon substrate 200, a first isolation medium 201, a diffusion barrier layer 202, a first seed layer 203, a conductive layer 204, a first adhesion layer 205, an upper end seed layer 206, a Ni film 207, a first metal convex part 208, a second isolation medium 209, a second adhesion layer 210, a lower end seed layer 211, a second metal convex part 212, a first chip 213 and a second chip 214.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
In view of the problems in the prior art, in an embodiment of the disclosure, specifically referring to fig. 1, a through silicon via structure includes: a silicon substrate 200, wherein through holes (not marked in the figure) are arranged on the silicon substrate 200. The isolation medium is disposed between the inner side surface of the through hole and the through hole, and it should be noted that the isolation medium between the through holes divides the through hole into a plurality of mounting holes 102 at intervals. The diffusion barrier layer 202 is disposed in the mounting hole 102, and covers the isolation medium, the first seed layer 203 is disposed in the mounting hole 102, covers the diffusion barrier layer 202, and the conductive layer 204 is also disposed in the mounting hole 102 and covers the first seed layer 203, it is worth to say that the isolation medium, the diffusion barrier layer 202, the first seed layer 203, and the conductive layer 204 are sequentially stacked in the mounting hole 102, and the filling of the through hole is achieved while the mounting hole 102 is filled.
Because the mounting holes 102 are formed through the isolation medium, the formed through-silicon-via structure is more compact, and a possible short circuit condition between through-silicon-vias is avoided, and each mounting hole 102 can transmit electric signals in a parallel connection mode, so when a part of the mounting holes 102 are short-circuited or damaged, the electric signals can still be transmitted, and the reliability of the through-silicon-via structure is improved.
Note that, in this embodiment, the conductive layer 204 is formed ofMade of copper material, and the diffusion barrier layer 202 can be TiN, TaN, ZrN, TiWN or MnSiO3Any one of the five materials is prepared. The first seed crystal layer 203 can be made of any one of Cu, Ru, Co, RuCo, CuRu or CuCo.
Preferably, the isolation medium includes a first isolation medium 201 and a second isolation medium 209, the first isolation medium 201 is disposed on the upper surface of the silicon substrate 200, the inner side surface of the through hole and between the through holes, and the second isolation medium 209 is disposed on the lower surface of the silicon substrate 200.
The isolation medium is divided into the first isolation medium 201 and the second isolation medium 209, and the isolation medium is arranged through two different processing steps, so that the processing of the silicon through hole medium is facilitated. The first isolation medium 201 and the second isolation medium 209 cover the upper surface and the lower surface of the silicon substrate 200 and the inner side surface of the through hole, so that the diffusion barrier layer 202 is isolated from the silicon substrate 200, and the adjacent mounting holes 102 are separated by the first isolation medium 201, thereby avoiding the occurrence of short circuit between the mounting holes 102 and further ensuring the reliability of the through silicon via structure.
Further preferably, the package structure further includes a first adhesion layer 205, an upper end seed layer 206 and a first metal protrusion 208, wherein the first adhesion layer 205 covers the diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204 exposed from one end of the mounting hole 102 at intervals, the upper end seed layer 206 is disposed on the first adhesion layer 205, and the first metal protrusion 208 is disposed on the upper end seed layer 206. By sequentially stacking the first adhesion layer 205, the upper end seed layer 206 and the first metal convex part 208, the stacked structure is separated by the isolation medium between the mounting holes 102 to form a gap, so that one ends of the formed through silicon vias exist in parallel, the contact area between the through silicon via structure and air is increased, heat dissipation can be effectively performed, and the service life of the through silicon via structure is prolonged.
Preferably, the semiconductor device further comprises a second adhesion layer 210, a lower seed layer 211 and a second metal protrusion 212, wherein the second adhesion layer 210 covers the diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204 exposed from the other end of the mounting hole 102 at intervals, the lower seed layer 211 is disposed on the second adhesion layer 210, and the second metal protrusion 212 is disposed on the lower seed layer 211. The stacked structure is separated by the isolation medium between the mounting holes 102 to form a gap, so that the formed through silicon vias exist in a parallel connection mode, and the contact area of the through silicon via structure and air is further increased for heat dissipation.
In another embodiment of the disclosure, a package structure is made by using the through silicon via structure in the above embodiments, and further includes a first chip 213 and a second chip 214, where the first chip 213 is disposed on the first metal bump 208, and the second chip 214 is disposed on the second metal bump 212. The packaging structure manufactured by adopting the through silicon via structure ensures the reliability of electric signal transmission between the first chip 213 and the second chip 214, thereby improving the reliability of the packaging structure.
In another embodiment of the present disclosure, a method for manufacturing a package structure, as shown in fig. 2, includes the following steps:
s01: providing a silicon substrate;
s02: forming a through hole on the silicon substrate, and arranging an isolation medium between the inner side surface of the through hole and the through hole to divide the through hole into a plurality of mounting holes at intervals;
s03: sequentially arranging a diffusion barrier layer, a first seed crystal layer and a conductive layer in the mounting hole, and filling the mounting hole;
s04: and arranging a first chip and a second chip, wherein the first chip and the second chip are conducted through the conducting layer.
The through holes are firstly formed in the silicon substrate 200, the isolation medium is arranged between the inner side surface of the through hole and the through hole, so that the through hole is divided into a plurality of mounting holes 102 at intervals, then the diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204 are sequentially arranged in the mounting holes 102, and a through silicon via structure is formed, and as the mounting holes 102 are formed through the isolation medium, the through silicon via structure is more compact, and the possible short circuit condition among the through silicon vias is avoided, and each mounting hole 102 exists in a parallel connection mode and can transmit electric signals, when a part of the mounting holes 102 are short-circuited or damaged, the electric signals can still be transmitted, so that the reliability of the through silicon via structure is improved.
Preferably, in step S02, the isolation medium includes a first isolation medium 201 and a second isolation medium 209, a metal assisted etching process is previously used to form a spaced groove 101, and then the first isolation medium 201 is disposed in the groove 101 and on the upper surface of the silicon substrate 200.
Specifically, referring to fig. 3, firstly, a photoresist is spin-coated on the upper surface of a silicon substrate 200, a plurality of patterns of the mounting holes 102 of the tsv structure are formed through exposure and development processes, then a layer of catalyst 100 is deposited on the upper surface of the patterns of the mounting holes 102 through a physical vapor deposition process, in this embodiment, an Ag film is used as the catalyst 100, and then the Ag film on the top of the photoresist is removed through a stripping process, so as to form an Ag film distributed at intervals on the silicon substrate 200.
Further, referring to fig. 4, the silicon substrate 200 covered with the Ag film is then placed in a mixed solution of hydrofluoric acid and hydrogen peroxide to perform metal-assisted chemical etching, so as to form a groove 101 inside the silicon substrate 200. Next, referring to fig. 5, a wet etching process is used to remove the Ag film at the bottom of the groove 101. Finally, referring to fig. 6, a chemical vapor deposition process is used to deposit the first isolation medium 201 in the groove 101 and on the upper surface of the silicon substrate 200, and the groove 101 is completely filled with the first isolation medium 201.
The narrow groove 101 can be obtained by adopting a metal auxiliary etching process, so that the first isolation medium 201 is arranged thinly, the proportion of the first isolation medium 201 in the through silicon via structure is reduced, the through silicon via structure is more compact and simpler, the first isolation medium 201 among the through silicon via structures is directly obtained through one-step process, and the overall process complexity is reduced.
Preferably, in step S03, a portion of the silicon material of the silicon substrate 200 and the first isolation medium 201 between adjacent grooves 101 are removed to form the mounting hole 102, the diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204 are sequentially deposited in the mounting hole 102, the mounting hole 102 is filled, and then the diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204 on the level of the first isolation medium 201 are removed.
Specifically, referring to fig. 7, firstly, a photoresist is spin-coated on the surface of the first isolation medium 201, and a plurality of patterns of the tsv structure are formed through exposure and development processes, and then, with the photoresist as a mask, by dry etching: such as ion milling etching, plasma etching, reactive ion etching, laser ablation; or patterned by wet etching using an etchant solution, thereby forming a plurality of adjacent mounting holes 102 on the silicon substrate 200.
Then, referring to fig. 8, a physical vapor deposition process is used to sequentially deposit the diffusion barrier layer 202 and the first seed layer 203 in the mounting hole 102 and on the surface of the first isolation medium 201, and then the conductive layer 204 is disposed on the surface of the first seed layer 203, where the conductive layer 204 is a copper metal layer formed by electroplating a metal copper material, and the conductive layer 204 completely fills the inside of the mounting hole 102. Referring to fig. 9, the diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204 on the horizontal surface of the first isolation medium 201 are then removed by chemical mechanical polishing, wherein the horizontal surface of the first isolation medium 201 is located on the upper surface of the first isolation medium 201 and is parallel to the upper surface of the silicon substrate 200.
Further preferably, the first adhesion layer 205 is disposed on the first isolation medium 201, the diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204 exposed at the upper end of the first isolation medium 201, then the upper seed layer 206 and the first metal protrusion 208 are sequentially disposed on the first adhesion layer 205, and finally a portion of the first adhesion layer 205 and the upper seed layer 206 on the horizontal plane of the first isolation medium 201 are removed, so that the first adhesion layer 205, the upper seed layer 206 and the first metal protrusion 208 are disposed at intervals.
Specifically, referring to fig. 10, the first adhesion layer 205 and the upper seed layer 206 are then sequentially deposited on the horizontal surface of the first isolation medium 201 by using a physical vapor deposition process. Further, referring to fig. 11, a Ni film 207 is grown on the upper seed layer 206 by a physical vapor deposition process, and then a trench in the shape of the first metal protrusion 208 is formed by a photolithography and etching process. Referring to fig. 12, a Cu material is plated in the trench by using a plating process to form the first metal protrusion 208. Referring to fig. 13, the Ni thin film 207, a portion of the upper terminal seed layer 206, and a portion of the first adhesive layer 205 are then removed by dry etching or wet etching using an etchant solution, thereby forming an electrical connection bump of a through-silicon via structure. Gaps are formed between the adjacent salient points, so that the silicon through hole structure is ensured to exist in a parallel connection mode, and heat dissipation is facilitated.
Further preferably, the lower surface of the silicon substrate 200 is removed, so that the first isolation medium 201, the diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204 in the mounting hole 102 are exposed at the lower end of the silicon substrate 200, then the second isolation medium 209 is disposed at the lower end of the silicon substrate 200, so that the diffusion barrier layer 202 is separated from the silicon substrate 200, the second adhesion layer 210 is disposed at the lower ends of the exposed diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204, and finally the lower end seed layer 211 and the second metal protrusion 212 are sequentially disposed on the second adhesion layer 210.
Specifically, referring to fig. 14, firstly, a portion of the silicon substrate 200, a portion of the first isolation medium 201, a portion of the diffusion barrier layer 202, a portion of the first seed layer 203, and a portion of the conductive layer 204 at the lower end of the above structure are removed by using a method of mechanical grinding and chemical mechanical polishing, until the silicon substrate 200 with a desired thickness is obtained, and the through hole is formed at the same time.
Then, referring to fig. 15, a trench is formed at the lower end of the silicon substrate 200 by removing the lower end by photolithography and etching, the second isolation dielectric 209 is formed at the lower end of the silicon substrate 200 and the trench by chemical vapor deposition, and then a portion of the second isolation dielectric 209 is removed by photolithography and etching so that the second isolation dielectric 209 is flush with the bottom of the first isolation dielectric 201, thereby separating the diffusion barrier 202 from the silicon substrate 200. Referring to fig. 16, finally, the same process as that for forming the first metal protrusion 208 is adopted, and the second adhesion layer 210, the lower seed layer 211 and the second metal protrusion 212 are disposed on the surface of the second isolation medium 209 and the surfaces of the first isolation medium 201, the diffusion barrier layer 202, the first seed layer 203 and the conductive layer 204 exposed at the lower end of the mounting hole 102.
Gaps are formed among the second adhesion layer 210, the lower end seed layer 211 and the second metal convex part 212 which are adjacent to each other, so that the through silicon via structure is ensured to exist in a parallel connection mode, and heat dissipation is facilitated.
Further preferably, in step S04, the first chip 213 is provided on the first metal projection 208, and the second chip 214 is provided on the second metal projection 212. Specifically, referring to fig. 1, a plurality of first metal bumps 208 are first soldered to the same lead of the first chip 213 at the same time, and then a plurality of second metal bumps 212 are soldered to the same lead of the second chip 214 at the same time. That is to say, the plurality of tsv structures are connected in parallel to the first chip 213 and the second chip 214, that is, a single tsv structure is divided into a plurality of tsv structures existing in parallel, so that when one of the tsv structures fails, other tsv structures can still transmit signals, and through the tsv size calculation design, the current of the plurality of tsv structures is the same as the current of the single tsv structure in the prior art, so that the original signal transmission and distribution are not affected.
To further facilitate understanding, reference is made to fig. 17, which is a top view of an embodiment of the present invention.
It should be noted that any one of Ag, Au, Pt, and Pd can be selected as the catalyst 100, and SiO can be selected2、Si3N4The first isolation dielectric 201 and the second isolation dielectric 209 are made of any one of SiON, SiCOH or SiCOFH, and TiN, TaN, ZrN, TiWN, MnSiO may be selected3Any of the above as the diffusion barrier layer 202, a Ti or Ta material may be selected as the second adhesion layer 210 and the first adhesion layer 205; any one material of Cu, Ru, Co, RuCo, CuRu, or CuCo may be selected to prepare the first seed layer 203, the upper terminal seed layer 206, and the lower terminal seed layer 211.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (11)
1. A through-silicon via structure, comprising:
the silicon substrate is provided with a through hole;
the isolation medium is arranged between the inner side surface of the through hole and divides the through hole into a plurality of mounting holes at intervals;
the diffusion barrier layer is arranged in the mounting hole and covers the isolation medium;
a first seed layer covering the diffusion barrier layer;
and the conductive layer covers the first seed crystal layer, fills the mounting hole, and sequentially stacks the isolation medium, the diffusion barrier layer, the first seed crystal layer and the conductive layer to fill the through hole.
2. The through-silicon via structure of claim 1, wherein:
the isolation medium comprises a first isolation medium and a second isolation medium, the first isolation medium is arranged on the upper surface of the silicon substrate, the inner side surface of the through hole and between the through holes, and the second isolation medium is arranged on the lower surface of the silicon substrate.
3. The through-silicon via structure of claim 2, wherein:
the first adhesion layer, the upper end seed crystal layer and the first metal convex part are further included;
the first adhesion layer covers the diffusion barrier layer, the first seed crystal layer and the conductive layer exposed from one end of the mounting hole at intervals;
the upper end seed crystal layer is arranged on the first adhesion layer;
the first metal projection is disposed on the upper end seed crystal layer.
4. The through-silicon via structure of claim 3, wherein:
the second adhesion layer, the lower end seed crystal layer and the second metal convex part are further included;
the second adhesion layer covers the diffusion barrier layer, the first seed crystal layer and the conductive layer exposed from the other end of the mounting hole at intervals;
the lower seed crystal layer is arranged on the second adhesion layer;
the second metal convex part is arranged on the lower end seed crystal layer.
5. A package structure comprising the through-silicon via structure of any one of claims 1-4, wherein:
the chip comprises a first chip and a second chip, wherein the first chip is arranged on the first metal convex part, and the second chip is arranged on the second metal convex part.
6. A method for manufacturing the package structure according to claim 5, wherein:
s01: providing a silicon substrate;
s02: forming a through hole on the silicon substrate, and arranging an isolation medium between the inner side surface of the through hole and the through hole to divide the through hole into a plurality of mounting holes at intervals;
s03: sequentially arranging a diffusion barrier layer, a first seed crystal layer and a conductive layer in the mounting hole, and filling the mounting hole;
s04: and arranging a first chip and a second chip, wherein the first chip and the second chip are conducted through the conducting layer.
7. The method of manufacturing a package structure according to claim 6, wherein:
in step S02, the isolation medium includes a first isolation medium and a second isolation medium, a metal assisted etching process is performed in advance to form spaced grooves, and then the first isolation medium is disposed in the grooves and on the upper surface of the silicon substrate.
8. The method of manufacturing a package structure according to claim 7, wherein:
in step S03, removing a portion of the silicon material of the silicon substrate and the first isolation medium between adjacent grooves to form the mounting hole, depositing the diffusion barrier layer, the first seed layer and the conductive layer in the mounting hole in sequence, filling the mounting hole, and then removing the diffusion barrier layer, the first seed layer and the conductive layer on the horizontal plane of the first isolation medium.
9. The method of manufacturing a package structure according to claim 8, wherein:
arranging the first adhesion layer on the first isolation medium, the diffusion barrier layer, the first seed crystal layer and the conductive layer exposed from the upper end;
then, sequentially arranging the upper end seed crystal layer and the first metal convex part on the first adhesion layer;
and finally, removing part of the first adhesion layer and the upper end seed crystal layer on the horizontal plane of the first isolation medium, so that the first adhesion layer, the upper end seed crystal layer and the first metal convex parts are arranged at intervals.
10. The method of manufacturing a package structure according to claim 9, wherein:
removing the lower surface of the silicon substrate to expose the first isolation medium, the diffusion barrier layer, the first seed crystal layer and the conductive layer in the mounting hole at the lower end of the silicon substrate;
then arranging the second isolation medium at the lower end of the silicon substrate to separate the diffusion barrier layer from the silicon substrate;
and arranging the second adhesion layer at the lower ends of the exposed diffusion barrier layer, the first seed crystal layer and the exposed conductive layer, and finally sequentially arranging the lower end seed crystal layer and the second metal convex part on the second adhesion layer.
11. The method of manufacturing a package structure according to claim 10, wherein:
in step S04, the first chip is provided on the first metal bump, and the second chip is provided on the second metal bump.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104576585A (en) * | 2013-10-11 | 2015-04-29 | 台湾积体电路制造股份有限公司 | Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs) |
| CN111769097A (en) * | 2020-06-18 | 2020-10-13 | 复旦大学 | Silicon through hole structure for three-dimensional interconnection and manufacturing method thereof |
| CN111769076A (en) * | 2020-06-18 | 2020-10-13 | 复旦大学 | TSV adapter plate for 2.5D packaging and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576585A (en) * | 2013-10-11 | 2015-04-29 | 台湾积体电路制造股份有限公司 | Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs) |
| CN111769097A (en) * | 2020-06-18 | 2020-10-13 | 复旦大学 | Silicon through hole structure for three-dimensional interconnection and manufacturing method thereof |
| CN111769076A (en) * | 2020-06-18 | 2020-10-13 | 复旦大学 | TSV adapter plate for 2.5D packaging and preparation method thereof |
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