CN111769076B - TSV adapter plate for 2.5D packaging and preparation method thereof - Google Patents
TSV adapter plate for 2.5D packaging and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
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- 239000003054 catalyst Substances 0.000 claims description 4
- 229910016507 CuCo Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
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- Condensed Matter Physics & Semiconductors (AREA)
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- Power Engineering (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a TSV adapter plate for 2.5D packaging and a preparation method thereof. According to the method, the silicon wafer is thinned by adopting the metal-assisted chemical etching process, and the silicon through hole is formed by adopting the metal-assisted chemical etching process, so that the method does not need complex process equipment, the process is simple, and the depth-to-width ratio of the silicon through hole is easy to adjust. In addition, by the method of forming the seed crystal layer on the back surface of the silicon substrate and then filling the conductive metal in the silicon through hole, the conductive metal on the upper surface of the silicon through hole is removed without chemical mechanical polishing, so that the process steps can be further reduced.
Description
Technical Field
The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a TSV adapter plate for 2.5D packaging and a preparation method thereof.
Background
With the development of electronic products in the directions of miniaturization, high performance, high reliability and the like, the system integration level is also increasingly improved. Under the circumstances, the way to improve the performance by further reducing the feature size of the integrated circuit and the line width of the interconnection line is limited by the physical characteristics of the material and the equipment process, and the conventional moore's law has been difficult to develop. 2.5D/3D integration technology taking TSV as a core has been widely considered as the leading technology in the future high-density packaging field, and is an effective way for breaking through Moore's law. Compared with the traditional 2D packaging, the TSV adapter plate-based 2.5D packaging enables a plurality of chips to be directly interconnected on the adapter plate, wiring length is greatly shortened, signal delay and loss are reduced, and relative bandwidth of the TSV adapter plate-based 2.5D packaging can reach 8-50 times of that of the traditional packaging. The silicon-based adapter plate can be used for manufacturing interconnection lines with smaller line width, and the wiring density is greatly improved, so that the requirement of a high-performance chip is met. The silicon-based adapter plate and the chip both adopt silicon as substrate materials, the mismatch of the thermal expansion coefficients of the silicon-based adapter plate and the chip is small, the thermal stress borne by the chip is greatly reduced, and the reliability is improved. Shorter interconnect lines between the chip and the substrate may improve system electrical performance. Therefore, the packaging form in which a plurality of functional chips are interconnected through the TSV interposer is receiving more and more attention from most semiconductor companies and scientific research institutes around the world.
In order to meet the overall thickness requirement of the package, an important step in the conventional TSV manufacturing process is silicon thinning. For thinning the silicon wafer, a mechanical grinding combined with chemical mechanical polishing, wet etching, dry etching or dry polishing is usually adopted. However, these process models involve complicated process equipment and process steps, and thus the process cost is high. In addition, for the traditional TSV manufacturing process, after copper is electroplated in the through silicon via, a chemical mechanical polishing method is adopted to remove copper materials on the surface of the through silicon via, and the process steps are also increased; and the polishing slurry used for chemical mechanical polishing is harmful to the environment.
Disclosure of Invention
The invention aims to provide a TSV adapter plate for 2.5D packaging and a preparation method thereof, wherein the TSV adapter plate is simple in process and easy to adjust the depth-to-width ratio of a silicon through hole.
The invention provides a preparation method of a TSV adapter plate for 2.5D packaging, which comprises the following specific steps:
thinning the silicon substrate by adopting a metal-assisted chemical etching method;
sequentially forming a third insulating medium and a seed crystal layer on the back of the silicon substrate, and adhering a first carrier;
photoetching and defining the position of a silicon through hole on the front surface of the silicon substrate, and etching to form the silicon through hole;
depositing a first insulating medium, and etching to remove the first insulating medium at the bottom of the through silicon via;
depositing a diffusion barrier layer, and etching to remove the diffusion barrier layer at the bottom of the silicon through hole;
etching to remove the third insulating medium at the bottom of the through silicon via;
filling conductive metal in the silicon through hole;
removing the first insulating medium and the diffusion barrier layer on the upper surface of the through silicon via by adopting photoetching and etching processes, depositing a second insulating medium, and then removing the second insulating medium on the surface of the conductive metal by adopting photoetching and etching processes;
forming an adhesion layer/seed layer laminated film on the top of the conductive metal, and forming a micro bump on the laminated film;
adhering a second carrier on the front side of the silicon substrate, then removing the seed crystal layer and the first carrier on the back side of the silicon substrate, forming an adhesion layer/seed layer laminated film at the bottom of the conductive metal, and forming a C4 bump on the laminated film; removing the second carrier.
In the preparation method of the invention, preferably, the thinning of the silicon substrate by using the metal-assisted chemical etching method specifically comprises the following steps:
growing a layer of first metal film serving as a catalyst on the back surface of the silicon substrate, and then adhering a third carrier on the front surface of the silicon substrate;
placing the silicon substrate in a mixed solution of hydrofluoric acid and hydrogen peroxide for etching;
under the catalytic action of the first metal film, the silicon material in contact with the first metal film is continuously oxidized by hydrogen peroxide and etched by hydrofluoric acid, and the silicon substrate is thinned to the required thickness by controlling the etching rate and the etching time;
and etching to remove the first metal film.
In the preparation method of the present invention, preferably, the metal thin film is at least one of Ag, Pt, Au, and Pd.
In the preparation method, preferably, the thickness of the metal film is 20-50 nm.
In the preparation method of the invention, preferably, the through silicon via is formed by metal-assisted chemical etching.
In the preparation method, preferably, a layer of second metal film (206) grows on the front surface of the silicon substrate (200), and the position of the silicon through hole is defined through photoetching and etching processes;
placing the silicon substrate (200) in a mixed solution of hydrofluoric acid and hydrogen peroxide for chemical etching;
under the catalytic action of the metal film (206), the silicon material in contact with the second metal film (206) is continuously oxidized by hydrogen peroxide and etched by hydrofluoric acid, the silicon substrate (200) is etched and penetrated through by controlling the etching rate and the etching time, and the second metal film (206) is in direct contact with the third insulating medium (203) at the bottom;
the second metal film (206) is etched away.
In the preparation method of the invention, preferably, the diffusion impervious layer is TaN, TiN, ZrN, MnSiO3At least one of (1).
In the preparation method of the present invention, preferably, the conductive metal is Cu.
In the preparation method of the invention, at least one of the seed crystal layer Cu, Ru, Co, CuRu alloy and CuCo alloy is preferably selected.
The invention also provides a TSV adapter plate for 2.5D packaging, which comprises:
a through-silicon via penetrating the silicon substrate;
the first insulating medium covers the side wall of the through silicon via, and the diffusion barrier layer covers the surface of the first insulating medium;
a second insulating medium and a third insulating medium, wherein the second insulating medium covers the upper surfaces of the silicon substrate, the first insulating medium and the diffusion barrier layer, and the third insulating medium covers the lower surfaces of the silicon substrate, the first insulating medium and the diffusion barrier layer;
the structure comprises a conductive metal, a laminated film formed by an adhesive layer/a seed layer, a micro bump and a C4 bump, wherein the conductive metal completely fills the silicon through hole;
the laminated film formed by the adhesion layer/the seed layer covers the upper surface of the conductive metal and part of the surface of the second insulating medium; the laminated film formed by the adhesion layer/seed layer covers the lower surface of the conductive metal and part of the surface of the third insulating medium;
the micro-convex points are positioned on the surface of the laminated film formed by the adhesive layer/the seed layer;
the C4 bump is positioned on the surface of the laminated film formed by the adhesion layer/seed layer.
The invention adopts the metal auxiliary chemical etching process to thin the silicon chip and prepare the silicon through hole, does not need complex process equipment, has simple process and easy adjustment of the depth-to-width ratio of the silicon through hole. In addition, copper materials on the back of the through silicon via are used as seed crystal layers to electroplate copper in the through silicon via, and the copper materials on the upper surface of the through silicon via do not need to be removed by adopting a chemical mechanical polishing process, so that the process steps can be reduced.
Drawings
Fig. 1 is a flowchart of a TSV interposer fabrication method for a 2.5D package.
FIGS. 2 to 15 are schematic structural diagrams illustrating steps of a TSV adapter plate manufacturing method for 2.5D packaging.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
The technical scheme of the invention is further explained by combining the attached figures 1-15 and the embodiment. Fig. 1 is a flowchart of a TSV interposer manufacturing method for 2.5D packaging, and fig. 2 to 15 are schematic structural diagrams of steps of the TSV interposer manufacturing method for 2.5D packaging. As shown in fig. 1, the preparation method comprises the following specific steps:
step S1: and thinning the silicon wafer to obtain a substrate. Firstly, growing a layer of metal Ag film 202 serving as a first metal film on the back surface of a silicon substrate 200 by adopting a physical vapor deposition method, wherein the thickness range is 20-50 nm; then, a piece of ceramic thin film 201 is adhered to the front surface of the silicon substrate 200 with an adhesive as a third carrier, and the resulting structure is shown in fig. 2. Then, placing the silicon substrate 200 in a mixed solution of hydrofluoric acid and hydrogen peroxide to carry out metal-assisted chemical etching; under the catalytic action of the Ag film 202, the silicon material in contact with the Ag film is continuously oxidized by hydrogen peroxide and etched by hydrofluoric acid; the silicon substrate 200 can be thinned to the required thickness of 50-100 μm by controlling the etching rate and the etching time, and the obtained structure is shown in FIG. 3. In the present embodiment, Ag is used as a catalyst for metal-assisted chemical etching and a ceramic thin film is used as a support, but the present invention is not limited thereto, and at least one of Ag, Pt, Au, and Pd may be selected as a catalyst, and at least one of a ceramic thin film and an epoxy glass may be selected as a support. When the silicon chip is thinned to a certain thickness, the silicon chip is easy to bend and deform; the silicon wafer is adhered to the carrier to prevent the silicon wafer from being deformed.
Step S2: and forming a silicon through hole. The Ag film 202 is first removed by dry etching, such as ion mill etching, plasma etching, reactive ion etching, laser ablation, or by a wet etching process using an etchant solution. Then, a layer of Si is deposited on the back surface of the silicon substrate 200 by adopting a chemical vapor deposition method3N4The film 203 is used as a third insulating medium and has a thickness of 200-300 nm. Then, a Cu film is deposited as a seed crystal layer 204 by a physical vapor deposition method, and the thickness range is 10-30 nm. Then, a piece of ceramic film 205 is adhered to the back of the Cu film 204 with an adhesive as a first carrier, and the ceramic film 201 is removed, and the resulting structure is shown in fig. 4. In this embodiment, Si is used3N4The thin film is used as the third insulating medium and the Cu thin film is used as the seed layer, but the present invention is not limited thereto and Si may be selected3N4At least one of SiON and SiC is used as an insulating medium, and at least one of Cu, Ru, Co, a CuRu alloy and a CuCo alloy is selected as a seed crystal layer. Further, an Ag film is grown on the front surface of the silicon substrate 200 by using a physical vapor deposition method as the second metal film 206, and the position of the through-silicon via is defined by photolithography and etching processes, and the resulting structure is shown in fig. 5. Then, placing the silicon substrate 200 in a mixed solution of hydrofluoric acid and hydrogen peroxide for metal-assisted chemical etching; under the catalytic action of the Ag film 206, the silicon material in contact with the Ag film is continuously oxidized by hydrogen peroxide and etched by hydrofluoric acid; by controlling the etching rate and etching time, the silicon substrate is etched through, the Ag film 206 and the Si on the bottom3N4The films 203 are in direct contact and the resulting structure is shown in figure 6. The Ag film 206 is finally removed by dry etching, such as ion mill etching, plasma etching, reactive ion etching, laser ablation, or by wet etching process using etchant solution, and the resulting structure is shown in fig. 7.
Step S3: a first insulating medium and a diffusion barrier layer are deposited. First adopt toChemical vapor deposition method for depositing a layer of SiO on the surface of the silicon through hole2Film 207 serves as a first insulating medium; then, photoetching and etching processes are adopted to remove SiO deposited at the bottom of the silicon through hole2Film 207, the resulting structure is shown in figure 8. Then adopting physical vapor deposition method to deposit on SiO2 A TaN film 208 is grown on the surface of the film 207 to be used as a diffusion barrier layer; the TaN film 208 deposited at the bottom of the through-silicon-via is then removed by photolithography and etching processes, and the resulting structure is shown in fig. 9. Finally, removing Si at the bottom of the through silicon via by adopting photoetching and etching processes3N4Film 203, the resulting structure is shown in fig. 10. SiO is used in the present embodiment2As the first insulating medium, TaN is used as a diffusion barrier layer, but the present invention is not limited thereto, and SiO may be selected2、Si3N4At least one of SiON, SiCOH and SiCOFH is used as a first insulating medium; TaN, TiN, ZrN and MnSiO can be selected3As a diffusion barrier. The first insulating medium and the diffusion barrier layer can be grown in a mode of at least one of physical vapor deposition, chemical vapor deposition and atomic layer deposition.
Step S4: electroplating copper and forming contact bumps. Firstly, the copper film 204 is used as a seed layer, an electroplating process is adopted to electroplate a copper material 209 in the through silicon via, the through silicon via is completely filled with the copper material, and the top of the copper material 209 is flush with the top of the silicon substrate 200, so that the obtained structure is shown in fig. 11. Then, removing the first insulating medium 207 and the diffusion barrier layer 208 on the upper surface of the through silicon via by adopting photoetching and etching processes; then depositing a layer of Si by chemical vapor deposition3N4Film 210 acts as a second insulating medium; then, the Si on the surface of the copper material 209 is removed by adopting photoetching and etching processes3N4Film 210, the resulting structure is shown in fig. 12. Then, a laminated film 211 consisting of a Ti film and a Cu film is grown by adopting a physical vapor deposition method, wherein the Ti film and the Cu film are respectively used as an adhesion layer and a seed layer; further adopting an electroplating method to electroplate laminated metal 212 formed by a Cu material and a Sn material on the surface of the adhesive layer/seed layer laminated film 211 to be used as a micro bump; further removing by photolithography and etchingThe stacked film 211 formed by part of the adhesion layer/seed layer ensures that there is no conduction between adjacent micro bumps, and the resulting structure is shown in fig. 13. Next, adhering a ceramic film 213 as a third carrier on the front surface of the silicon substrate 200 by using an adhesive; the ceramic film 205 and the copper film 204 on the back side of the silicon substrate are further removed in this order, and the resultant structure is shown in fig. 14. Finally, growing a laminated film 214 consisting of a Ti film and a Cu film by adopting a physical vapor deposition method, wherein the Ti film and the Cu film are respectively used as an adhesion layer and a seed layer; further adopting an electroplating method to electroplate laminated metal 215 consisting of Cu material and Sn material on the surface of the adhesive layer/seed layer laminated film 214 to be used as a C4 bump; further removing the laminated film 214 formed by part of the adhesion layer/seed layer by adopting photoetching and etching methods to ensure that no conduction exists between adjacent C4 bumps; the ceramic thin film 213 is further removed and the resulting structure is shown in fig. 15. Si is used in the present embodiment3N4As the second insulating medium, however, the present invention is not limited thereto, and Si may be selected3N4At least one of SiON and SiC as a second insulating medium; wherein the second insulating medium also acts as a diffusion barrier.
As shown in fig. 15, a TSV interposer for a 2.5D package of the present invention includes: through-silicon vias that pass through the silicon substrate 200; a first insulating medium 207 and a diffusion barrier layer 208, wherein the first insulating medium 207 covers the side wall of the through silicon via, and the diffusion barrier layer 208 covers the surface of the first insulating medium 207; a second insulating dielectric 210 and a third insulating dielectric 203, wherein the second insulating dielectric 210 covers the upper surfaces of the silicon substrate 200, the first insulating dielectric 207 and the diffusion barrier 208, and the third insulating dielectric 203 covers the lower surfaces of the silicon substrate 200, the first insulating dielectric 207 and the diffusion barrier 208; a laminated film 211,214 composed of a conductive metal 209, an adhesive layer/seed layer, a micro bump 212 and a C4 bump 215, wherein the conductive metal 209 completely fills the silicon through hole; a laminated film 211 composed of an adhesion layer/seed layer covers the upper surface of the conductive metal 209 and a part of the surface of the second insulating medium 210; a laminated film 214 composed of an adhesion layer/seed layer covers the lower surface of the conductive metal 209 and a part of the surface of the third insulating medium 203; the micro-bumps 212 are positioned on the surface of the laminated film 211 formed by the adhesion layer/seed layer; the C4 bumps 215 are located on the surface of the laminated film 214 formed by the adhesion/seed layer.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. A preparation method of a TSV adapter plate for 2.5D packaging is characterized by comprising the following specific steps:
thinning the silicon substrate (200) by adopting a metal-assisted chemical etching method;
sequentially forming a third insulating medium (203) and a seed crystal layer (204) on the back of the silicon substrate (200), and adhering a first carrier (205);
photoetching and defining the position of a silicon through hole on the front surface of the silicon substrate (200), and etching to form the silicon through hole;
depositing a first insulating medium (207), and etching to remove the first insulating medium (207) at the bottom of the through silicon via; depositing a diffusion barrier layer (208), and etching to remove the diffusion barrier layer (208) at the bottom of the through silicon via; etching to remove the third insulating medium (203) at the bottom of the through silicon via;
filling a conductive metal (209) in the silicon through hole; removing the first insulating medium (207) and the diffusion barrier layer (208) on the upper surface of the through silicon via by adopting photoetching and etching processes, depositing a second insulating medium (210), and then removing the second insulating medium (210) on the surface of the conductive metal (209) by adopting photoetching and etching processes;
forming a first adhesion layer/seed layer stack film (211) on top of the conductive metal (209) and forming a micro-bump (212) on the stack film; adhering a second carrier (213) on the front surface of the silicon substrate (200), then removing the seed layer (204) and the first carrier (205) on the back surface of the silicon substrate (200), forming a second adhesion layer/seed layer laminated film (214) at the bottom of the conductive metal (209), and forming a C4 bump (215) on the laminated film; removing the second carrier (213).
2. The method for preparing the TSV adapter plate for the 2.5D packaging according to claim 1, wherein the thinning of the silicon substrate by a metal-assisted chemical etching method specifically comprises the following steps:
growing a first metal film (202) serving as a catalyst on the back surface of the silicon substrate (200), and then adhering a third carrier (201) on the front surface of the silicon substrate (200);
placing the silicon substrate (200) in a mixed solution of hydrofluoric acid and hydrogen peroxide for etching;
under the catalytic action of the first metal film (202), the silicon material in contact with the first metal film (202) is continuously oxidized by hydrogen peroxide and etched by hydrofluoric acid, and the silicon substrate (200) is thinned to the required thickness by controlling the etching rate and the etching time;
the first metal film (202) is etched away.
3. The method for manufacturing the TSV interposer for 2.5D packaging of claim 2, wherein the metal film is at least one of Ag, Pt, Au, and Pd.
4. The method for preparing the TSV interposer for 2.5D packaging of claim 2, wherein the thickness of the metal film is 20-50 nm.
5. The method for preparing the TSV interposer for the 2.5D package of claim 1, wherein the through silicon vias are formed using metal assisted chemical etching.
6. The TSV adapter plate preparation method for 2.5D packaging according to claim 5, wherein a second metal film (206) is grown on the front side of the silicon substrate (200), and the position of the through silicon via is defined through photoetching and etching processes;
placing the silicon substrate (200) in a mixed solution of hydrofluoric acid and hydrogen peroxide for chemical etching;
under the catalytic action of the metal film (206), the silicon material in contact with the second metal film (206) is continuously oxidized by hydrogen peroxide and etched by hydrofluoric acid, the silicon substrate (200) is etched and penetrated through by controlling the etching rate and the etching time, and the second metal film (206) is in direct contact with the third insulating medium (203) at the bottom;
the second metal film (206) is etched away.
7. The method for preparing a TSV interposer for 2.5D packaging of claim 1, wherein the diffusion barrier layer is TaN, TiN, ZrN, MnSiO3At least one of (1).
8. The method for preparing the TSV interposer for the 2.5D package of claim 1, wherein the conductive metal is Cu.
9. The method of claim 8, wherein the seed layer is at least one of Cu, Ru, Co, a CuRu alloy, and a CuCo alloy.
10. A TSV interposer for 2.5D package obtained based on the manufacturing method of any one of claims 1 to 9, comprising:
a through-silicon via penetrating the silicon substrate (200);
a first insulating medium (207) and a diffusion barrier layer (208), wherein the first insulating medium (207) covers the side wall of the through silicon via, and the diffusion barrier layer (208) covers the surface of the first insulating medium (207);
a second insulating dielectric (210) and a third insulating dielectric (203), wherein the second insulating dielectric (210) covers the upper surfaces of the silicon substrate (200), the first insulating dielectric (207) and the diffusion barrier (208), and the third insulating dielectric (203) covers the lower surfaces of the silicon substrate (200), the first insulating dielectric (207) and the diffusion barrier (208);
a conductive metal (209), a laminated film (211,214) composed of an adhesion layer/seed layer, a micro bump (212), and a C4 bump (215), wherein the conductive metal (209) completely fills the through silicon via; a laminated film (211) formed by the first adhesion layer/seed layer covers the upper surface of the conductive metal (209) and part of the surface of the second insulating medium (210); a laminated film (214) formed by the second adhesion layer/seed layer covers the lower surface of the conductive metal (209) and part of the surface of the third insulating medium (203); the micro-bumps (212) are positioned on the surface of the laminated film (211) formed by the first adhesion layer/seed layer; the C4 bump (215) is positioned on the surface of the laminated film (214) formed by the second adhesion layer/seed layer.
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