CN111769047A - 一种高压金属氧化物半导体终端区制造方法 - Google Patents
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Abstract
本发明公开了一种高压金属氧化物半导体终端区制造方法,包括:采用第一次光罩,经曝光显影后留下氮化硅层,同时植入接面边界延伸环;采用热氧化处理法,在接面边界延伸环上表面生成场氧化层,同时接面边界延伸环在N‑外延层上扩散开来;将氮化硅层去除后采用热氧化处理法,生成闸极氧化层;并在闸极氧化层上表面进行多晶硅沉积,再经一层光罩后留下所需的多晶硅层;在N‑外延层的主动区内植入P‑井区;采用常规技术依次制备后续的介电层以及金属层等。本发明通过利用LOCOS工艺制程,避免掉一些不需要的光罩成本,又不影响产品的静态及动态特性,在保证产品特性的前提下,简化了产品工艺流程,降低了制作成本。
Description
技术领域
本发明涉及一种高压金属氧化物半导体终端区制造方法,属于半导体领域。
背景技术
对传统高压功率金属氧化物半导体(MOSFET)来说,其电压阻断能力往往受到终端pn接面的曲率效应所影响,如何提高电压阻断能力,已经是近代多数功率组件的关键技术之一,从单纯的保护环(Guard Ring)到场板(Field Plate)设计,再到近几年比较热门的JTE(Junction Termination extension)接面边界延伸环设计。
对于现有的JTE设计,除了比场板的光罩层数多一道JTE Ring光层,也因其第一道工艺流程就需进行JTE Ring的动作,难以产生曝光对准所需的对准层(Align mark),因而需要有一道零层光罩(Zero mask)来形成对准层。虽然电压阻断能力好,相对外延片的浓度较高,但是零层光罩的成本较高,大大提高了JTE设计的制造成本。
发明内容
为了解决现有技术存在的技术问题,本发明提供一种高压金属氧化物半导体终端区制造方法,利用现有的硅的选择氧化工艺,将JTE结构中的场氧化层及其底下的接面边界延伸环(JTE Ring)完成,不需额外增加接面边界延伸环(JTE Ring)光罩,也因硅的局部氧化工艺制程中第一道为氮化硅层的沉积,就不存在对准层的问题,大大减少了光罩及工艺制作成本,但其电压阻断能力和现有JTE设计比较没有任何差异。
本发明中主要采用的技术方案为:
一种高压金属氧化物半导体终端区制造方法,具体步骤如下:
步骤1:对N-外延层采用第一次光罩,经曝光显影后N-外延层上表面两侧分别留下氮化硅层,同时在N-外延层上层植入接面边界延伸环;
步骤2:采用热氧化处理法在接面边界延伸环上表面生成场氧化层,同时接面边界延伸环在N-外延层上扩散开来;
步骤3:将氮化硅层去除后采用热氧化处理法,在N-外延层上表面以及场氧化层上表面生成闸极氧化层;
步骤4:利用化学气相沉积法在闸极氧化层上表面进行多晶硅沉积,再经一层光罩后留下部分多晶硅层;
步骤5:在N-外延层的主动区内分别植入P-井区及N+井区;
步骤6:利用化学气相沉积法在全部表面上方沉积介电质薄膜,再利用一层光罩以干蚀刻的方式在介电质薄膜上蚀刻出金属层接触位置;
步骤7:利用化学气相沉积法在金属层接触位置沉积金属层;最后利用一层光罩将金属层的位置分隔开即完成制造过程。
优选地,所述步骤1中,N-外延层上表面两侧留下的氮化硅层之间存在间隙,且接面边界延伸环位于氮化硅层间隙下方。
优选地,所述N-外延层底部设有汲极。
优选地,所述步骤1中的氮化硅层的厚度为2000Å~5000Å。
优选地,所述步骤2中的热氧化处理法采用水蒸气为氧化源进行湿氧化,并在垂直式炉管内900℃~1200℃的温度条件下,在接面边界延伸环上表面生成场氧化层,所述场氧化层的厚度为5000Å~15000Å。
优选地,所述步骤3中的热氧化处理法采用干氧化方式,以纯氧作为表面硅的氧化源,并在垂直式炉管内900℃~1200℃的温度条件下生成闸极氧化层,所述闸极氧化层的厚度为500Å~1500Å。
优选地,所述步骤4中,所述多晶硅层的厚度为5000Å~10000Å。
优选地,所述P-井区的植入能量为50 KeV ~100KeV,P-的浓度介于1e13cm-3~1e14cm-3;而N+井区的植入能量为50 KeV ~100KeV,N+的浓度则介于1e15cm-3~1e16cm-3;其中,N+井区使用一层光罩将其植入于N-外延层的主动区。
优选地,所述步骤6中介电质薄膜厚度为10000Å。
有益效果:本发明提供一种高压金属氧化物半导体终端区制造方法,通过利用LOCOS工艺制程,避免掉一些不需要的光罩成本,又不影响产品的静态及动态特性,在保证产品特性的前提下,简化了产品工艺流程,降低了制作成本。
附图说明
图1是传统高压功率金属氧化物半导体终端区结构图;
图2是本发明的高压功率金属氧化物半导体终端区结构图;
图3是经本发明中步骤1之后的结构示意图;
图4是经本发明中步骤2之后的结构示意图;
图5是经本发明中步骤3和4之后的结构示意图;
图6是经本发明中步骤5之后的结构示意图;
图7是经本发明中步骤6之后的结构示意图;
图8是本发明与一般JTE的高压600V产品的性能对比表;
图中:N-外延层1、接面边界延伸环2、场氧化层3、闸极氧化层4、多晶硅层5、P-井区6、N+井区7、介电质薄膜8、金属层9、氮化硅层10;虚线左方A区域为终端区、虚线右方B区域为主动区。
具体实施方式
为了使本技术领域的人员更好地理解本申请中的技术方案,下面对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都应当属于本申请保护的范围。
一种高压金属氧化物半导体终端区制造方法,具体步骤如下:
步骤1:对N-外延层1采用第一次光罩,经曝光显影后N-外延层1上表面两侧分别留下氮化硅层10,同时在N-外延层1上层植入接面边界延伸环2,如图3所示;
步骤2:采用热氧化处理法在接面边界延伸环2上表面生成场氧化层3,同时接面边界延伸环2在N-外延层1上扩散开来,如图4所示;
步骤3:将氮化硅层10去除后采用热氧化处理法,在N-外延层1上表面以及场氧化层3上表面生成闸极氧化层4;
步骤4:利用化学气相沉积法在闸极氧化层4上表面进行多晶硅沉积,再经一层光罩后留下部分多晶硅层5,如图5所示;
步骤5:在N-外延层的主动区B内分别植入P-井区6及N+井区7,如图6所示;
步骤6:利用化学气相沉积法在全部表面上方沉积介电质薄膜8,再利用一层光罩以干蚀刻的方式在介电质薄膜8上蚀刻出金属层接触位置,如图7所示;
步骤7:利用化学气相沉积法在金属层接触位置沉积金属层9,最后利用一层光罩将金属层9的位置分隔开即完成制造过程,得到图2所示的产品结构。
优选地,所述步骤1中,N-外延层上表面两侧留下的氮化硅层10之间存在间隙,且接面边界延伸环2位于氮化硅层10间隙下方。
优选地,所述N-外延层1底部设有汲极。
优选地,所述步骤1中的氮化硅层10的厚度为2000Å~5000Å。
优选地,所述步骤2中的热氧化处理法采用水蒸气为氧化源进行湿氧化,并在垂直式炉管内900℃~1200℃的温度条件下,在接面边界延伸环2上表面生成场氧化层3,所述场氧化层3的厚度为5000Å~15000Å。
优选地,所述步骤3中的热氧化处理法采用干氧化方式,以纯氧作为表面硅的氧化源,并在垂直式炉管内900℃~1200℃的温度条件下生成闸极氧化层4,所述闸极氧化层4的厚度为500Å~1500Å。
优选地,所述步骤4中,所述多晶硅层5的厚度为5000Å~10000Å。
优选地,所述P-井区6的植入能量为50 KeV ~100KeV,P-的浓度介于1e13cm-3~1e14cm-3;而N+井区7的植入能量为50 KeV ~100KeV,N+的浓度则介于1e15cm-3~1e16cm-3;其中,N+井区使用一层光罩将其植入于N-外延层的主动区B。
优选地,所述步骤6中介电质薄膜8厚度为10000Å。
以高压600V产品为例,如图8所示,为本发明与现有JTE(如图1所示)的高压600V产品的性能对比。根据图8可知,本发明与现有JTE的高压600V产品相比,两者的产品特性差异较小,性能基本保持一致,证明本发明不仅减少了光罩成本,同时也保证了产品的静态及动态特性。
1)本发明中,接面边界延伸环2(JTE Ring)长度及浓度由本领域技术人员进行依其电压阻断的能力需求而有不同的设计,故而未加详述。
2)本发明中的场氧化层3长度及其厚度由本领域技术人员依其电压阻断的能力需求而有不同的设计,故而未加详述。
3)本发明中多晶硅层5的长度及厚度由本领域技术人员进行依其电压阻断的能力需求而有不同的设计,故而未加详述。
4)本发明中采用热氧化处理法、化学气相沉积法以及植入技术均属于常规技术手段,本领域技术人员可根据实际需求设计工艺条件,故而未加详述。
5)本发明中,本领域技术人员可根据产品的实际结构留下所需要的多晶硅层,如图5所示,闸极氧化层4上留下的多晶硅层5分别位于场氧化层3两侧的终端区A和主动区B上方。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (9)
1.一种高压金属氧化物半导体终端区制造方法,其特征在于,具体步骤如下:
步骤1:对N-外延层采用第一次光罩,经曝光显影后N-外延层上表面两侧分别留下氮化硅层,同时在N-外延层上层植入接面边界延伸环;
步骤2:采用热氧化处理法在接面边界延伸环上表面生成场氧化层,同时接面边界延伸环在N-外延层上扩散开来;
步骤3:将氮化硅层去除后采用热氧化处理法,在N-外延层上表面以及场氧化层上表面生成闸极氧化层;
步骤4:利用化学气相沉积法在闸极氧化层上表面进行多晶硅沉积,再经一层光罩后留下部分多晶硅层;
步骤5:在N-外延层的主动区内分别植入P-井区及N+井区;
步骤6:利用化学气相沉积法在全部表面上方沉积介电质薄膜,再利用一层光罩以干蚀刻的方式在介电质薄膜上蚀刻出金属层接触位置;
步骤7:利用化学气相沉积法在金属层接触位置沉积金属层,最后利用一层光罩将金属层的位置分隔开即完成制造过程。
2.根据权利要求1所述的一种高压金属氧化物半导体终端区制造方法,其特征在于,所述步骤1中,N-外延层上表面两侧留下的氮化硅层之间存在间隙,且接面边界延伸环位于氮化硅层间隙下方。
3.根据权利要求1所述的一种高压金属氧化物半导体终端区制造方法,其特征在于,所述N-外延层底部设有汲极。
4.根据权利要求1所述的一种高压金属氧化物半导体终端区制造方法,其特征在于,所述步骤1中的氮化硅层的厚度为2000Å~5000Å。
5.根据权利要求1所述的一种高压金属氧化物半导体终端区制造方法,其特征在于,所述步骤2中的热氧化处理法采用水蒸气为氧化源进行湿氧化,并在垂直式炉管内900℃~1200℃的温度条件下,在接面边界延伸环上表面生成场氧化层,所述场氧化层的厚度为5000Å~15000Å。
6.根据权利要求1所述的一种高压金属氧化物半导体终端区制造方法,其特征在于,所述步骤3中的热氧化处理法采用干氧化方式,以纯氧作为表面硅的氧化源,并在垂直式炉管内900℃~1200℃的温度条件下生成闸极氧化层,所述闸极氧化层的厚度为500Å~1500Å。
7.根据权利要求1所述的一种高压金属氧化物半导体终端区制造方法,其特征在于,所述步骤4中,所述多晶硅沉积的厚度为5000Å~10000Å。
8. 根据权利要求1所述的一种高压金属氧化物半导体终端区制造方法,其特征在于,所述P-井区的植入能量为50 KeV ~100KeV,P-的浓度介于1e13cm-3~1e14cm-3;而N+井区的植入能量为50 KeV ~100KeV,N+的浓度则介于1e15cm-3~1e16cm-3;其中,N+井区使用一层光罩将其植入于N-外延层的主动区。
9.根据权利要求1所述的一种高压金属氧化物半导体终端区制造方法,其特征在于,所述步骤6中介电质薄膜厚度为10000Å。
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JP2006173281A (ja) * | 2004-12-14 | 2006-06-29 | Denso Corp | 半導体装置およびその製造方法 |
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