CN111717059A

CN111717059A - Direct current charging pile controller and control method thereof

Info

Publication number: CN111717059A
Application number: CN202010643873.XA
Authority: CN
Inventors: 包文泉
Original assignee: Individual
Current assignee: Hangzhou Cangxin Power Technology Co ltd
Priority date: 2020-07-07
Filing date: 2020-07-07
Publication date: 2020-09-29
Anticipated expiration: 2040-07-07
Also published as: CN111717059B

Abstract

The invention discloses a direct current charging pile controller and a control method thereof, wherein the controller comprises a main control chip, an FPGA chip, an internal digital logic module, an Ethernet interface, a charging gun A control circuit, a charging gun B control circuit, a charging gun C control circuit, a charging gun D control circuit, a touch display screen communication interface circuit, an IC card communication interface circuit and a power supply circuit; the control method of the controller includes step S1: initializing; step S2: entering a main control program; step S3: executing the interrupt subprogram, and returning to the step S2 after the execution is finished; the controller gives full play to the advantages of FPGA logic control and multiple interfaces, reduces the use of peripheral interfaces of a single chip microcomputer, further lightens the processing burden of programs of the single chip microcomputer, realizes four-gun parallel charging and improves the integration level of the controller.

Description

Direct current charging pile controller and control method thereof

Technical Field

The invention relates to the technical field of direct current charging piles, in particular to a direct current charging pile controller and a control method thereof.

Background

The direct current charging technology adopts a high-voltage and high-current charging mode; in order to ensure the safety of charging operation, related control flows and safeguard measures are specified in the existing national standard; such as connection detection, charging gun electronic lock, insulation monitoring measures, residual voltage release, charging control and the like; in actual research and development design, a main controller of the system not only needs to realize related control requirements specified in national standards, but also needs to realize functions such as ammeter control communication, charging module control communication, Ethernet communication, fan control, auxiliary power supply output control and the like in order to meet the requirements of actual application; the existing main control board of the direct current charging pile mostly adopts an embedded processor (singlechip) as a main part, and because the control peripheral has more requirements on the performance and interface resources of the processor, a plurality of processors are required to work cooperatively in a mode of realizing multi-gun charging for a common 32-bit singlechip, so that the control circuit is complex and the integration level is low; in addition, the processing logic in the main control program of the processor is relatively complex, which may cause unknown errors, resulting in the phenomena of the main controller crash and the like in the charging process.

Disclosure of Invention

Aiming at the problems in the prior art, the controller for the direct current charging pile and the control method thereof are composed of the FPGA, the single chip microcomputer and the peripheral circuit, the advantages of logic control and multiple interfaces of the FPGA are fully exerted, the use of peripheral interfaces of the single chip microcomputer is reduced, the program processing burden of the single chip microcomputer is further lightened, the four-gun parallel charging is realized, the integration level of the controller is improved, and the problems that the existing controller is complex in circuit, low in integration level and complex in processing logic and easily causes crash are solved.

In order to realize the purpose of the invention, the invention adopts the following technical scheme:

a direct current charging pile controller comprises a main control chip, an FPGA chip, an Ethernet interface, a charging gun A control circuit, a charging gun B control circuit, a charging gun C control circuit, a charging gun D control circuit, a touch display screen communication interface circuit, an IC card communication interface circuit and a power supply circuit; the charging gun A control circuit, the charging gun B control circuit, the charging gun C control circuit, the charging gun D control circuit, the touch display screen communication interface circuit and the IC card communication interface circuit are respectively and electrically connected with the FPGA chip; the FPGA chip is electrically connected with the main control chip through interrupt 0, interrupt 1, interrupt 2 and interrupt 3 signal lines and a communication bus; the Ethernet interface is electrically connected with the main control chip; the power supply circuit supplies power to each chip and circuit;

further, the charging gun A control circuit, the charging gun B control circuit, the charging gun C control circuit and the charging gun D control circuit comprise an output control circuit, an ammeter communication interface circuit, an insulation monitoring module communication circuit, a charging module communication interface circuit, a charging communication interface circuit and a CC1 detection circuit; the output control circuit comprises nine groups of control channels, a first group of control operation indicator lamps, a second group of control fault indicator lamps, a third group of control cooling fans, a fourth group and a fifth group which respectively control the switching and the output of an auxiliary power supply, a sixth group of control charging gun output, a seventh group of control discharge loop switching, and an eighth group and a ninth group of control charging gun electronic locks for locking and unlocking; .

The I/O port of the FPGA chip is electrically connected with the EXTI0, the EXTI1, the EXTI2, the EXTI3 interrupt signal input port and the FSMC interface of the main control chip through an interrupt 0 signal wire, an interrupt 1 signal wire, an interrupt 2 signal wire, an interrupt 3 signal wire and a communication bus; the Ethernet interface comprises an Ethernet PHY chip and an Ethernet connector; the RMII interface of the main control chip is electrically connected with the Ethernet PHY chip, and the Ethernet PHY chip is electrically connected with the Ethernet connector; the power supply circuit comprises an AC-DC module, a DC-DC isolation module A, a voltage conversion chip A and a voltage conversion chip B, DC-DC isolation module B; the AC-DC module is connected into the AC220V, and the output end of the AC-DC module is connected with the input end of the DC-DC isolation module A, DC-DC isolation module B; the output end of the DC-DC isolation module A is connected with the input ends of the voltage conversion chip A and the voltage conversion chip B; the output end of the DC-DC isolation module A, the output end of the voltage conversion chip B and the output end of the DC-DC isolation module B are connected with the ground in common;

the output control circuit comprises a relay, a driving chip and an isolation chip, wherein an I/O port of the FPGA chip is connected with one end of the isolation chip, the other end of the isolation chip is connected with one end of the driving chip, the other end of the driving chip is connected with a coil end of the relay, and nine groups of relay output control channels are formed through the connection mode;

the ammeter communication interface circuit, the touch display screen communication interface circuit and the IC card communication interface circuit all comprise RS232 interface chips and isolation chips, an I/O port of the FPGA chip is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the RS232 interface chip;

the insulation monitoring module communication circuit comprises an RS485 interface chip and an isolation chip, wherein an I/O port of the FPGA chip is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the RS485 interface chip;

the charging module communication interface circuit and the charging communication interface circuit both comprise a CAN interface chip and an isolation chip, wherein an I/O port of the FPGA chip is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the CAN interface chip;

the CC1 detection circuit comprises a V/F conversion chip and an isolation chip, wherein an I/O port of the FPGA chip is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the V/F conversion chip;

furthermore, the internal digital logic of the FPGA chip comprises a charging gun A signal processing module, a charging gun B signal processing module, a charging gun C signal processing module, a charging gun D signal processing module, an IC card signal processing module and a touch screen signal processing module; the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module, the charging gun D signal processing module, the IC card signal processing module and the touch screen signal processing module are connected with an address signal line, a data signal line, a write control signal line, a read control signal line and a CLK clock signal line; the address signal wire, the data signal wire, the write control signal wire, the read control signal wire and the CLK clock signal wire form a communication bus to be connected with the FSMC interface of the main control chip; the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module and the charging gun D signal processing module respectively output interrupt 0 signals, interrupt 1 signals, interrupt 2 signals and interrupt 3 signals to be connected with interrupt signal input ends of EXTI0, EXTI1, EXTI2 and EXTI3 of the main control chip;

the internal digital logic of the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module and the charging gun D signal processing module comprises a frequency counter module, a CAN bus interface A module, a CAN bus interface B module, a UART interface A module, a UART interface B module and an output control module; the frequency counter module collects an output signal of the CC1 detection circuit, and a transmission FIFO module is arranged in the frequency counter module; the CAN bus interface A module is connected and communicated with the charging module communication interface circuit, and a transmitting FIFO module and a receiving FIFO module are arranged in the CAN bus interface A module; the CAN bus interface B module is connected with the charging communication interface circuit for communication, and a transmitting FIFO module and a receiving FIFO module are arranged in the CAN bus interface B module; the UART interface A module is connected and communicated with the ammeter communication interface circuit, and a transmitting FIFO module and a receiving FIFO module are arranged in the UART interface A module; the UART interface B module is connected and communicated with the insulation monitoring module communication circuit, and a transmitting FIFO module and a receiving FIFO module are arranged in the UART interface B module; the output control module is in control connection with the output control circuit, and a state register is arranged in the output control module;

the touch screen signal processing module is a UART interface C module with a transmitting FIFO module and a receiving FIFO module, and the UART interface C module is connected and communicated with the touch display screen communication interface circuit; the IC card signal processing module is a UART interface D module with a transmitting FIFO module and a receiving FIFO module, and the UART interface D module is connected and communicated with the IC card communication interface circuit;

the address signal line and the read control signal line are respectively connected with a frequency counter module, a CAN bus interface A module, a CAN bus interface B module, a UART interface A module, a UART interface B module, a touch screen signal processing module and a read data enabling end of a transmission FIFO module of the IC card signal processing module after logic and operation;

the address signal line and the write control signal line are respectively connected with a CAN bus interface A module, a CAN bus interface B module, a UART interface A module, a UART interface B module, a touch screen signal processing module, a write data enabling end of a receiving FIFO module of the IC card signal processing module and a write data enabling end of a state register of the output control module after logic and operation are carried out on the address signal line and the write control signal line;

the data signal line is connected with the frequency counter module, the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the data output end of the transmitting FIFO module of the IC card signal processing module, the data input end of the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the data input end of the receiving FIFO module of the IC card signal processing module and the data input end of the status register of the control module;

the CLK clock signal line is connected with the frequency counter module, the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the data reading clock end of the transmitting FIFO module of the IC card signal processing module, the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the data writing clock end of the receiving FIFO module of the IC card signal processing module and the data writing clock end of the status register of the control module;

furthermore, the read full flag bit of the transmission FIFO module of the frequency counter module is output to form an interrupt signal.

A control method using the direct current charging pile controller comprises the following steps,

step S1: the method comprises the steps of initializing an EXTI0, an EXTI1, an EXTI2, an EXTI3 interrupt, an Ethernet interface and an FSMC interface;

step S2: entering a main control program, and executing a touch screen control step S21, an IC card control step S22, a charging control step S23 and an Ethernet communication step S24;

step S3: when the EXTI0, the EXTI1, the EXTI2 and the EXTI3 interrupt signals trigger, executing an interrupt 0/1/2/3 subroutine, and returning to the step S2 after the execution is finished;

in the step S3, when an interrupt signal is triggered, the main control chip executes an FSMC read instruction to the frequency counter module of the corresponding charging gun signal processing module through the FSMC interface, obtains CC1 status data, and returns to the step S2; when the voltage state of CC1 is 4V, starting to execute the steps of locking the electronic lock of the charging gun and controlling the output of the auxiliary power supply in the charging control step S23, after the step of controlling the output of the auxiliary power supply is completed, sending a handshake message to the charging automobile, after the sending of the handshake message is completed, successfully receiving a return message from the charging automobile, starting to execute the steps of insulation monitoring and voltage releasing, after the voltage releasing is completed, sending a message confirmation to the charging automobile, confirming the return message of the charging automobile, executing the step of closing and electrifying after the confirmation is completed, and starting to output electric energy to the charging automobile; during charging, according to the message data of the charging automobile, the main control chip communicates with the charging module to execute a current regulation step and read ammeter data in real time; when the charging automobile returns a message to finish charging, sequentially executing the steps of power failure stopping, voltage releasing, auxiliary power supply output cutting and electronic lock unlocking; the touch screen control step S21 includes reading operation instruction data input by an operator to the touch screen and writing charging state information data into the touch screen; inputting operation instruction data including starting charging and ending charging; the charging state information comprises charging preparation, charging and charging ending states; the IC card control step S22 includes reading and writing the IC card information, deducting fee, and judging balance; the ethernet communication step S24 includes sending electric meter data and charging status information, and receiving charging start-stop instruction data from the internet.

Preferably, when the touch screen control step S21, the IC card control step S22, and the charging control step S23 are executed, the main control chip and the external communication are all completed by performing read/write operations on the FSMC interface.

Preferably, the charging control step S23 sets a charging state variable, and the charging state variable changes in real time according to a message of the charging vehicle, IC card information, an internet charging start/stop instruction, and an input operation of the touch screen; a charging control step S23 executes a closing power-on and power-off stopping step according to the charging state variable; the ethernet communication step S24 updates the transmitted charge state information in real time according to the charge state variable; the touch screen control step S21 updates the written charge state information data in real time according to the charge state variable.

Compared with the prior art, the invention has the following beneficial effects:

the invention provides a new solution for the direct current charging pile, which consists of an FPGA, a singlechip and a peripheral circuit, wherein each group of charging gun signal processing modules arranged in the FPGA controls one charging gun to charge, different module data are read and written by matching address signals with read control and write control signals, and the control and communication of corresponding peripheral equipment are completed, so that the four charging guns of the integrated direct current charging pile are realized and perform charging, the advantages of FPGA logic control resources and multiple interfaces are fully exerted, the use of peripheral interfaces of the singlechip is reduced, the processing burden of a singlechip program is further lightened, and the integration level of a controller and the operating efficiency of a main control program are improved.

Drawings

FIG. 1 is a block diagram of a DC charging pile controller according to the present invention;

FIG. 2 is a block diagram of the charging gun A/B/C/D control circuit of the DC charging pile controller according to the present invention;

fig. 3 is a circuit connection diagram of a main control chip, an FPGA chip and an ethernet interface of the dc charging pile controller according to the present invention;

FIG. 4 is a connection diagram of a power supply circuit of a DC charging pile controller according to the present invention;

FIG. 5 is a circuit diagram of the charging gun A/B/C/D control circuit of the DC charging pile controller according to the present invention;

FIG. 6 is a circuit diagram of a touch screen and an IC card communication interface circuit of the DC charging pile controller according to the present invention;

FIG. 7 is a connection structure diagram of an internal digital logic module of an FPGA chip of the DC charging pile controller according to the present invention;

FIG. 8 is a block diagram of the digital logic connections of the A/B/C/D signal processing block of the charging gun of FIG. 7;

FIG. 9 is a diagram of the digital logic connection structure of the IC card signal processing module and the touch screen signal processing module of FIG. 7;

fig. 10 shows the overall steps of the control method of the dc charging pile controller according to the present invention;

FIG. 11 is a block diagram of the control flow of steps S2, S3 in FIG. 10;

Detailed Description

The drawings in the embodiments of the invention will be combined; the technical scheme in the embodiment of the invention is clearly and completely described as follows:

as shown in fig. 1, in an embodiment of the present invention, a dc charging pile controller includes a main control chip 1, an FPGA chip 2, an ethernet interface 3, a charging gun a control circuit 4, a charging gun B control circuit 5, a charging gun C control circuit 6, a charging gun D control circuit 7, a touch display screen communication interface circuit 8, an IC card communication interface circuit 9, and a power supply circuit 10; the charging gun A control circuit 4, the charging gun B control circuit 5, the charging gun C control circuit 6, the charging gun D control circuit 7, the touch display screen communication interface circuit 8 and the IC card communication interface circuit 9 are respectively and electrically connected with the FPGA chip 2; the FPGA chip 2 is electrically connected with the main control chip 1 through signal lines of interrupt 0, interrupt 1, interrupt 2 and interrupt 3 and a communication bus; the Ethernet interface 3 is electrically connected with the main control chip 1; the power supply circuit 10 supplies power to each chip and circuit;

as shown in fig. 2, the charging gun a control circuit 4, the charging gun B control circuit 5, the charging gun C control circuit 6 and the charging gun D control circuit 7 comprise an output control circuit 401, an electric meter communication interface circuit 402, an insulation monitoring module communication circuit 403, a charging module communication interface circuit 404, a charging communication interface circuit 405 and a CC1 detection circuit 406; the output control circuit 401 comprises nine groups of control channels, a first group of control operation indicator lamps, a second group of control fault indicator lamps, a third group of control cooling fans, a fourth group and a fifth group which respectively control the switching and the output of an auxiliary power supply, a sixth group of control charging gun output, a seventh group of control discharge loop switching, and an eighth group and a ninth group of control charging gun electronic locks for locking and unlocking; .

As shown in fig. 3-6, the specific circuit connection diagram of the present invention is shown, in which the related chips, power signals, and data transmission signal connections mainly shown in the diagram are omitted, and the peripheral auxiliary circuits of the chips may be referred to the disclosed chip manual; in a specific embodiment of the present invention, the I/O port of the FPGA chip 2 is electrically connected to the FSMC interface of the main control chip 1 and the EXTI0, EXTI1, EXTI2, and EXTI3 interrupt signal input ports, and bus communication is implemented by using the FSMC interface; the ethernet interface 3 comprises an ethernet PHY chip 31 and an ethernet connector 32; the RMII interface of the main control chip 1 is electrically connected with the ethernet PHY chip 31, and the ethernet PHY chip 31 is electrically connected with the ethernet connector 32; the power supply circuit 10 comprises an AC-DC module 101, a DC-DC isolation module A102, a voltage conversion chip A103, a voltage conversion chip B104 and a DC-DC isolation module B105; the AC-DC module 101 is connected with the AC220V, and the output end of the AC-DC module is connected with the input ends of the DC-DC isolation module A102 and the DC-DC isolation module B105; the output end of the DC-DC isolation module A102 is connected with the input ends of a voltage conversion chip A103 and a voltage conversion chip B104; the output end of the DC-DC isolation module A102, the output end of the voltage conversion chip A103, the output end of the voltage conversion chip B104 and the output end of the DC-DC isolation module B105 are connected with the ground in common;

the output control circuit 401 includes a relay (ADL 105), a driver chip (ULN2803), and an isolator chip (addm 160N), wherein an I/O port of the FPGA chip 2 is connected to one end of the isolator chip, the other end of the isolator chip is connected to one end of the driver chip, and the other end of the driver chip is connected to a coil end of the relay, so as to form nine sets of relay output control channels through the above connection method, note that only the circuit connection of one set of channels is shown in fig. 5;

the ammeter communication interface circuit 402, the touch display screen communication interface circuit 8 and the IC card communication interface circuit 9 respectively comprise an RS232 interface chip (MAX232) and an isolation chip (AduM 1201), wherein an I/O port of the FPGA chip 2 is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the RS232 interface chip;

the insulation monitoring module communication circuit 403 comprises an RS485 interface chip (MAX485) and an isolation chip (AduM 1201), wherein an I/O port of the FPGA chip 2 is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the RS485 interface chip;

the charging module communication interface circuit 404 and the charging communication interface circuit 405 both comprise a CAN interface chip (TJA 1050) and an isolation chip (AduM 1201), wherein the I/O port of the FPGA chip 2 is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the CAN interface chip; the charging communication interface circuit realizes the communication between the controller and the charging automobile, and the charging module communication interface circuit realizes the communication between the controller and the charging module;

the CC1 detection circuit 406 comprises a V/F conversion chip (AD 654 JR) and an isolation chip (Adu 1100), wherein an I/O port of the FPGA chip 2 is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the V/F conversion chip;

as shown in fig. 7, the digital logic inside the FPGA chip 2 includes a charging gun a signal processing module 201, a charging gun B signal processing module 202, a charging gun C signal processing module 203, a charging gun D signal processing module 204, an IC card signal processing module 205, and a touch screen signal processing module 206; the charging gun A signal processing module 201, the charging gun B signal processing module 202, the charging gun C signal processing module 203, the charging gun D signal processing module 204, the IC card signal processing module 205 and the touch screen signal processing module 206 are connected with an address signal line, a data signal line, a write control signal line, a read control signal line and a CLK clock signal line; the address signal wire, the data signal wire, the write control signal wire, the read control signal wire and the CLK clock signal wire form a communication bus 207 which is connected with the FSMC interface of the main control chip 1; the charging gun A signal processing module 201, the charging gun B signal processing module 202, the charging gun C signal processing module 203 and the charging gun D signal processing module 204 respectively output interrupt 0 signals, interrupt 1 signals, interrupt 2 signals and interrupt 3 signals to be connected with interrupt signal input ends of EXTI0, EXTI1, EXTI2 and EXTI3 of the main control chip 1; each group of charging gun signal processing modules controls one charging gun to charge, when a charging gun is connected, the corresponding charging gun signal processing module outputs an interrupt signal, and the main control chip 1 receives the interrupt signal to make a response to implement charging operation;

as shown in fig. 8, the internal digital logic of the charging gun a signal processing module 201, the charging gun B signal processing module 202, the charging gun C signal processing module 203, and the charging gun D signal processing module 204 includes a frequency counter module 2010, a CAN bus interface a module 2011, a CAN bus interface B module 2012, a UART interface a module 2013, a UART interface B module 2014, and an output control module 2015; the frequency counter module 2010 collects output signals of the CC1 detection circuit 406, and a transmission FIFO module (a first-in first-out data buffer, which is the same as the existing one and has a write data enable end, a write data clock end, a data input end, a write full flag, a write empty flag, a read data enable end, a read data clock end, a read full flag, a read empty flag, etc.) is arranged in the frequency counter module 2010; the CAN bus interface a module 2011 is connected and communicated with the charging module communication interface circuit 404, and a transmitting FIFO module and a receiving FIFO module are arranged in the CAN bus interface a module 2011; the CAN bus interface B module 2012 is connected with the charging communication interface circuit 405 for communication, and a transmitting FIFO module and a receiving FIFO module are arranged in the CAN bus interface B module 2012; the UART interface A module 2013 is connected with the electric meter communication interface circuit 402 for communication, and a transmitting FIFO module and a receiving FIFO module are arranged in the UART interface A module 2013; the UART interface B module 2014 is connected with the insulation monitoring module communication circuit 403 for communication, and a transmitting FIFO module and a receiving FIFO module are arranged in the UART interface B module 2014; the output control module 2015 is in control connection with the output control circuit 401, the output control module 2015 is provided with a state register, and the logic expression of the output control module 2015 is changed by writing internal data of the state register, so that the output level of the output control circuit 401 is changed;

as shown in fig. 9, the touch screen signal processing module 205 is a UART interface C module with a transmit FIFO module and a receive FIFO module, and the UART interface C module is connected to the touch screen communication interface circuit 8 for communication; the IC card signal processing module 206 is a UART interface D module with a transmitting FIFO module and a receiving FIFO module, and the UART interface D module is connected with the IC card communication interface circuit 9 for communication;

the address signal line and the read control signal line are respectively connected with the read data enabling end of the sending FIFO module of the frequency counter module 2010, the CAN bus interface a module 2011, the CAN bus interface B module 2012, the UART interface a module 2013, the UART interface B module 2014, the touch screen signal processing module 205 and the IC card signal processing module 206 after being subjected to logic and operation, and it is noted that the address signal line is a multi-bit address bus signal, and a one-bit address corresponds to one sending FIFO module read data enabling end;

the address signal line and the write control signal line are respectively connected with a CAN bus interface A module 2011, a CAN bus interface B module 2012, a UART interface A module 2013, a UART interface B module 2014, a touch screen signal processing module 205, a write data enabling end of a receiving FIFO module of the IC card signal processing module 206 and a write data enabling end of a state register of the output control module 2015 after logic and operation are carried out on the address signal line and the write control signal line;

the data signal line is connected with a frequency counter module 2010, a CAN bus interface A module 2011, a CAN bus interface B module 2012, a UART interface A module 2013, a UART interface B module 2014, a touch screen signal processing module 205, a data output end of a transmitting FIFO module of the IC card signal processing module 206, a CAN bus interface A module 2011, a CAN bus interface B module 2012, a UART interface A module 2013, a UART interface B module 2014, a touch screen signal processing module 205, a data input end of a receiving FIFO module of the IC card signal processing module 206 and a data input end of a status register of a control module 2015;

the CLK clock signal line is connected to the frequency counter module 2010, the CAN bus interface a module 2011, the CAN bus interface B module 2012, the UART interface a module 2013, the UART interface B module 2014, the touch screen signal processing module 205, the read data clock terminal of the transmit FIFO module of the IC card signal processing module 206, the CAN bus interface a module 2011, the CAN bus interface B module 2012, the UART interface a module 2013, the UART interface B module 2014, the touch screen signal processing module 205, the write data clock terminal of the receive FIFO module of the IC card signal processing module 206, and the write data clock terminal of the status register of the control module 2015;

the full flag bit output of the sending FIFO module of the frequency counter module 2010 forms interrupt signals, i.e., an interrupt 0 signal, an interrupt 1 signal, an interrupt 2 signal, and an interrupt 3 signal (the frequency counter module of each charging gun signal processing module outputs one interrupt signal).

After the charging gun is connected, the CC1 detects the output signal of the circuit 406, the frequency counter module 2010 counts, and when the transmission FIFO module is full, an interrupt signal is triggered and transmitted to the main control chip 1.

During specific work, when the controller reads data from the peripheral interface, the bus interface 207 reads a control signal to be effective, and simultaneously outputs a corresponding address signal bit to select a corresponding transmission FIFO module to read internal data to a data signal line, and the internal data is received by the main control chip 1; when the controller writes data to the external interface, the bus interface 207 writes the control signal to be valid, and outputs the corresponding address signal bit to select the corresponding receiving FIFO module or the state register, so as to store the data on the data signal line, and the external interface sends the data out.

As shown in fig. 10, a method for controlling a dc charging pile controller includes,

as shown in fig. 11, specifically, when an interrupt signal is triggered, the main control chip 1 executes an FSMC read instruction to the frequency counter module 2010 of the corresponding charging gun signal processing module through the FSMC interface, obtains CC1 status data, and returns to step S2; when the voltage state of CC1 is 4V, the locking of the electronic lock of the charging gun and the output control step of the auxiliary power supply in the charging control step S23 are started, after the output control step of the auxiliary power supply is completed, a handshake message is sent to the charging automobile, after the handshake message is sent, a return message from the charging automobile is successfully received, the insulation monitoring and voltage releasing steps are started, the voltage releasing is completed, a message confirmation is sent to the charging automobile, the message confirmation is returned to the charging automobile, after the confirmation is completed, the closing and electrifying step is executed, the electric energy is started to be output to the charging automobile, and during charging, according to the message data of the charging automobile, the main control chip 1 and the charging module are communicated to execute the current regulation step and read; when the charging automobile returns a message to finish charging, sequentially executing the steps of power failure stopping, voltage releasing, auxiliary power supply output cutting and electronic lock unlocking;

specifically, when the touch screen control step S21, the IC card control step S22, and the charge control step S23 are executed, the communication between the main control chip 1 and the outside is completed by performing read/write operations on the FSMC interface, so that the main control chip 1 is prevented from directly operating and controlling the corresponding peripheral, the peripheral configuration programs are reduced, and the operating efficiency of the main control program is improved.

Specifically, the touch screen controlling step S21 includes executing reading of operation instruction data input by an operator to the touch screen and writing of charge state information data to the touch screen; inputting operation instruction data including starting charging and ending charging; the charging state information comprises charging preparation, charging and charging ending states;

specifically, the IC card control step S22 includes reading and writing the IC card information, deducting fees, and determining balance;

specifically, the ethernet communication step S24 includes sending electric meter data and charging status information, and receiving charging start-stop instruction data from the internet.

Specifically, a charging state variable is set in the charging control step S23, and the charging state variable is changed in real time according to a message of the charging automobile, IC card information, an internet charging start-stop instruction, and an input operation of the touch screen; a charging control step S23 executes a closing power-on and power-off stopping step according to the charging state variable; the ethernet communication step S24 updates the transmitted charge state information in real time according to the charge state variable; the touch screen control step S21 updates the written charge state information data in real time according to the charge state variable. The charging state variables at least comprise a charging start-stop flag bit, current charging voltage and current data information, IC card balance information, auxiliary source state and charging fault information.

Specifically executing a charging control step S23, performing FSMC read instruction and FSMC write instruction operations on different address intervals according to different interrupt signals, and realizing charging control on different charging guns; in specific implementation, 26-bit addresses of [25:0] of the FSMC interface can be connected to an address signal line of the bus interface 207, wherein the address interval of [5:0] is allocated to the charging gun a signal processing module 201 and corresponds to 6 modules included in the charging gun a signal processing module, the same address interval of [11:6] is allocated to the charging gun B signal processing module 202, the address interval of [17:12] is allocated to the charging gun C signal processing module 203, and the address interval of [23:18] is allocated to the charging gun D signal processing module 205; when the touch screen control step S21 and the IC card control step S22 are executed, the remaining [25:24] are respectively allocated to the touch screen signal processing module 205 and the IC card signal processing module 206; the read-write of different module data is realized by matching the address signal with the read control signal and the write control signal, and the control and communication of corresponding peripheral equipment are completed.

Claims

1. The utility model provides a direct current fills electric pile controller which characterized in that: the intelligent charging system comprises a main control chip, an FPGA chip, an Ethernet interface, a charging gun A control circuit, a charging gun B control circuit, a charging gun C control circuit, a charging gun D control circuit, a touch display screen communication interface circuit, an IC card communication interface circuit and a power supply circuit; the charging gun A control circuit, the charging gun B control circuit, the charging gun C control circuit, the charging gun D control circuit, the touch display screen communication interface circuit and the IC card communication interface circuit are respectively and electrically connected with the FPGA chip; the FPGA chip is electrically connected with the main control chip through interrupt 0, interrupt 1, interrupt 2 and interrupt 3 signal lines and a communication bus; the Ethernet interface is electrically connected with the main control chip; the power supply circuit supplies power to each chip and circuit.

2. The dc charging pile controller according to claim 1, wherein: the charging gun A control circuit, the charging gun B control circuit, the charging gun C control circuit and the charging gun D control circuit comprise output control circuits, ammeter communication interface circuits, insulation monitoring module communication circuits, charging module communication interface circuits, charging communication interface circuits and CC1 detection circuits; the output control circuit comprises nine groups of control channels, a first group of control operation indicator lamps, a second group of control fault indicator lamps, a third group of control cooling fans, a fourth group and a fifth group which respectively control the switching and the output of an auxiliary power supply, a sixth group of control charging gun output, a seventh group of control discharge loop switching, and an eighth group and a ninth group of control charging gun electronic locks for locking and unlocking;

the CC1 detection circuit comprises a V/F conversion chip and an isolation chip, wherein an I/O port of the FPGA chip is connected with one end of the isolation chip, and the other end of the isolation chip is connected with one end of the V/F conversion chip.

3. The dc charging pile controller according to claim 2, wherein: the FPGA chip is internally provided with digital logic and comprises a charging gun A signal processing module, a charging gun B signal processing module, a charging gun C signal processing module, a charging gun D signal processing module, an IC card signal processing module and a touch screen signal processing module; the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module, the charging gun D signal processing module, the IC card signal processing module and the touch screen signal processing module are connected with an address signal line, a data signal line, a write control signal line, a read control signal line and a CLK clock signal line; the address signal wire, the data signal wire, the write control signal wire, the read control signal wire and the CLK clock signal wire form a communication bus to be connected with the FSMC interface of the main control chip; the charging gun A signal processing module, the charging gun B signal processing module, the charging gun C signal processing module and the charging gun D signal processing module respectively output interrupt 0 signals, interrupt 1 signals, interrupt 2 signals and interrupt 3 signals to be connected with interrupt signal input ends of EXTI0, EXTI1, EXTI2 and EXTI3 of the main control chip;

the CLK clock signal line is connected with the frequency counter module, the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the data reading clock end of the transmitting FIFO module of the IC card signal processing module, the CAN bus interface A module, the CAN bus interface B module, the UART interface A module, the UART interface B module, the touch screen signal processing module, the data writing clock end of the receiving FIFO module of the IC card signal processing module and the data writing clock end of the status register of the control module.

4. The direct current charging pile controller according to claim 3, wherein: and the read full zone bit of the transmission FIFO module of the frequency counter module is output to form an interrupt signal.

5. The control method of the direct current charging pile controller according to claim 4, characterized in that: comprises the following steps of preparing a mixture of a plurality of raw materials,

step S3: when the EXTI0, the EXTI1, the EXTI2 and the EXTI3 interrupt signals trigger, the interrupt 0/1/2/3 subroutine is executed, and the step S2 is returned to after the execution is finished.

6. The control method of the direct current charging pile controller according to claim 5, characterized in that: in the step S3, when an interrupt signal is triggered, the main control chip executes an FSMC read instruction to the frequency counter module of the corresponding charging gun signal processing module through the FSMC interface, obtains CC1 status data, and returns to the step S2; when the voltage state of CC1 is 4V, starting to execute the steps of locking the electronic lock of the charging gun and controlling the output of the auxiliary power supply in the charging control step S23, after the step of controlling the output of the auxiliary power supply is completed, sending a handshake message to the charging automobile, after the sending of the handshake message is completed, successfully receiving a return message from the charging automobile, starting to execute the steps of insulation monitoring and voltage releasing, after the voltage releasing is completed, sending a message confirmation to the charging automobile, confirming the return message of the charging automobile, executing the step of closing and electrifying after the confirmation is completed, and starting to output electric energy to the charging automobile; during charging, according to the message data of the charging automobile, the main control chip communicates with the charging module to execute a current regulation step and read ammeter data in real time; when the charging automobile returns a message to finish charging, sequentially executing the steps of power failure stopping, voltage releasing, auxiliary power supply output cutting and electronic lock unlocking; the touch screen control step S21 includes reading operation instruction data input by an operator to the touch screen and writing charging state information data into the touch screen; inputting operation instruction data including starting charging and ending charging; the charging state information comprises charging preparation, charging and charging ending states; the IC card control step S22 includes reading and writing the IC card information, deducting fee, and judging balance; the ethernet communication step S24 includes sending electric meter data and charging status information, and receiving charging start-stop instruction data from the internet.

7. The control method of the direct-current charging pile controller according to claim 6, characterized in that: when the touch screen control step S21, the IC card control step S22, and the charging control step S23 are executed, the communication between the main control chip and the outside is completed by performing read/write operations on the FSMC interface.

8. The control method of the direct-current charging pile controller according to claim 6, characterized in that: the charging control step S23 is characterized in that a charging state variable is set, and the charging state variable is changed in real time according to messages of a charging automobile, IC card information, an Internet charging start-stop instruction and input operation of a touch screen; a charging control step S23 executes a closing power-on and power-off stopping step according to the charging state variable; the ethernet communication step S24 updates the transmitted charge state information in real time according to the charge state variable; the touch screen control step S21 updates the written charge state information data in real time according to the charge state variable.