CN111696480B

CN111696480B - OLED pixel compensation circuit and driving method

Info

Publication number: CN111696480B
Application number: CN202010522533.1A
Authority: CN
Inventors: 郑剑花; 郭平昇
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2020-06-10
Filing date: 2020-06-10
Publication date: 2023-10-03
Anticipated expiration: 2040-06-10
Also published as: CN111696480A

Abstract

An OLED pixel compensation circuit and a driving method, wherein the pixel compensation circuit comprises thin film transistors T1, T2, T3, T4, T5, T6, T7, T8 and T9, wherein the source electrode of the T1 is connected with the source electrodes of on-chip high voltages VGH and T7 and the source electrode of the T6, the grid electrode of the T1 is connected with the grid electrodes of clock signals ECK1 and T5, and the drain electrode of the T1 is connected with the source electrode of the T2, the grid electrode of the T7 and one end of a capacitor CB; compared with the prior art, the driving circuit capable of generating an EM compensation signal at each stage is realized, and the loss generated by RC delay is compensated, so that the input signal is simplified, and the display effect is better.

Description

OLED pixel compensation circuit and driving method

Technical Field

The invention relates to the field of panel design, in particular to an OLED pixel compensation circuit and a driving method design.

Background

In existing commercial displays, the ICs are typically located on the short side and the GIP traces are located on the long side. The source trace of such a commercial display is longer and data will gradually decrease as RCdelay on the source trace increases. Therefore, as the wiring distance increases, RCdelay increases, the pixel electrode voltage writing becomes smaller, and the screen brightness decreases. Therefore, a sourceinene overdrive method is proposed to compensate the pixel electrode voltage, so as to avoid the phenomenon of brightness reduction.

Disclosure of Invention

Therefore, it is desirable to provide an internal compensation circuit that addresses the problem of reduced display pixel voltage.

For this purpose, we provide an OLED pixel compensation circuit comprising thin film transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, the source of T1 being connected to the source of the on-chip high voltage VGH, T7 and the source of T6, the gate of T1 being connected to the gates of the clock signals ECK1 and T5, the drain of T1 being connected to the source of T2, the gate of T7 and one end of the capacitor CB; the drain electrode of the T7 is connected with the other end of the capacitor CB, the grid electrode of the T6 and the source electrode of the T8, the drain electrode of the T6 is connected with the drain electrode of the T8 and the source electrode of the T9, the grid electrode of the T2 is connected with the drain electrode of the T4, the grid electrode of the T8, the grid electrode of the T9 and the source electrode of the T5, the source electrode of the T4 is connected with the reset signal RST, the grid electrode is connected with the current-stage driving signal Gn, and the drain electrodes of the T2, the T5 and the VGL are connected; the drain electrode of the T7 is also connected with the output end of the compensation signal EMn.

The OLED pixel compensation circuit driving method is suitable for the OLED pixel compensation circuit and comprises the following steps:

the first stage, the input signal of the current stage is high level, clock signal and reset signal are low level;

the second stage, the input signal of the current stage keeps high level, the reset signal is high level, the clock signal is low level;

the third stage, the input signal of the current stage keeps high level, reset signal and clock signal low level;

a fourth stage, namely, a low level of a current-stage input signal, a reset signal and a clock signal;

and fifth stage, the input signal of the current stage is low level, the clock signal is high level, and the reset signal is raised to high level after being kept low level.

Compared with the prior art, the driving circuit capable of generating an EM compensation signal at each stage is realized, and the loss generated by RCdelay is compensated, so that the input signal is simplified, and the display effect is better.

Drawings

FIG. 1 is a schematic diagram of a compensation circuit according to an embodiment;

fig. 2 is a schematic diagram of a driving waveform according to an embodiment.

Detailed Description

In order to describe the technical content, constructional features, achieved objects and effects of the technical solution in detail, the following description is made in connection with the specific embodiments in conjunction with the accompanying drawings.

Referring to fig. 1, an OLED pixel compensation circuit includes thin film transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9, wherein a source of the T1 is connected to sources of on-chip high voltages VGH and T7 and a source of the T6, a gate of the T1 is connected to gates of clock signals ECK1 and T5, and a drain of the T1 is connected to a source of the T2, a gate of the T7, and one end of a capacitor CB; the drain electrode of the T7 is connected with the other end of the capacitor CB, the grid electrode of the T6 and the source electrode of the T8, the drain electrode of the T6 is connected with the drain electrode of the T8 and the source electrode of the T9, the grid electrode of the T2 is connected with the drain electrode of the T4, the grid electrode of the T8, the grid electrode of the T9 and the source electrode of the T5, the source electrode of the T4 is connected with the reset signal RST, the grid electrode is connected with the current-stage driving signal Gn, and the drain electrodes of the T2, the T5 and the VGL are connected; the drain electrode of the T7 is also connected with the output end of the compensation signal EMn. Such an OLED pixel compensation circuit, after being properly driven, is capable of generating one compensation signal EMn for each stage (n). The driving method of the pixel compensation circuit is as follows:

in the embodiment shown in fig. 2, the following phases are included:

first stage t1: the current input signal is high, the clock signal and the reset signal are low, T4 is opened, and EMn maintains the high level of the previous frame.

Second stage t2: the input signal of the current stage keeps high level, the reset signal is high level, the clock signal is low level; t4, T2, T8 and T9 are turned on and the EMn is pulled to low by VGL.

Third stage t3: the current-stage input signal keeps high level, and the reset signal and clock signal are low level; t4 is turned on, and EMn maintains the low level of the last stage.

Fourth stage t4: the current stage input signal, the reset signal and the clock signal are low level; all TFTs are turned off and the EMn is maintained at low level.

Fifth stage t5: the input signal of the current stage is low level, the clock signal is high level, the reset signal is raised to high level after being kept low level, T1, T5, T6 and T7 are opened, and EMn is pulled to high level by VGH.

The compensation signal EMn is pulled down by superposition of the current-stage driving signal Gn and the reset signal RST, and pulled up by ECK 1. Further, when the EMn is at the high level, T6 is turned on, and the intermediate T8 and T9 are at the high level, in which case, if T8 and T9 are turned on by mistake, the level of the EMn is not pulled down by VGL. Thus, the effect of T6 ensures that EMn is not pulled low at high levels.

In other embodiments, when the panel is at the first frame of the power-on state, the EMn has no high level of the previous frame in the first stage, and the two OLED driving voltages OVDD/OVSS, that is, the anode and cathode voltages at the two ends of the OLED light emitting diode, are applied one frame later, so that the human eyes will not see the non-uniformity in the initial stage of the first frame.

It should be noted that, although the foregoing embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solution, directly or indirectly, to other relevant technical fields, all of which are included in the scope of the invention.

Claims

1. The OLED pixel compensation circuit driving method is characterized by being suitable for an OLED pixel compensation circuit, wherein the OLED pixel compensation circuit comprises thin film transistors T1, T2, T4, T5, T6, T7, T8 and T9, a source electrode of the T1 is connected with a source electrode of on-chip high voltage VGH and T7 and a source electrode of the T6, a grid electrode of the T1 is connected with grid electrodes of clock signals ECK1 and T5, and a drain electrode of the T1 is connected with a source electrode of the T2, a grid electrode of the T7 and one end of a capacitor CB; the drain electrode of the T7 is connected with the other end of the capacitor CB, the grid electrode of the T6 and the source electrode of the T8, the drain electrode of the T6 is connected with the drain electrode of the T8 and the source electrode of the T9, the grid electrode of the T2 is connected with the drain electrode of the T4, the grid electrode of the T8, the grid electrode of the T9 and the source electrode of the T5, the source electrode of the T4 is connected with the reset signal RST, the grid electrode is connected with the current-stage driving signal Gn, and the drain electrodes of the T2, the T5 and the VGL are connected; the drain electrode of the T7 is also connected with the output end of the compensation signal EMn; the method comprises the following stages: