CN214011960U - GIP circuit for improving display stability - Google Patents
GIP circuit for improving display stability Download PDFInfo
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- CN214011960U CN214011960U CN202023006169.8U CN202023006169U CN214011960U CN 214011960 U CN214011960 U CN 214011960U CN 202023006169 U CN202023006169 U CN 202023006169U CN 214011960 U CN214011960 U CN 214011960U
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Abstract
The utility model discloses a promote GIP circuit that shows stability, including transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, transistor T10, electric capacity C1, electric capacity C2 and electric capacity C3; the above technical solution outputs data of the gate line g (n) through the transistor T4, and controls the voltage level of the node Q2 through the transistor T8, the transistor T9 and the transistor T10. And the leakage of the node Q1 is also prevented, so that a GIP output signal of a subsequent output stage of the GIP circuit has no abnormity, and the problem of dark fringe display of a general GIP circuit after touch is solved. The structure solves the problem that output signals of the GIP circuit are distorted in different touch modes, can improve the display quality and the touch quality of the display panel, improves the appearance of the display panel, and further improves the competitiveness of the display panel.
Description
Technical Field
The utility model relates to a show technical field, especially relate to a promote GIP circuit that shows stability.
Background
The touch technology is mainly divided into an On-Cell technology and an In-Cell technology at present, wherein the On-Cell technology is that a touch screen is embedded between a display screen and a polarizer, namely a touch sensor is arranged On a display panel; the In-Cell technology is to embed the touch panel function into the Array substrate, so that the thickness of the In-Cell panel is reduced due to the fact that the thickness of the touch screen is reduced by one layer.
The display panel adopting the In-Cell technology has the advantages of lighter product, lower thickness, better light transmission, reduction of the time for attaching the screen, improvement of the production efficiency and the like. However, the display panel using the In-Cell technology has some problems when performing touch control In different ways.
The In-Cell display panel is divided into two modes during touch display: referring to fig. 1, the first mode may be referred to as a Long V Touch Display mode, where when a frame is displayed, the Long V Touch Display mode is divided into a Display Time and a Blanking Time (a Touch is inserted into the Blanking Time), that is, a sum of two Time periods is a Time of one frame after Touch is placed after Display. Referring to fig. 2, the second mode may be referred to as a Long H Touch Display mode, in which Touch is inserted into Display in batches when a frame is displayed, i.e., a frame is divided into Display (i.e., Display) -Touch (i.e., Touch) -Display-Touch-Display in a cyclic manner from top to bottom. When the Long H touch display mode is performed, since the touch stage is inserted into the display stage, when the GIP design is adopted, since a touch stage is inserted between two display stages, the Q node of the GIP circuit of the second display stage is to maintain a high potential (about 200 us) for a Long time, and due to the leakage problem of the transistor, the Q node of the second display stage has a large leakage problem, so that the Q node of the first row GIP of the second display stage and the Q node of the GIP of the first display stage have a large difference, thereby possibly causing a difference of output signals of the GIP of the display panel, and causing a problem of a horizontal dark line of the display panel.
SUMMERY OF THE UTILITY MODEL
Therefore, it is desirable to provide a GIP circuit for improving display stability, so as to solve the problem that a display panel has a horizontal dark line due to the influence of the GIP output signal caused by the leakage of the transistor.
In order to achieve the above object, the present embodiment provides a GIP circuit that improves display stability, including a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a capacitor C1, a capacitor C2, and a capacitor C3;
a control terminal of the transistor T1 and a control terminal of the transistor T8 are respectively connected to a gate line G (n-4), an input terminal of the transistor T1 and an input terminal of the transistor T8 are respectively connected to a turn-on voltage VGH, an output terminal of the transistor T1 is connected to a control terminal of the transistor T4, and an output terminal of the transistor T8 is connected to a control terminal of the transistor T9;
the input end of the transistor T9 is connected with a starting voltage VGH, and the output end of the transistor T9 is connected to a line connecting the output end of the transistor T1 and the control end of the transistor T4;
the control end of the transistor T2 is connected to a line on which the output end of the transistor T1 is connected to the control end of the transistor T4, the input end of the transistor T2 is connected to the control end of the transistor T3, the first plate of the capacitor C1 and the control end of the transistor T6, respectively, and the output end of the transistor T2, the output end of the transistor T3 and the output end of the transistor T6 are connected to the turn-off voltage VGL, respectively;
the second plate of the capacitor C1 is connected with the clock signal CK;
the input end of the transistor T3 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4;
the input end of the transistor T4 is connected to the clock signal CK, the output end of the transistor T4 is connected to the gate line G (n), the first plate of the capacitor C2 is connected to the control end of the transistor T4, and the second plate of the capacitor C2 is connected to a line connecting the output end of the transistor T4 and the gate line G (n);
the input end of the transistor T6 and the input end of the transistor T5 are respectively connected with a gate line G (n), the control end of the transistor T5 is connected with a clock signal CKB, and the output end of the transistor T5 is connected with a closing voltage VGL;
the control end of the transistor T7 is connected to the gate line G (n +4), the input end of the transistor T7 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4, and the output end of the transistor T7 is connected to the off-voltage VGL;
the control end of the transistor T10 is connected to the clock signal CK, the input end of the transistor T10 is connected to the line connecting the output end of the transistor T8 and the control end of the transistor T9, and the output end of the transistor T10 is connected to the off-voltage VGL;
the first plate of the capacitor C3 is connected with the output end of the transistor T8, and the second plate of the capacitor C3 is used for connecting external components.
Further, an input terminal of the transistor T1, an input terminal of the transistor T2, an input terminal of the transistor T3, an input terminal of the transistor T4, an input terminal of the transistor T5, an input terminal of the transistor T6, an input terminal of the transistor T7, an input terminal of the transistor T8, an input terminal of the transistor T9, and an input terminal of the transistor T10 are all drains.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, and the transistor T10 are all thin film transistors.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, the capacitor C1, and the capacitor C2 are all disposed on the display panel.
Further, the display panel is an In-Cell display panel.
Different from the prior art, the above technical solution outputs data of the gate line g (n) through the transistor T4, and controls the voltage level of the node Q2 through the transistor T8, the transistor T9 and the transistor T10. The leakage of the node Q1 can be prevented, the GIP output signal of the subsequent output stage of the GIP circuit of the stage has no abnormity, and the problem of dark fringe display of a general GIP circuit after touch control is solved. The structure solves the problem that output signals of the GIP circuit are distorted in different touch modes, provides a solution for realizing a high-definition display screen, can improve the display quality and the touch quality of the display panel, improves the impression of the display panel, and further improves the competitiveness of the display panel.
Drawings
Fig. 1 is a timing diagram of a Long V touch display mode according to the background art;
fig. 2 is a timing diagram of a Long H touch display mode according to the background art;
fig. 3 is a schematic structural diagram of the GIP circuit according to the present embodiment;
FIG. 4 is a timing diagram of the touch phase in the present embodiment;
FIG. 5 is a timing diagram of the display phase according to the present embodiment;
fig. 6 is a schematic structural diagram of the GIP circuit in the embodiment at the touch precharge stage;
fig. 7 is a schematic structural diagram of the GIP circuit in the touch voltage stabilization phase according to the present embodiment;
fig. 8 is a schematic structural diagram of the GIP circuit in the touch output stage according to the present embodiment;
fig. 9 is a schematic structural diagram of the GIP circuit in the touch pull-down stage according to the present embodiment;
fig. 10 is a schematic structural diagram of the GIP circuit in the touch pull-down hold stage according to the present embodiment.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 3 to 10, the present embodiment provides a GIP circuit for improving display stability, which includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a capacitor C1, a capacitor C2, and a capacitor C3. The control terminal of the transistor T1 and the control terminal of the transistor T8 are respectively connected to a gate line G (n-4), the input terminal of the transistor T1 and the input terminal of the transistor T8 are respectively connected to a turn-on voltage VGH, the output terminal of the transistor T1 is connected to the control terminal of the transistor T4, and the output terminal of the transistor T8 is connected to the control terminal of the transistor T9. The input terminal of the transistor T9 is connected to the turn-on voltage VGH, and the output terminal of the transistor T9 is connected to a line connecting the output terminal of the transistor T1 and the control terminal of the transistor T4. The control end of the transistor T2 is connected to a line on which the output end of the transistor T1 is connected to the control end of the transistor T4, the input end of the transistor T2 is connected to the control end of the transistor T3, the first plate of the capacitor C1 and the control end of the transistor T6, and the output end of the transistor T2, the output end of the transistor T3 and the output end of the transistor T6 are connected to the off-voltage VGL. The second plate of the capacitor C1 is connected to the clock signal CK. The input terminal of the transistor T3 is connected to a line where the output terminal of the transistor T1 and the control terminal of the transistor T4 are connected. The input end of the transistor T4 is connected to the clock signal CK, the output end of the transistor T4 is connected to the gate line G (n), the first plate of the capacitor C2 is connected to the control end of the transistor T4, and the second plate of the capacitor C2 is connected to a line connecting the output end of the transistor T4 and the gate line G (n). The input terminal of the transistor T6 and the input terminal of the transistor T5 are respectively connected to the gate line g (n), the control terminal of the transistor T5 is connected to the clock signal CKB, and the output terminal of the transistor T5 is connected to the off voltage VGL. The control terminal of the transistor T7 is connected to the gate line G (n +4), the input terminal of the transistor T7 is connected to the line connecting the output terminal of the transistor T1 and the control terminal of the transistor T4, and the output terminal of the transistor T7 is connected to the off-voltage VGL. The control terminal of the transistor T10 is connected to the clock signal CK, the input terminal of the transistor T10 is connected to a line where the output terminal of the transistor T8 and the control terminal of the transistor T9 are connected, and the output terminal of the transistor T10 is connected to the off-voltage VGL. The first plate of the capacitor C3 is connected with the output end of the transistor T8, and the second plate of the capacitor C3 is used for connecting external components.
The above technical solution outputs data of the gate line g (n) through the transistor T4, and controls the voltage level of the node Q2 through the transistor T8, the transistor T9 and the transistor T10. The leakage of the node Q1 can be prevented, the GIP output signal of the subsequent output stage of the GIP circuit of the stage has no abnormity, and the problem of dark fringe display of a general GIP circuit after touch control is solved. The structure solves the problem that output signals of the GIP circuit are distorted in different touch modes, provides a solution for realizing a high-definition display screen, can improve the display quality and the touch quality of the display panel, improves the impression of the display panel, and further improves the competitiveness of the display panel.
In this embodiment, a Transistor is used as a variable current switch capable of controlling an output current based on an input voltage, and the Transistor that can be used in this application is a Thin Film Transistor (TFT), a MOS Transistor (i.e., a metal-oxide-semiconductor field effect Transistor, MOSFET for short), a junction field effect Transistor, or the like. Preferably, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, and the transistor T10 are all thin film transistors. The thin film transistor is used as a switch to drive the liquid crystal pixel point, and the characteristics of high speed, high brightness and high contrast can be achieved.
In this embodiment, the input terminal of the transistor T1, the input terminal of the transistor T2, the input terminal of the transistor T3, the input terminal of the transistor T4, the input terminal of the transistor T5, the input terminal of the transistor T6, the input terminal of the transistor T7, the input terminal of the transistor T8, the input terminal of the transistor T9, and the input terminal of the transistor T10 are all drains, the output terminals of the 10 transistors are sources, and the control terminals of the 10 transistors are gates.
In this embodiment, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, the capacitor C1, and the capacitor C2 are all disposed on a display panel. In a preferred embodiment, the display panel is an in-cell display panel. The In-Cell technology is to embed the touch panel function into the Array substrate, so that the thickness of the In-Cell panel is reduced due to the fact that the thickness of the touch screen is reduced by one layer. The display panel adopting the In-Cell technology has the advantages of lighter product, lower thickness, better light transmission, reduction of the time for attaching the screen, improvement of the production efficiency and the like.
In this embodiment, the Display panel may be an LCD Display panel, where LCD is a short for Liquid Crystal Display, and chinese is a Liquid Crystal Display. The LCD display panel has advantages of small size, low power consumption, and high brightness. Or in some embodiments, the GIP circuit may be disposed on an OLED display panel, where the OLED is an Organic Light-Emitting Diode, and the chinese language is an Organic electroluminescent display or an Organic Light-Emitting semiconductor. The OLED display panel has the characteristics of lightness, thinness, high brightness, low power consumption, quick response, high definition, good flexibility, high luminous efficiency and the like, and can meet the new requirements of consumers on display technology.
It should be noted that vg (n) represents the voltage on the gate line g (n). There are a plurality of GIP circuits in the display panel, each GIP circuit is connected to one sub-pixel through a gate line G (n) to realize driving to the sub-pixel, and each GIP circuit is connected to a driving ic through a gate line G (n +4) and a gate line G (n-4) so that the driving ic drives the sub-pixel through the GIP circuit. The plurality of sub-pixels are arranged on the display panel in an array mode, and one side of each sub-pixel is provided with a GIP circuit.
Referring to fig. 3 and 4, the present embodiment provides a GIP circuit driving method for improving display stability, which is applied to the GIP circuit for improving display stability according to any one of the above embodiments, and includes: in the touch precharge stage (i.e., labeled as a1 in fig. 4), the turn-on voltage VGH is written with a high potential, the turn-off voltage VGL is written with a low potential, the clock signal CK is written with a low potential, the clock signal CKB is written with a low potential, the gate line G (n-4) is written with a high potential, the gate line G (n) is written with a low potential, and the gate line G (n +4) is written with a low potential; in the touch voltage stabilization stage (i.e., labeled as a2 in fig. 4), the on voltage VGH is written to a high potential, the off voltage VGL is written to a low potential, the clock signal CK is written to a low potential, the clock signal CKB is written to a low potential, the gate line G (n-4) is written to a low potential, the gate line G (n) is written to a low potential, and the gate line G (n +4) is written to a low potential; in the touch output stage (i.e., labeled as a3 in fig. 4), the on voltage VGH is written into a high potential, the off voltage VGL is written into a low potential, the clock signal CK is written into a high potential, the clock signal CKB is written into a low potential, the gate line G (n-4) is written into a low potential, the gate line G (n) is written into a high potential, and the gate line G (n +4) is written into a low potential; in the touch pull-down stage (i.e., labeled as a4 in fig. 4), the on voltage VGH is written with a high potential, the off voltage VGL is written with a low potential, the clock signal CK is written with a low potential, the clock signal CKB is written with a low potential, the high potential and the low potential are sequentially written with a clock signal CKB, the gate line G (n-4) is written with a low potential, the gate line G (n) is written with a low potential, and the gate line G (n +4) is written with a high potential and a low potential sequentially; in the touch pull-down maintaining stage (i.e., marked as a5 in fig. 4), the on voltage VGH is written with a high potential, the off voltage VGL is written with a low potential, the clock signal CK is sequentially and cyclically written with a high potential and a low potential, the clock signal CKB is sequentially and cyclically written with a low potential and a high potential, and the gate line G (n-4), the gate line G (n), and the gate line G (n +4) are respectively written with a low potential.
Referring to fig. 3 and 5, in the present embodiment, the method further includes a display stage step: in the display precharge stage (i.e., marked as t1 in fig. 5), the turn-on voltage VGH is written with a high potential, the turn-off voltage VGL is written with a low potential, the clock signal CK is written with a low potential, the clock signal CKB is written with a low potential, the gate line G (n-4) is written with a high potential, the gate line G (n) is written with a low potential, and the gate line G (n +4) is written with a low potential; in the display output stage (i.e., marked as t2 in fig. 5), the on voltage VGH is written with a high potential, the off voltage VGL is written with a low potential, the clock signal CK is written with a high potential, the clock signal CKB is written with a low potential, the gate line G (n-4) is written with a low potential, the gate line G (n) is written with a high potential, and the gate line G (n +4) is written with a low potential; in the pull-down display period (i.e., marked as t3 in fig. 5), the on voltage VGH is written with a high potential, the off voltage VGL is written with a low potential, the clock signal CK is written with a low potential, the clock signal CKB is written with a low potential, the high potential and the low potential are sequentially written with a low potential, the gate line G (n-4) is written with a low potential, the gate line G (n) is written with a low potential, and the gate line G (n +4) is written with a high potential and a low potential sequentially; in the pull-down sustain period (i.e., labeled as t4 in fig. 5), the turn-on voltage VGH is written with a high potential, the turn-off voltage VGL is written with a low potential, the clock signal CK is sequentially and cyclically written with a high potential and a low potential, the clock signal CKB is sequentially and cyclically written with a low potential and a high potential, and the gate line G (n-4), the gate line G (n), and the gate line G (n +4) are respectively written with a low potential.
It should be noted that, within a preset time, the display stage step and the touch stage step are sequentially cycled. The display stage step and the touch stage step are sequentially circulated. The preset time may be a time of one frame, and the display panel operates according to the display phase, the touch phase, the display phase, and the touch phase … …, so as to implement the Long H touch display mode described above. Of course, this preset time may be a half frame, two frames, ten frames, etc.
Referring to fig. 3, 4 and 6, the touch precharge phase (labeled as a1 in fig. 4) of the GIP circuit is described herein: the gate line G (n-4) and the turn-on voltage VGH are high, and the transistor T1 and the transistor T8 are turned on. VGH charges the Q1 node and the Q2 node through the transistor T1 and the transistor T8, so that the potentials at the Q1 node and the Q2 node rise to high potentials, and controls the transistor T2, the transistor T4, and the transistor T9 to be turned on. The clock signal CK and the off voltage VGL are at low potential, and the potentials of the gate line g (n) and the P node are pulled down by the transistor T2 and the transistor T4 and are maintained at low potential. It should be noted that the operation manner of the touch precharge stage (i.e., labeled as a1 in fig. 4) is the same as the operation manner of the display precharge stage (i.e., labeled as t1 in fig. 5).
Referring to fig. 3, fig. 4 and fig. 7, the touch voltage stabilizing stage (i.e., labeled as a2 in fig. 4) of the GIP circuit is described herein: the turn-on voltages VGH, the Q1 node, and the Q2 node are high, and the transistor T2, the transistor T4, and the transistor T9 are turned on. The gate line G (n-4), the gate line G (n +4), the clock signal CK, the clock signal CKB, the off voltage VGL, and the P node are low, and the transistor T1, the transistor T3, the transistor T5, the transistor T6, the transistor T7, the transistor T8, and the transistor T10 are turned off. The duration of the touch voltage stabilization phase is about 200us, that is, the high potential of the Q1 node of the GIP circuit of a certain stage needs to be kept high within 200 us. However, in the conventional GIP circuit, the transistor leaks, and further the Q1 node leaks, which causes the voltage output by the gate line g (n) in the subsequent output stage to be lower than that of the previous stage, which causes the dark line problem of the display panel at some positions, so that the display effect of the display panel is not good, and the quality of the display panel is affected. In the touch stage of the GIP circuit, the node Q2 is at a high potential, and the transistor T9 is turned on, so that the node Q1 is supplemented to a potential which is the same as the turn-on voltage VGH through the transistor T8, thereby preventing the leakage of the node Q1, enabling the GIP output signal of the subsequent output stage of the GIP circuit to be abnormal, and solving the problem of dark fringe display of the general GIP circuit after touch.
Referring to fig. 3, 4 and 8, the touch output stage (labeled as a3 in fig. 4) of the GIP circuit is described herein: the clock signal CK and Q1 nodes are high, and the transistor T2, the transistor T4, and the transistor T10 are turned on. The gate line G (n-4), the gate line G (n +4), the off voltage VGL, and the clock signal CKB are at the low voltage level, and the transistor T1, the transistor T3, the transistor T5, the transistor T6, the transistor T7, and the transistor T8 are turned off. Since the transistor T10 is turned on, the potential of the node Q2 is pulled low to a low potential by the turn-off voltage VGL through the transistor T10, so that the transistor T9 is turned off. Since the transistor T2 is turned on, the P node is pulled low to a low potential by the off voltage VGL through the transistor T2. Since the transistor T4 is turned on, the clock signal CK is at a high level, and the gate line g (n) is at a high level, and the node Q1 is raised to a level of 2H by the coupling effect of the capacitor C2, which improves the output stability of the gate line g (n). It should be noted that the operation manner of the touch output stage (i.e., labeled as a3 in fig. 4) is the same as the operation manner of the display output stage (i.e., labeled as t2 in fig. 5).
Referring to fig. 3, 4 and 9, the touch pull-down phase (labeled as a4 in fig. 4) of the GIP circuit is described herein: the gate line G (n +4), the clock signal CKB, and the turn-on voltage VGH are high, and the transistor T5 and the transistor T7 are turned on. The gate line G (n-4), the clock signal CK, and the off voltage VGL are low potential, and the transistor T1, the transistor T2, the transistor T3, the transistor T6, the transistor T8, the transistor T9, and the transistor T10 are turned off. Since the node Q1 is at a high level in the early stage, the transistor T4 is turned on, the voltage level of the gate line g (n) is pulled down to a low level by the clock signal CK and the off voltage VGL via the transistor T4 and the transistor T5, and the voltage level of the node Q1 is pulled down to a low level by the off voltage VGL via the transistor T7, the node P is still at a low level due to the coupling effect of the capacitor C1 since the clock signal CK is at a low level. It should be noted that the operation of the touch-down phase (i.e., labeled as a4 in fig. 4) is the same as the operation of the display-down phase (i.e., labeled as t3 in fig. 5).
Referring to fig. 3, 4 and 10, the touch pull-down hold phase (labeled as a5 in fig. 4) of the GIP circuit is described herein: the node P is coupled by the clock signal CK, and when the node P is at a high level, the transistor T3 and the transistor T6 are both turned on, so that the voltage level of the node Q1 and the voltage level of the gate line g (n) are pulled down to a low level by the off voltage VGL through the transistor T3 and the transistor T6, respectively, and when the clock signal CK is at a high level, the node Q2 is pulled down to a low level. It should be noted that the operation of the touch pull-down maintaining phase (i.e., labeled as a5 in fig. 4) is the same as the operation of the display pull-down maintaining phase (i.e., labeled as t4 in fig. 5).
The technical scheme solves the problem that output signals of the GIP circuit are distorted in different touch modes, provides a solution for realizing a high-definition display screen, can improve the display quality and the touch quality of the display panel, improves the impression of the display panel, and further improves the competitiveness of the display panel.
It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.
Claims (5)
1. A GIP circuit for improving display stability is characterized by comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a capacitor C1, a capacitor C2 and a capacitor C3;
a control terminal of the transistor T1 and a control terminal of the transistor T8 are respectively connected to a gate line G (n-4), an input terminal of the transistor T1 and an input terminal of the transistor T8 are respectively connected to a turn-on voltage VGH, an output terminal of the transistor T1 is connected to a control terminal of the transistor T4, and an output terminal of the transistor T8 is connected to a control terminal of the transistor T9;
the input end of the transistor T9 is connected with a starting voltage VGH, and the output end of the transistor T9 is connected to a line connecting the output end of the transistor T1 and the control end of the transistor T4;
the control end of the transistor T2 is connected to a line on which the output end of the transistor T1 is connected to the control end of the transistor T4, the input end of the transistor T2 is connected to the control end of the transistor T3, the first plate of the capacitor C1 and the control end of the transistor T6, respectively, and the output end of the transistor T2, the output end of the transistor T3 and the output end of the transistor T6 are connected to the turn-off voltage VGL, respectively;
the second plate of the capacitor C1 is connected with the clock signal CK;
the input end of the transistor T3 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4;
the input end of the transistor T4 is connected to the clock signal CK, the output end of the transistor T4 is connected to the gate line G (n), the first plate of the capacitor C2 is connected to the control end of the transistor T4, and the second plate of the capacitor C2 is connected to a line connecting the output end of the transistor T4 and the gate line G (n);
the input end of the transistor T6 and the input end of the transistor T5 are respectively connected with a gate line G (n), the control end of the transistor T5 is connected with a clock signal CKB, and the output end of the transistor T5 is connected with a closing voltage VGL;
the control end of the transistor T7 is connected to the gate line G (n +4), the input end of the transistor T7 is connected to the line connecting the output end of the transistor T1 and the control end of the transistor T4, and the output end of the transistor T7 is connected to the off-voltage VGL;
the control end of the transistor T10 is connected to the clock signal CK, the input end of the transistor T10 is connected to the line connecting the output end of the transistor T8 and the control end of the transistor T9, and the output end of the transistor T10 is connected to the off-voltage VGL;
the first plate of the capacitor C3 is connected with the output end of the transistor T8, and the second plate of the capacitor C3 is used for connecting external components.
2. The GIP circuit for improving display stability of claim 1, wherein said input terminal of the transistor T1, said input terminal of the transistor T2, said input terminal of the transistor T3, said input terminal of the transistor T4, said input terminal of the transistor T5, said input terminal of the transistor T6, said input terminal of the transistor T7, said input terminal of the transistor T8, said input terminal of the transistor T9 and said input terminal of the transistor T10 are all drains.
3. The GIP circuit for improving display stability of claim 1, wherein said transistor T1, said transistor T2, said transistor T3, said transistor T4, said transistor T5, said transistor T6, said transistor T7, said transistor T8, said transistor T9 and said transistor T10 are all thin film transistors.
4. The GIP circuit for improving display stability of claim 1, wherein said transistor T1, said transistor T2, said transistor T3, said transistor T4, said transistor T5, said transistor T6, said transistor T7, said transistor T8, said transistor T9, said transistor T10, said capacitor C1 and said capacitor C2 are all disposed on a display panel.
5. The GIP circuit for improving display stability of claim 4, wherein said display panel is an In-Cell display panel.
Priority Applications (1)
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| CN112527149A (en) * | 2020-12-14 | 2021-03-19 | 福建华佳彩有限公司 | GIP circuit for improving display stability and driving method |
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| CN112527149A (en) * | 2020-12-14 | 2021-03-19 | 福建华佳彩有限公司 | GIP circuit for improving display stability and driving method |
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