CN111696480A - OLED pixel compensation circuit and driving method - Google Patents

Abstract

An OLED pixel compensation circuit and a driving method thereof, wherein the pixel compensation circuit comprises thin film transistors T1, T2, T3, T4, T5, T6, T7, T8 and T9, the source of the T1 is connected with the source of an on-chip high voltage VGH, the source of the T7 and the source of the T6, the grid of the T1 is connected with the grids of clock signals ECK1 and T5, and the drain of the T1 is connected with the source of the T2, the grid of the T7 and one end of a capacitor CB; different from the prior art, the driving circuit capable of generating an EM compensation signal at each stage is realized, loss generated by RC delay is compensated, and therefore input signals are simplified, and the display effect is better.

Description

OLED pixel compensation circuit and driving method

Technical Field

The invention relates to the field of panel design, in particular to an OLED pixel compensation circuit and a driving method design.

Background

In a conventional commercial display, an IC is generally disposed on a short side and a GIP trace is disposed on a long side. The source trace of such commercial displays is long and the data gradually decreases as the RCdelay on the source trace increases. Therefore, as the trace distance increases, RCdelay increases, the voltage writing of the pixel electrode becomes smaller, and the image brightness decreases. Therefore, a sourceoverdrive method is provided to compensate the voltage of the pixel electrode, and the phenomenon of brightness reduction is avoided.

Disclosure of Invention

Therefore, it is desirable to provide an internal compensation circuit that solves the problem of reduced pixel voltage of the display.

To this end, we provide an OLED pixel compensation circuit, which includes thin film transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, a source of the T1 is connected to an on-chip high voltage VGH, a source of the T7, and a source of the T6, a gate of the T1 is connected to gates of clock signals ECK1 and T5, and a drain of the T1 is connected to a source of the T2, a gate of the T7, and one end of a capacitor CB; the drain of the T7 is connected with the other end of the capacitor CB, the gate of the T6 and the source of the T8, the drain of the T6 is connected with the drain of the T8 and the source of the T9, the gate of the T2 is connected with the drain of the T4, the gate of the T8, the gate of the T9 and the source of the T5, the source of the T4 is connected with a reset signal RST, the gate of the T4 is connected with the current-stage driving signal Gn, and the drain of the T2, the drain of the T5 and the drain of the T9 are connected with VGL; the drain of the T7 is also connected to the output of the compensation signal EMn.

A driving method of an OLED pixel compensation circuit is suitable for the OLED pixel compensation circuit and comprises the following steps:

the first stage, the high level of the current stage input signal, the low level of the clock signal and the reset signal;

in the second stage, the current-stage input signal keeps high level, the reset signal is high level, and the clock signal is low level;

in the third stage, the input signal of the current stage keeps high level, and the reset signal and the clock signal keep low level;

the fourth stage, the current stage input signal, the reset signal and the clock signal are at low level;

in the fifth stage, the current-stage input signal is at low level, the clock signal is at high level, and the reset signal is at high level after keeping at low level.

Different from the prior art, the driving circuit capable of generating an EM compensation signal at each stage is realized, loss generated by RCdelay is compensated, and therefore input signals are simplified, and the display effect is better.

Drawings

FIG. 1 is a schematic diagram of a compensation circuit according to an embodiment;

fig. 2 is a schematic diagram of a driving waveform according to an embodiment.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1, an OLED pixel compensation circuit includes thin film transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9, a source of the T1 is connected to an on-chip high voltage VGH, a source of the T7, and a source of the T6, a gate of the T1 is connected to gates of clock signals ECK1 and T5, and a drain of the T1 is connected to a source of the T2, a gate of the T7, and one end of a capacitor CB; the drain of the T7 is connected with the other end of the capacitor CB, the gate of the T6 and the source of the T8, the drain of the T6 is connected with the drain of the T8 and the source of the T9, the gate of the T2 is connected with the drain of the T4, the gate of the T8, the gate of the T9 and the source of the T5, the source of the T4 is connected with a reset signal RST, the gate of the T4 is connected with the current-stage driving signal Gn, and the drain of the T2, the drain of the T5 and the drain of the T9 are connected with VGL; the drain of the T7 is also connected to the output of the compensation signal EMn. Such an OLED pixel compensation circuit, when properly driven, is capable of generating one compensation signal EMn for each stage (n). The driving method of the pixel compensation circuit is as follows:

in the embodiment shown in fig. 2, the following stages are included:

first stage t 1: when the input signal of the previous stage is high, the clock signal and the reset signal are low, T4 is turned on, and EMn maintains the high level of the previous frame.

Second stage t 2: when the previous stage input signal keeps high level, the reset signal is high level, and the clock signal is low level; t4, T2, T8, and T9 are open and EMn is pulled to the low level by VGL.

Third stage t 3: when the previous stage input signal keeps high level, the reset signal and the clock signal are low level; t4 is turned on, EMn maintains the low level of the previous stage.

Fourth stage t 4: the current stage inputs signals, reset signals and clock signals to low level; all TFTs are turned off, and EMn remains at the low level.

Fifth stage t 5: when the input signal of the previous stage is at low level, the clock signal is at high level, the reset signal is at high level after keeping at low level, T1, T5, T6 and T7 are turned on, and EMn is pulled to high level by VGH.

The compensation signal EMn is pulled down by the superposition of the current-stage driving signal Gn and the reset signal RST, and is pulled up by the ECK 1. Further, when EMn is at high level, T6 is turned on, and at this time, the middle of T8 and T9 is at high level, in this case, if T8 and T9 are turned on by mistake, the level of EMn is not pulled low by VGL. Therefore, the action of T6 ensures that EMn is not pulled low at high level.

In some other embodiments, when the panel is in the first frame of the power-on at this time, EMn has no high level of the previous frame in the first period, and then the two OLED driving voltages OVDD/OVSS, i.e. the voltages of the anode and the cathode at the two ends of the OLED led, are applied later by one frame, so that the human eye does not see the non-uniformity in the initial period of the first frame.

It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.

Claims (2)

1. An OLED pixel compensation circuit is characterized by comprising thin film transistors T1, T2, T3, T4, T5, T6, T7, T8 and T9, wherein the source of T1 is connected with the source of an on-chip high voltage VGH and T7 and the source of T6, the gate of T1 is connected with the gates of clock signals ECK1 and T5, and the drain of T1 is connected with the source of T2, the gate of T7 and one end of a capacitor CB; the drain of the T7 is connected with the other end of the capacitor CB, the gate of the T6 and the source of the T8, the drain of the T6 is connected with the drain of the T8 and the source of the T9, the gate of the T2 is connected with the drain of the T4, the gate of the T8, the gate of the T9 and the source of the T5, the source of the T4 is connected with a reset signal RST, the gate of the T4 is connected with the current-stage driving signal Gn, and the drain of the T2, the drain of the T5 and the drain of the T9 are connected with VGL; the drain of the T7 is also connected to the output of the compensation signal EMn.

2. A driving method of an OLED pixel compensation circuit, applicable to the OLED pixel compensation circuit of claim 1, comprising the following stages:

the first stage, the high level of the current stage input signal, the low level of the clock signal and the reset signal;

in the second stage, the current-stage input signal keeps high level, the reset signal is high level, and the clock signal is low level;

in the third stage, the input signal of the current stage keeps high level, and the reset signal and the clock signal keep low level;

the fourth stage, the current stage input signal, the reset signal and the clock signal are at low level;

in the fifth stage, the current-stage input signal is at low level, the clock signal is at high level, and the reset signal is at high level after keeping at low level.

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