CN111584348A - Reworking method of three-layer photoetching material - Google Patents

Reworking method of three-layer photoetching material Download PDF

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CN111584348A
CN111584348A CN202010466198.8A CN202010466198A CN111584348A CN 111584348 A CN111584348 A CN 111584348A CN 202010466198 A CN202010466198 A CN 202010466198A CN 111584348 A CN111584348 A CN 111584348A
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polysilicon gate
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李中华
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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    • G03F7/427—Stripping or agents therefor using plasma means only
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    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
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Abstract

The invention discloses a reworking method of three-layer photoetching materials, which comprises the following steps: providing a semiconductor substrate with a polysilicon gate; step two, spin coating three layers of photoetching materials formed by laminating an ODL layer, an SHB layer and a PR layer; step three, checking the film layer, and if the film layer is checked to have a problem, performing the subsequent step four; step four, carrying out a rework process, comprising: step 41, cleaning with an organic solvent; step 42, carrying out first plasma gas etching by using CF4 as etching gas; and 43, carrying out second plasma gas etching by using N2H2 as etching gas. And step 44, cleaning the semiconductor substrate by adopting a single-chip cleaning process. The invention can improve the application range of the rework process, greatly improve the safety of the rework process and reduce the defect of extra introduction of the rework process.

Description

Reworking method of three-layer photoetching material
Technical Field
The present invention relates to semiconductor integrated circuit manufacturing, and more particularly to a method for reworking a three-layer photoresist.
Background
As technology advances, the feature line width size of chips becomes smaller and smaller. In order to improve the fidelity of the line width pattern, the wafer film stack during photoetching adopts multilayer material stack to sequentially transfer the pattern. The manufacturing process of the chip is very complex and has many steps, and the wafer is a wafer composed of a semiconductor substrate with a single crystal structure, such as a silicon substrate. After the manufacture of each step reaches the standard, the finally manufactured chip can reach the design function, otherwise, the chip becomes a waste product. If the abnormality of any process step can not be reworked, the abnormality can be abandoned as waste.
In the photolithography process, in order to improve the resolution of the pattern and the fidelity in the process, three layers of thin film stack structures made of different materials, i.e., three layers of photolithography materials, are used to sequentially transfer the pattern and the dimension. When the process is abnormal, the film material on the surface of the wafer can be stripped through the reworking process, and the reworked wafer is redeposited with the related film material, so that the wafer is prevented from being scrapped. The three layers of lithographic material are typically an Organic bottom Layer (ODL) Layer, a silicon-on-silicon Hard Mask (SHB) Layer, and a Photoresist (PR) Layer, respectively.
The SHB layer employs a silicon-based anti-reflective layer such as a silicon bottom anti-reflective coating (BARC).
The ODL layer is typically a Carbon coating (SOC), which is a high Carbon content polymer.
Three layers of photoetching materials are also needed in the cutting process of the polysilicon gate, and the definition of the photoetching process and the etching of the polysilicon gate are realized through the three layers of photoetching materials.
One conventional rework process includes the following steps: step 1, removing photoresist on the surface of a wafer by adopting O2 plasma gas etching; step 2, adopting CF4 plasma gas to etch and remove the silicon-based anti-reflection layer under the wafer photoresist; and 3, removing the ODL layer below the silicon-based anti-reflection layer of the wafer by adopting O2 plasma gas etching.
The existing dry etching rework process can save deposition abnormity of the silicon-based anti-reflection layer, photoresist deposition abnormity after deposition of the silicon-based anti-reflection layer, and any abnormity in the photoetching exposure process and after exposure. However, if any abnormality before the deposition of the silicon-based anti-reflection layer, such as an abnormality found after the coating of the ODL layer, is reworked by using the process, the wafer may be scrapped because:
the steps 1 and 3 are both etched by using O2 plasma gas, if the process abnormality before the silicon-based antireflection layer usually occurs when the ODL layer is coated, the ODL layer is removed in the step 1 by performing the rework process, so that the subsequent CF4 plasma gas etching in the step 2 can damage the structure on the semiconductor substrate, such as the polysilicon gate formed on the semiconductor substrate, and directly remove the polysilicon gate, thereby easily causing the wafer abnormality.
An improved rework process includes the following steps:
step 1, removing photoresist on the surface of a wafer by adopting a photoresist Reduction (RRC) process; step 2, adopting CF4 plasma gas to etch and remove the silicon-based anti-reflection layer under the wafer photoresist; and 3, removing the ODL layer below the silicon-based anti-reflection layer of the wafer by adopting O2 plasma gas etching. The improved method can eliminate the defects existing in the prior method described above, namely, after the ODL layer is coated and found to be abnormal, the RRC process of the step 1 can not generate the effect of thinning the ODL layer; the CF4 plasma etching in step 2 only partially thins the ODL layer and does not remove the ODL layer, so that the included ODL layer can protect the polysilicon gate at the bottom and prevent the CF4 plasma etching from damaging the polysilicon gate. However, this improved method has a disadvantage in that, after the ODL layer is removed in the O2 plasma gas etching of step 3, the O2 plasma gas etching is liable to cause oxidation of the exposed polysilicon gate, thereby causing a loss in the height of the polysilicon gate. For a semiconductor device with a technology node of below 28nm, the thickness, i.e., height, of the polysilicon gate is originally low, so that the polysilicon gate resistance is increased after the height of the polysilicon gate is lost, and finally the performance of the device is affected.
Disclosure of Invention
The invention aims to provide a method for reworking three-layer photoetching materials, which can improve the application range of the rework process, greatly improve the safety of the rework process and reduce the defect caused by extra rework process.
In order to solve the technical problem, the rework method of the three-layer photoetching material provided by the invention comprises the following steps:
providing a semiconductor substrate needing a photoetching process, forming a gate dielectric layer and a polysilicon gate which are sequentially overlapped on the semiconductor substrate, forming a graphical etching barrier layer on the top of the polysilicon gate, wherein the etching barrier layer covers part of the polysilicon gate, and the surface of the polysilicon gate outside the area covered by the etching barrier layer is exposed.
And secondly, spin-coating three layers of photoetching materials on the semiconductor substrate, wherein the three layers of photoetching materials are an ODL layer, an SHB layer and a PR layer which are sequentially overlapped.
Step three, inspecting the film layer after the respective forming process of the ODL layer, the SHB layer or the PR layer is finished or after the development is finished, and if the inspection has a problem, performing the subsequent step four; and if the checking result is normal, continuing to perform the subsequent corresponding photoetching process or etching process.
Step four, carrying out a rework process, which comprises the following steps:
and 41, carrying out organic solvent cleaning, wherein the organic solvent cleaning process is used for removing the PR layer and simultaneously ensuring that the PR layer does not react with the SHB layer and the ODL layer at the bottom layer of the PR layer.
And 42, carrying out first plasma gas etching, wherein the etching gas of the first plasma gas etching adopts CF4, the first plasma gas etching is used for removing the SHB layer, and meanwhile, the ODL layer is ensured to keep partial thickness when the ODL layer is separately processed by adopting the first plasma gas etching.
And 43, performing second plasma gas etching, wherein the etching gas of the second plasma gas etching is N2H2, and the second plasma gas etching is used for removing the ODL layer, and simultaneously ensuring that the exposed polysilicon gate is not subjected to oxidation reaction so as to reduce the height loss of the polysilicon gate.
And step 44, cleaning the semiconductor substrate by adopting a single-chip cleaning process.
In a further improvement, the ODL layer employs SOC.
In a further improvement, the SHB layer employs a silicon BARC.
In a further improvement, the organic solvent cleaning adopts a photoresist reduction process.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, a field oxide layer is further formed on the semiconductor substrate, and an active region is defined by the field oxide layer.
In a further improvement, the etching barrier layer comprises a first silicon nitride layer and a second silicon dioxide layer which are sequentially overlapped.
In a further improvement, the first silicon nitride layer has a thickness of
Figure BDA0002512735500000031
The thickness of the second silicon dioxide layer is
Figure BDA0002512735500000032
The further improvement is that the gate dielectric layer is made of silicon dioxide or a high dielectric constant material.
In a further improvement, the process technology node of the semiconductor device corresponding to the polysilicon gate is below 28 nm.
In a further improvement, the height of the polysilicon gate is
Figure BDA0002512735500000033
In a further improvement, the photolithography process is used to define the region of the polysilicon gate to be cut.
The further improvement is that if the inspection result is normal after the development in the third step, the photoetching process is finished, and the subsequent etching process is carried out.
The further improvement is that the etching process takes the developed PR layer as a mask, and the SHB layer, the ODL layer and the polysilicon gate layer are sequentially etched to realize the cutting of the polysilicon gate.
In a further improvement, in step 44, the liquid used in the single-wafer cleaning process includes: a mixture H of sulfur peroxide with a ratio of 6: 1-4: 1 and a temperature of 110-140 DEG C2SO4:H2O2Solution or ammonia peroxide mixture NH with the mixture ratio of 1:1.5:50 and the temperature of 30-70 DEG C4OH:H2O2:H2And (4) O solution.
The invention has specially set the rework process of the three-layer photoetching material on the semiconductor substrate with the polysilicon gate formed on the surface, mainly adopts one-time organic solvent cleaning, plasma gas etching with two etching gases respectively CF4 and N2H2 and one-time single-chip cleaning process, the rework process can be performed after the three-layer photoetching material is formed, and can also be suitable for the rework after one layer or two layers of photoetching material of the three-layer photoetching material are formed, especially, when the rework is needed after the bottom layer ODL layer is formed, the organic solvent cleaning process set for the PR layer removing process and the first-time plasma gas etching which uses CF4 as etching gas and is set for the removal of the SHB layer can not cause adverse effect on the ODL layer, the ODL layer can have thickness retention, the organic solvent cleaning process and the first-time plasma gas etching can not cause adverse effect on the structure of the junction on the semiconductor substrate at the bottom of the ODL layer under the protection of the retained ODL layer, therefore, the rework process is suitable for the situation when any step in the photoetching process has problems, for example, the rework can be well realized no matter in the processes of the ODL layer, the SHB layer and the PR layer, or after three layers of photoetching materials are formed and developed, so that the application range of the rework process can be enlarged, the safety of the rework process is greatly improved, and the defect caused by extra introduction of the rework process can be reduced.
In addition, when the semiconductor substrate is provided with the polysilicon gate, N2H2 is used as etching gas during the second plasma gas etching, so that the second plasma gas is prevented from generating oxidation on the polysilicon gate while the ODL layer is well removed, and the polysilicon gate is prevented from generating height loss after being oxidized, so that the polysilicon gate can be prevented from height loss, the polysilicon gate resistance is prevented from being increased due to height loss, and the performance of the device can be improved; with the continuous reduction of the technology nodes, for example, the technology nodes are reduced to be below 28nm, the beneficial effects brought by the invention on the maintenance of the height of the polysilicon gate are more prominent.
In addition, the single-chip cleaning process is adopted at the last time, and is different from the multi-chip cleaning, namely batch operation cleaning in the prior art, the single-chip cleaning process can avoid the problem of overall pollution of the wafers of the semiconductor substrate introduced by batch operation cleaning, the safety of the rework process can be further improved, and the defect additionally introduced by the rework process can be reduced.
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The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a flow chart of a method for rework of a three-layer lithographic material according to an embodiment of the invention;
FIGS. 2A-2D are schematic diagrams of device structures in sub-steps of a rework method of embodiments of the invention during processing of a first scenario;
FIGS. 3A-3D are schematic diagrams of device structures in sub-steps of a rework method of embodiments of the invention while processing a second scenario;
fig. 4A-4D are schematic diagrams of device structures in various sub-steps of a rework method of the embodiment of the invention when processing the third scenario.
Detailed Description
FIG. 1 is a flow chart of a method for reworking a three-layer photoresist according to an embodiment of the present invention; fig. 2A to 2D are schematic diagrams of device structures in the sub-steps of the rework method according to the embodiment of the invention when processing the first situation; fig. 3A to 3D are schematic diagrams of device structures in the sub-steps of the rework method according to the embodiment of the invention when processing the second situation; fig. 4A to 4D are schematic diagrams of device structures in respective sub-steps of the rework method according to the embodiment of the invention when processing the third situation; the reworking method of the three-layer photoetching material comprises the following steps:
step one, as shown in fig. 2A, providing a semiconductor substrate 1 which needs to be subjected to a photolithography process, forming a gate dielectric layer 5 and a polysilicon gate 6 which are sequentially overlapped on the semiconductor substrate 1, forming a patterned etching barrier layer 7 on the top of the polysilicon gate 6, wherein the etching barrier layer 7 covers a part of the polysilicon gate 6, and the surface of the polysilicon gate 6 outside the area covered by the etching barrier layer 7 is exposed.
In the embodiment of the present invention, the semiconductor substrate 1 includes a silicon substrate. A field oxide layer 4 is also formed on the semiconductor substrate 1, and an active region is defined by the field oxide layer 4.
A well region is further formed on the semiconductor substrate 1, and comprises a P well 2 and an N well 3. The semiconductor device includes PMOS and NMOS, the NMOS is formed in the active area where P trap 2 is formed; the PMOS is formed in the active region where the N-well 3 is formed.
The etching barrier layer 7 includes a first silicon nitride layer 7a and a second silicon oxide layer 7b which are sequentially stacked.
Preferably, the thickness of the first silicon nitride layer 7a is
Figure BDA0002512735500000051
The second silicon oxide layer 7b has a thickness of
Figure BDA0002512735500000052
The gate dielectric layer 5 is made of silicon dioxide or a high dielectric constant material.
And the process technology node of the semiconductor device corresponding to the polysilicon gate 6 is below 28 nm. The height of the polysilicon gate 6 is
Figure BDA0002512735500000053
The photolithography process is used to define the region of the polysilicon gate 6 that needs to be cut.
Step two, as shown in fig. 2A, three layers of lithography materials are spin-coated on the semiconductor substrate 1, wherein the three layers of lithography materials are an ODL layer 8, an SHB layer 9 and a PR layer 10 which are sequentially stacked.
In the embodiment of the present invention, the ODL layer 8 uses an SOC.
The SHB layer 9 employs a silicon BARC.
And step three, inspecting the film layer after the formation process of the ODL layer 8, the SHB layer 9 or the PR layer 10 is finished or after the development is finished, and if the inspection has a problem, performing the subsequent step four.
In the embodiment of the present invention, the case where the film inspection has a problem after the formation of the PR layer 10 including the development is completed corresponds to the first case shown in fig. 2A to 2D.
When a problem occurs in the film layer inspection after the SHB layer 9 formation process is completed, it corresponds to the second case shown in fig. 3A to 3D.
When a problem occurs in film layer inspection after the completion of the ODL layer 8 forming process, it corresponds to the third case shown in fig. 4A to 4D.
And if the checking result is normal, continuing to perform the subsequent corresponding photoetching process or etching process.
Step four, carrying out a rework process, which comprises the following steps:
and 41, carrying out organic solvent cleaning, wherein the organic solvent cleaning process is used for removing the PR layer 10 and simultaneously ensuring that the PR layer does not react with the SHB layer 9 and the ODL layer 8 on the bottom layer of the PR layer 10.
In the embodiment of the invention, the cleaning of the organic solvent adopts a photoresist decrement process.
For the first case: as shown in fig. 2B, after step 41 is completed, the PR layer 10 is removed.
For the second case: as shown in fig. 3A, since the PR layer 10 is not coated since a problem is detected after the SHB layer 9 is formed, the PR layer 10 does not need to be cleaned in step 41. As shown in fig. 3B, since the organic solvent cleaning does not react to the SHB layer 9, the SHB layer 9 remains, and the structures shown in fig. 3A and 3B before and after the organic solvent cleaning are the same.
For the third cleaning: as shown in fig. 4A, since the coating of the SHB layer 9 and the PR layer 10 is not performed since a problem is checked after the ODL layer 8 is formed, the PR layer 10 requiring cleaning is not present in step 41. As shown in fig. 4B, since the organic solvent cleaning does not react to the ODL layer 8, the ODL layer 8 remains, and the structures shown in fig. 4A and 4B before and after the organic solvent cleaning are identical.
And 42, carrying out first plasma gas etching, wherein the etching gas of the first plasma gas etching adopts CF4, the first plasma gas etching is used for removing the SHB layer 9, and meanwhile, the ODL layer 8 can keep partial thickness when the ODL layer 8 is separately processed by adopting the first plasma gas etching.
For the first case: after step 42 is completed, the SHB layer 9 is removed, as shown in fig. 2C.
For the second case: after step 42 is completed, the SHB layer 9 is removed, as shown in fig. 3C.
For the third cleaning: as shown in fig. 4C, since the SHB layer 9 is not present, there is no case of removing the SHB layer 9; however, the first plasma gas etching may partially etch the ODL layer 8, and the ODL layer 8 in the region shown by the dashed box 101 is removed; however, since the etching rate of the ODL layer 8 by the first plasma gas etching is small, most of the thickness of the ODL layer 8 is maintained. As can be seen from a comparison of fig. 4A to 4C, the organic solvent cleaning of step 41 and the first plasma gas etching of step 42 do not remove the ODL layer 8, so that the structure at the bottom of the ODL layer 8 is not adversely affected.
And 43, performing second plasma gas etching, wherein the etching gas of the second plasma gas etching is N2H2, and the second plasma gas etching is used for removing the ODL layer 8, and simultaneously ensuring that the exposed polysilicon gate 6 is not subjected to oxidation reaction so as to reduce the height loss of the polysilicon gate 6.
For the first case: after completion of step 43, the ODL layer 8 is removed, as shown in fig. 2D.
For the second case: after completion of step 43, the ODL layer 8 is removed, as shown in fig. 3D.
For the third cleaning: after completion of step 43, the ODL layer 8 is removed, as shown in fig. 4D.
And step 44, cleaning the semiconductor substrate 1 by adopting a single-chip cleaning process.
In an embodiment of the present invention, in step 44, the liquid medicine used in the single wafer cleaning process includes: a mixture H of sulfur peroxide with a ratio of 6: 1-4: 1 and a temperature of 110-140 DEG C2SO4:H2O2Solution or ammonia peroxide mixture NH with the mixture ratio of 1:1.5:50 and the temperature of 30-70 DEG C4OH:H2O2:H2And (4) O solution.
In the embodiment of the invention, if the inspection result is normal after the development in the third step, the photoetching process is finished, and the subsequent etching process is carried out.
In the etching process, the developed PR layer 10 is used as a mask, and the SHB layer 9, the ODL layer 8 and the polysilicon gate 6 layer are sequentially etched to realize cutting of the polysilicon gate 6.
The embodiment of the invention particularly sets the rework process of the three layers of photoetching materials on the semiconductor substrate 1 with the polysilicon gate 6 formed on the surface, mainly adopts one-time organic solvent cleaning, two-time plasma gas etching with respectively CF4 and N2H2 etching gases and one-time single-chip cleaning process, the rework process can be performed after the three layers of photoetching materials are formed, and can also be suitable for the rework after one layer or two layers of photoetching materials of the three layers of photoetching materials are formed, particularly, the rework time is needed after the bottom layer ODL 8 is formed, the organic solvent cleaning process set for the PR layer 10 removing process and the first-time plasma gas etching which uses CF4 as etching gases and is set for removing the SHB layer 9 do not cause adverse effects on the ODL layer 8, the ODL layer 8 has thickness retention, and the organic solvent cleaning process and the first-time plasma gas etching do not cause adverse effects on the semiconductor substrate 1 at the bottom of the ODL layer 8 under the protection of the reserved ODL layer 8 The structure of the invention causes adverse effects, so the rework process of the embodiment of the invention is suitable for situations when problems occur in any step of the photolithography process, for example, no matter in the process of the ODL layer 8, the SHB layer 9 and the PR layer 10, or after three layers of photolithography materials are formed and after development, the rework can be well realized by the embodiment of the invention, so the embodiment of the invention can improve the application range of the rework process, greatly improve the safety of the rework process, and also can reduce the defects additionally introduced by the rework process.
In addition, when the semiconductor substrate 1 is provided with the polysilicon gate 6, the embodiment of the invention adopts N2H2 as etching gas during the second plasma gas etching, so that the ODL layer 8 can be well removed, meanwhile, the second plasma gas is prevented from generating oxidation action on the polysilicon gate 6, and the polysilicon gate 6 is prevented from generating height loss after being oxidized, so that the embodiment of the invention can prevent the height loss of the polysilicon gate 6, further prevent the increase of the resistance of the polysilicon gate 6 caused by the height loss, and improve the performance of the device; with the continuous reduction of the technology nodes, for example, the technology nodes are reduced to below 28nm, the beneficial effects of the embodiment of the present invention on the retention of the height of the polysilicon gate 6 are more prominent.
In addition, the single-chip cleaning process adopted in the last time in the embodiment of the invention is different from the multi-chip cleaning, namely batch operation cleaning in the prior art, so that the single-chip cleaning process can avoid the problem of overall pollution of the wafers of the semiconductor substrate 1 introduced by batch operation cleaning, the safety of the rework process can be further improved, and the defect of additional introduction of the rework process can be reduced.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A rework method of three-layer photoetching materials is characterized by comprising the following steps:
providing a semiconductor substrate needing a photoetching process, forming a gate dielectric layer and a polysilicon gate which are sequentially overlapped on the semiconductor substrate, forming a graphical etching barrier layer on the top of the polysilicon gate, wherein the etching barrier layer covers part of the polysilicon gate, and the surface of the polysilicon gate outside the area covered by the etching barrier layer is exposed;
spin-coating three layers of photoetching materials on the semiconductor substrate, wherein the three layers of photoetching materials are an ODL layer, an SHB layer and a PR layer which are sequentially overlapped;
step three, inspecting the film layer after the respective forming process of the ODL layer, the SHB layer or the PR layer is finished or after the development is finished, and if the inspection has a problem, performing the subsequent step four; if the checking result is normal, continuing to perform the subsequent corresponding photoetching process or etching process;
step four, carrying out a rework process, which comprises the following steps:
step 41, carrying out organic solvent cleaning, wherein the organic solvent cleaning process is used for removing the PR layer and simultaneously ensuring that the PR layer does not react with the SHB layer and the ODL layer at the bottom layer of the PR layer;
42, carrying out first plasma gas etching, wherein the etching gas of the first plasma gas etching adopts CF4, the first plasma gas etching is used for removing the SHB layer, and meanwhile, the ODL layer is ensured to keep partial thickness when the ODL layer is separately processed by adopting the first plasma gas etching;
43, performing second plasma gas etching, wherein etching gas of the second plasma gas etching is N2H2, the second plasma gas etching is used for removing the ODL layer, and meanwhile, oxidation reaction on the exposed polysilicon gate is avoided, so that the height loss of the polysilicon gate is reduced;
and step 44, cleaning the semiconductor substrate by adopting a single-chip cleaning process.
2. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: the ODL layer adopts SOC.
3. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: the SHB layer adopts silicon BARC.
4. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: the organic solvent cleaning adopts a photoresist decrement process.
5. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: the semiconductor substrate includes a silicon substrate.
6. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: and forming a field oxide layer on the semiconductor substrate, wherein the field oxide layer defines an active region.
7. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: the etching barrier layer comprises a first silicon nitride layer and a second silicon dioxide layer which are sequentially overlapped.
8. A method of reworking a three layer lithographic material as claimed in claim 7, wherein: the first silicon nitride layer has a thickness of
Figure FDA0002512735490000021
The thickness of the second silicon dioxide layer is
Figure FDA0002512735490000022
9. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: the gate dielectric layer is made of silicon dioxide or a high-dielectric-constant material.
10. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: and the process technology node of the semiconductor device corresponding to the polysilicon gate is below 28 nm.
11. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: the height of the polysilicon gate is
Figure FDA0002512735490000023
12. A method of reworking a three layer lithographic material as claimed in claim 11, wherein: and the photoetching process is used for defining the region of the polysilicon gate to be cut.
13. A method of reworking a three layer lithographic material as claimed in claim 12, wherein: and if the inspection result is normal after the development in the third step, finishing the photoetching process and carrying out the subsequent etching process.
14. A method of reworking a three layer lithographic material as claimed in claim 12, wherein: and the etching process takes the developed PR layer as a mask, and sequentially etches the SHB layer, the ODL layer and the polysilicon gate layer to realize the cutting of the polysilicon gate.
15. A method of reworking a three layer lithographic material as claimed in claim 1, wherein: in step 44, the liquid medicine used in the single-chip cleaning process includes: a mixture H of sulfur peroxide with a ratio of 6: 1-4: 1 and a temperature of 110-140 DEG C2SO4:H2O2Solution or ammonia peroxide mixture NH with the mixture ratio of 1:1.5:50 and the temperature of 30-70 DEG C4OH:H2O2:H2And (4) O solution.
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