CN104914744A - Online coding synchronization control system used for coding imaging and control method - Google Patents
Online coding synchronization control system used for coding imaging and control method Download PDFInfo
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Abstract
The invention discloses an online coding synchronization control system used for coding imaging and a method. The synchronization control system is formed by an upper computer, a microcontroller and a field programmable gate array. In the synchronization control system, through serial port communication, the upper computer sends a sequential control parameter to the microcontroller. The microcontroller decodes and transcodes the acquired sequential parameter. Then the microcontroller controls the field programmable gate array FPGA to realize multipath coded TTL signal output according to the sequential parameter acquired through decoding. Finally, the multipath coded TTL signal is used to trigger a corresponding synchronization work device so as to complete synchronization control respectively. A pulse width of the multipath coded TTL signal and a relative time delay between different signals can carry out on-line coding. Characteristics of on-line real-time configuration, good expansibility and the like are possessed. The system and the method can be applied to the synchronization control fields of gated imaging, fluorescence lifetime imaging and the like.
Description
Technical field
The present invention relates to and can be encoded into picture synchro control field, particularly relate to a kind of online codified synchronous control system for coded imaging and control method.
Background technology
Online codified synchronous control technique can be the codified such as technique of laser range gated imaging, fluorescence lifetime imaging technical field of imaging and provides synchronous control technique.Online codified synchro control completes synchronous control technique by the online multichannel TTL signal triggering synchronous device work of can encoding online that produces, and the relative time delay between multichannel TTL signal and pulsewidth can carry out freely encoding online.On-line synchronous control technology can configure when making user carry out can be encoded into picture online in real time, adds the operability of user.Codified performance then expands the depth of field of the single-frame images of imaging.Therefore online codified synchro control makes the convenient operation and add the Depth of field of single-frame images more of the synchro control in imaging technique simultaneously, has important Research Significance.
The importance of online codified synchronous control technique is described for codified technique of laser range gated super-resolution imaging technology.Traditional super-resolution technique of laser range gated imaging technology synchro control is that TTL sequence signal that generation three tunnel has relative time delay and a distinct pulse widths goes to trigger CCD, storbing gate and laser respectively and makes it complete gated imaging, namely, when in a two field picture, CCD is high level, laser and storbing gate gate-width are fixing and relative time delay between the two is also fixing.Relative time delay between laser and storbing gate is fixed value, and therefore the depth of field of an image is fixing.For completing super-resolution three-dimensional imaging, needing the photo having a different delayed time value to multiple to carry out the inverting of overlay region, greatly reducing efficiency and the real-time of detection like this.Codified technique of laser range gated super-resolution imaging technology triggers TTL sequence signal by generation three tunnel equally, and trigger pulse laser, storbing gate and CCD realize gated imaging respectively.But three tunnels are triggered between TTL sequence signal and be there is specific matching relationship, three tunnels are triggered TTL sequence signal and are carried out work according to certain coded system trigger pulse laser instrument, storbing gate and CCD.In the art, in the pictures that the coding work of laser instrument, storbing gate and CCD makes, there is multiple time delay numerical value thus greatly increase the depth of field of single-frame images, because this increasing efficiency and the real-time of detection.
At present in technique of laser range gated imaging technical field, the device for synchronous control technique mainly contains based on digital delay pulse producer, based on CPLD (CPLD), based on programmable delay chip with based on field programmable gate array (FPGA).Digital delay pulse producer control accuracy is done, but it is bulky, load heavy, system complex, all parameters all manually push-botton operation, therefore the dirigibility of device and portability poor, be unfavorable for that gated imaging system is practical.The advantages such as CPLD has programmable functions because of it, and volume is little, reference time delay is large, but device combination logic resource is abundant, sequential logic resource is relatively less, there is generation pulse work and there is time delay greatly, the problems such as control accuracy is not high.Programmable delay chip has the advantages such as able to programme, delay precision is high, and reference time delay is larger, but the employing of programmable delay chip is analogue technique, does not have digit chip stability high.FPGA volume is little, clear logic, and containing phaselocked loop, reference time delay is large, and therefore very applicable logical design and temporal constraint are the ideal component of gated imaging synchro control.
Fluorescence lifetime imaging technology passes through detection autofluorescence and external source fluorescence lifetime imaging, for pathological tissues resolution, tissue physiology's activity detection provide imaging means.Its main implementation method comprises frequency domain method and time domain method two kinds.Wherein time domain method mutually such as frequency domain method have higher temporal resolution, it is fast and can be used for the advantages such as wide field imaging that gate control method has image taking speed.Gate control method in time domain method completes imaging by the synchronous working controlled between laser and imaging lens, time delay between laser emission time and image device work is relevant with fluorescence lifetime, multiple images respectively with different delayed time of usual employing carry out the life-span of inverting fluorescence, thus real-time and imaging efficiency lower.Online codified synchronous control technique can increase its imaging efficiency equally, makes single-frame images to have multiple time delay, and the inverting that therefore single-frame images can complete fluorescence lifetime makes fluorescence lifetime inverting work greatly reduce.Gate fluorescence lifetime imaging system is commonly used synchronous control technique and is mainly contained light delay technique and electric delay technique two kinds, it is higher and have codified performance that electricity delay technique device compares the dirigibility of light delay technique, and conventional electric delay device is based on digital delay pulse producer with based on field programmable gate array (FPGA).Digital delay pulse producer control accuracy is done, but its all parameter all manually push-botton operation, therefore the dirigibility of device and portability poor, be unfavorable for that fluorescence lifetime imaging system is practical, FPGA is lower compared to digital delay pulse producer delay precision, but its volume is little, clear logic, containing phaselocked loop, therefore very applicable logical design and temporal constraint are the ideal component of fluorescence lifetime imaging synchro control.
It is large that field programmable gate array FPGA has reference time delay, and logical resource enriches, very applicable logical design and temporal constraint, is thus widely used in the imaging of super-resolution laser synchronization and fluorescence lifetime imaging technical equivalents step control system.The current clock control precision based on the sequential control system of FPGA is at nanosecond order, on the pulsewidth precision that patent both domestic and external concentrates on synchro control TTL signal mostly and delay precision, as patent CN103368543A and CN201410837006.4 achieves the generation of the synchronous TTL signal of ps level pulsewidth and the time delay of ns level under the prerequisite using FPGA as synchro control chip, the synchronisation control means not for codified imaging technique occurs.The present invention proposes a kind of method using FPGA and microcontroller implementation online codified multichannel TTL signal to produce, this technology provides the support of synchronous sequence control technology for codified super-resolution range-gated imaging technique and fluorescence lifetime imaging technology, therefore has great importance.
Summary of the invention
In order to problem described in technical solution background, the present invention proposes a kind of online codified synchronous control technique.This invention realizes multichannel online codified TTL signal by microcontroller and programming logic gate array FPGA and exports.Relative time delay between multichannel TTL signal and pulsewidth all can be encoded online, thus need the field of synchro control to provide online codified activation schedule signal for codified super-resolution technique of laser range gated imaging, fluorescence lifetime imaging etc., the real-time of synchro control is improved, simple to operate, the integrated level of synchronous control system is higher.
The invention provides a kind of online codified synchronous control system for coded imaging and control method, the method comprises: host computer sends coding sequential control parameter by serial communication to microcontroller, and microcontroller is decoded to the time sequence parameter obtained, decoding; Then the time sequence parameter that microcontroller obtains according to decoding controls field programmable gate array FPGA and realizes the output of codified TTL signal by hardware circuit multichannel, and last multichannel codified TTL signal is used for triggering corresponding device work to complete synchro control respectively.
In such scheme, synchronous control system is made up of host computer, microcontroller and on-site programmable gate array FPGA;
In such scheme, refer to each time sequence parameter that can configure each road signal in real time online;
In such scheme, N be not less than 2 natural number, user can freely arrange N value according to demand.
In such scheme, the sequential control parameter that host computer sends at alignment microcontroller comprises: the frequency of N road codified signal, relative time delay, pulsewidth and coded system information.
In such scheme, the codified performance of the online codified signal in N road is embodied in the relative time delay between the signal of N road and all can be configured in accordance with freely encoding of user's design with the pulsewidth of each signal.
In such scheme, it is characterized in that the accuracy requirement of the online codified signal in N road can be reached by internal hardware circuit in design programming logic gate array FPGA.
In such scheme, the circuit module that programming logic gate array FPGA realizes comprises frequency management module, pulse-width controlled module, time delay administration module and other logical devices composition.Frequency management module completes the frequency division of clock signal and process of frequency multiplication to reach the clock signal of the precision of desired signal, pulsewidth module completes and realizes the controlled TTL signal of N road pulsewidth to the counting of clock signal, time delay administration module realizes introducing at the TTL signal that N road pulsewidth is controlled counting clock signal, and the pulsewidth and the time delay that finally reach N road TTL signal all can be configured.
In such scheme, N road online codified signal exports at same a slice programmable gate device FPGA chip.
In such scheme, N road codified signal is used for triggering the codified synchro control realizing the device of synchro control in various synchro control process respectively.
As can be seen from technique scheme, the present invention has following beneficial effect:
1. utilize the present invention, can be implemented in line codified synchro control, the pulsewidth of each road TTL trigger pip and time delay all adjustable and there is encoding, so, the present invention can be used for the synchro control of the coded imaging such as Range-gated Imager, fluorescence lifetime imaging technical field, especially needs the synchro control changing the time domain parameter such as multiple time delay and pulsewidth online.
2. utilize the present invention, because the microcontroller and field programmable gate array FPGA that adopt synchro control are programming device, so the synchronisation control means in this invention has good expansibility, the accuracy requirement of the online codified signal in N road can be able to be reached by design such as modules inner structure in Fig. 1.
3. utilize the present invention, because time sequence parameter can be sent by host computer, slave computer produces online codified clock signal by means of only microcontroller and field programmable gate array FPGA, so the present invention can make the convenient operation of synchro control and the control in the multiple field of the coded imaging such as Range-gated Imager, fluorescence lifetime imaging technical field, make synchronous control system integrated level higher.
Accompanying drawing explanation
For further illustrating technology contents of the present invention, be described in detail as follows below in conjunction with embodiment and accompanying drawing, wherein:
Fig. 1 is a kind of system composition diagram of the online codified synchronous control system for coded imaging;
Fig. 2 is a kind of online codified synchronisation control means schematic flow sheet for coded imaging;
Fig. 3 is a kind of sequential produced for the online codified synchronisation control means of coded imaging;
Fig. 4 is the synchro control time diagram in codified technique of laser range gated super-resolution imaging technology;
Fig. 5 is the synchro control sequential implementation method schematic diagram in codified technique of laser range gated super-resolution imaging technology;
Fig. 6 is the synchro control sequential implementation method process flow diagram in codified technique of laser range gated super-resolution imaging technology;
Fig. 7 is that in the synchro control in codified technique of laser range gated super-resolution imaging technology, time sequence parameter is that encoding time delay array τ [3]={ 10,15,20}, storbing gate triggers TTL signal gate-width t
g=[10,15,20] ns, laser triggering TTL signal gate-width t
l=15ns, laser triggering TTL signal frequency f
laser=10000Hz, CCD trigger TTL signal frequency f
fPS=50Hz and CCD triggers the time diagram of TTL signal dutyfactor Duty=50%;
Description of reference numerals in accompanying drawing 1,5:
1, host computer, 2, serial communication, 3, microcontroller, 4, processing unit, 5, communication unit, 6, FPGA, 7, communication unit, 8, frequency management module, 9, time delay administration module, 10, time delay generation unit, 11, pulse-width controlled module, 12, pulsewidth generation unit, 13, output signal, 14, times frequency module, 15, frequency division module, 16, or door, 17, impact damper, 18, laser triggering TTL sequence signal, 19, storbing gate triggers TTL sequence signal, 20, CCD triggers TTL sequence signal, 21, laser selects out gate, 22, storbing gate selects out gate.
Embodiment
Refer to shown in Fig. 1, the invention provides a kind of online codified synchronous control system for coded imaging, comprising: host computer 1, microcontroller 2 and programming logic gate array FPGA 6.By passing through programming realization frequency management module 8, time delay administration module 9, pulse-width controlled module 12 in programming realization processing unit 4 and communication unit 5, FPGA in microcontroller.Wherein, time delay administration module 9 is made up of multiple time delay generation unit 10, and pulse-width controlled module 11 is made up of pulsewidth generation unit 12.
Refer to Fig. 1, Fig. 2, Fig. 3, the present invention also provides a kind of implementation method of the online codified synchronous control system for coded imaging, has following steps:
Step 1: host computer 1 sends the sequential control parameter encoded at alignment microcontroller 3 by serial communication 2, this time sequence parameter comprises the frequency of N road codified signal, relative time delay, pulsewidth and coded system information.
Step 2: the time sequence parameter being sent to microcontroller in microcontroller 3 in processing unit 4 pairs of steps 1 carries out decoding and process.
Step 3: in microcontroller, communication unit 5 carries out communicating with communication unit in programmable gate device FPGA 67 and to decoding in the communication unit forwarding step 2 in FPGA and the time sequence parameter handled well;
Step 4:FPGA communication unit 7 completes and the communicating of pulse-width controlled module 11, and to time sequence parameter in frequency management module 8, time delay administration module 9 and pulse-width controlled module 11 write step 3.
Step 5: the frequency information of the n-signal that frequency management module 9 writes according to FPGA communication unit 7 in step 4 produces the clock signal that N road has different frequency and phase place; N be not less than 2 natural number, user can freely arrange N value according to demand; The precision of the online codified signal in N road can design according to user's actual requirement.
Step 6: the delayed data that time delay administration module 9 writes according to FPGA communication unit 7 in step 4 carries out to the clock signal that N road has different frequency and phase place the signal that delay process generation N road has different frequency and relative time delay;
Step 7: pulse-width controlled module 11 is carried out pulsewidth according to the pulse width information that FPGA communication unit 7 in step 4 writes to the signal that N road in step 6 has different frequency and a relative time delay and widened;
Step 8: export N road and there is the controlled signal 13 of the pulsewidth of relative time delay.
Above-mentioned steps 3 step 8 all realizes on same fpga chip, when this fpga chip exports, the time delay of N road signal and pulsewidth have coding efficiency, not needing the trigger pip of carrying out the configuration codified of encoding can be real-time again through other device.
In above-mentioned steps 5, the precision of the online codified signal in N road can be reached by design such as modules inner structure in Fig. 1.
The codified performance of the online codified signal in N road produced in above-mentioned steps 8 is embodied in the relative time delay between the signal of N road and all can produces in accordance with the coding of user's design with the pulsewidth of each signal, the codified signal on N road is used for triggering the codified synchro control realizing the device of synchro control in various synchro control process respectively, as shown in Figure 3.
Describe at this open constructive embodiment of the present invention and method.Scrutable is be not intended to limit the present invention in specific disclosed embodiment, but the present invention can by using further feature, and element approach and embodiment are implemented.Similar components in different embodiment can indicate similar number usually.
The application of above-mentioned a kind of online codified synchronous control system for coded imaging is described for the synchro control in codified technique of laser range gated super-resolution imaging technology below.
In codified technique of laser range gated super-resolution imaging technology, its synchro control needs the triggering TTL sequence signal on three tunnels, and trigger pulse laser, storbing gate and CCD realize gated imaging respectively; Three tunnels are triggered between TTL sequence and be there is specific matching relationship, and TTL sequence is triggered according to certain coded system work in three tunnels.Its synchro control time diagram is as Fig. 4.
Can be obtained by Fig. 4, in when CCD triggers TTL signal high level (a corresponding two field picture), the storbing gate triggering TTL signal of each laser triggering TTL signal and its correspondence forms a pulse pair, the relative time delay τ of two pulses that each pulse is internal
mcan be arranged by coding rule with storbing gate pulse gate-width.τ
mform 1 × M and tie up time delay array τ [M], the different pulse of the time delay realized in the two field picture that wherein M designs for coding rule is to number.Each pulse that time delay is different in a two field picture, also can according to the pulse formed with time delay array to organizing integrally circulation T time to can alone cycle T time, T and laser triggering TTL signal frequency f
laser, CCD triggers TTL signal frequency f
fPS, CCD dutycycle Duty is relevant with time delay array size M:
Wherein [] is round the evaluation in bracket.
Microcontroller 3 and FPGA6 laser triggering TTL signal and storbing gate in a two field picture trigger TTL signal according to the pulse formed with time delay array to organizing the idiographic flow of work of integrally circulation T time as Fig. 5, and idiographic flow is described as follows:
1. microcontroller 3 program initialization, needs the modules that uses and unit, comprises serial communication modular 2, processing unit 4 and communication unit 5 in configurator;
2. host computer 1 sends the parameter of passing through coding to microcontroller 3 by serial ports 2, comprises the triggering TTL signal frequency f of CCD
fPS, the triggering TTL signal dutyfactor Duty of CCD, laser triggering TTL signal frequency f
laser, laser triggering TTL signal pulsewidth t
l, storbing gate triggers TTL signal gate-width t
g, different in time delay array τ [M], time delay array size M and each frame pulse to cycle index T, and triggers TTL signal frame-frequency f according to CCD
fPStrigger TTL signal dutyfactor Duty with CCD and calculate CCD triggering TTL signal pulsewidth t
cCD
(2)
3. microcontroller 3 receives and from the data message of host computer 1, and writes CCD to FPGA communication unit 7 and trigger TTL signal frequency f
fPS, CCD triggers TTL signal pulsewidth t
cCD, laser triggering TTL signal frequency f
laser, laser triggering TTL signal pulsewidth t
ltTL signal gate-width t is triggered with storbing gate
g;
4.FPGA produces CCD and triggers TTL signal and laser triggering TTL signal 18;
5. the laser triggering TTL signal without logical AND gate 16 is passed through FPGA communication unit 7 to microcontroller 3 laser return pulse information, this return message is as the external trigger look-at-me of microcontroller 3.After laser pulse triggered interrupts, the number j of laser pulse is counted;
6. the CCD without impact damper 17 is triggered TTL signal and return CCD level height information by FPGA communication unit 7 to microcontroller 3, microcontroller 3 enters and judges whether CCD pulse signal is high level.If CCD is high level, enter (7); If CCD is low level, enter step (12);
7. microcontroller 3 writes the right gating time delay of the jth pulse of storage and width parameter (initial value of j is 0) by FPGA communication unit 7 to time delay administration module and pulsewidth generation unit in this external trigger is interrupted, and opens the selection out gate 16 of laser and storbing gate;
8.FPGA produces pulse laser and triggers TTL signal and corresponding storbing gate triggering TTL signal;
9. pulse adds 1 to count value j, and compares with M value.If j=M, show that the once circulation of time delay array completes, enter step (10), otherwise forward step (7) to;
10. a cycle period sequence completes, and pulse resets count value j, and time delay array cycle index counting i adds 1 (initial value of i is 0);
11.i and cycle period number T compares.If i=T, show that time delay array circulates the maximal value reached in the CCD time shutter, enters (12), otherwise returns (7);
A cycle index number count value i and laser counting number j resets by 12., and pulsed laser triggers TTL signal and storbing gate and triggers TTL signal behavior out gate 16 and cut out by the mode that microcontroller is write by FPGA communication unit 7;
13. EOP (end of program).
The following describes so that time delay array τ [3]={ 10,15,20}, storbing gate triggers TTL signal 19 pulsewidth t
g=[10,15,20] ns, the pulsewidth t of laser triggering TTL signal 16
l=15ns, laser triggering TTL signal frequency f
laser=10000Hz, CCD trigger TTL signal 28 frequency f
fPSit is that example illustrates that a kind of online codified synchronous control system for coded imaging and method produce the process of three road 5ns precision gate-widths and time delay codified signal that=50Hz and CCD triggers TTL signal 20 dutycycle Duty=50%, wherein the pulsewidth precision of CCD triggering TTL signal 20, laser triggering TTL signal 18 pulsewidth precision and storbing gate triggering TTL signal 19 is 5ns, and the relative time delay precision between the storbing gate trigger pulse of laser triggering pulse and its correspondence is also 5ns.Idiographic flow is as follows:
1. the time sequence parameter arranged above is sent to microcontroller 3 by host computer 1, and microcontroller 3 calculates time delay array size M=3 according to time sequence parameter, and the number of times calculating the circulation of time delay array according to formula (1) is T=33.Namely, in a CCD start pulse signal high level, the pulse be made up of time delay array is to the overall circulation of group 33 times; Calculating CCD triggering TTL signal gate-width according to formula (2) is t
cCD=10ms.Time diagram is as Fig. 7.
DCM times of frequency module 14 pairs of system input 50MHz clocks of 2.FPGA inside carry out frequency multiplication and obtain 200MHz global clock, and namely the clock period is 5ns.
3. microcontroller is converted to the number of clock period to the time sequence parameter obtained, and if laser triggering TTL signal pulsewidth is 15ns, then laser pulse width triggers TTL pulsewidth count value is 3 clock period; In like manner can obtain the frequency count of laser triggering TTL signal, 3 pulses are right in count value that frequency count that CCD triggers TTL signal, CCD trigger the pulsewidth of TTL signal and time delay array relative time delay count value and storbing gate pulse gate-width count value corresponding to each laser pulse.
4. microcontroller 3 writes the frequency count of laser triggering TTL signal and CCD triggering TTL signal to frequency division module in FPGA 15 by communication module in FPGA 7, trigger the pulsewidth count value of TTL signal to pulse-width controlled module write laser triggering TTL signal and CCD, FPGA produces CCD pulse signal 20 and laser triggering TTL signal.
5. laser pulse signal produce after by FPGA communication unit 7 to microcontroller 3 return laser light ordinal number j (initial value of j is 0).
6. microcontroller 3 according to the laser ordinal number j returned by FPGA communication module to the write of time delay generation unit to should the delay count of laser pulse and storbing gate pulsewidth count value.
7. microcontroller 3 judges whether CCD pulse signal is high level, simultaneously whether the time delay array now T that circulates exceedes the time delay array cycle index that this two field picture allows, CCD is high level, and time delay array counting i < T, microcontroller is opened laser by FPGA communication module and is selected out gate 22 and storbing gate to select out gate 22, laser pulse signal and storbing gate output of pulse signal.
8. when laser ordinal number counting j arrives 3 (size of time delay array), microcontroller resets laser ordinal number count parameter j, the array of time delay simultaneously cycle index counting i adds 1 (time delay array cycle index counting i initial value is 0), and the laser triggering TTL signal of above-mentioned coding and the output of storbing gate TTL signal are carried out in circulation in the process;
9. when time delay array count value i is more than or equal to 33 (in a two field picture time delay array can the number of times of complete cycle), microcontroller passes through FPGA communication module and cuts out laser selection out gate 21 and storbing gate selection out gate, then export by triggering TTL signal without laser triggering TTL signal and storbing gate after three and door 16.
10. when CCD low level, laser selects out gate and storbing gate to select out gate to close equally, triggers TTL signal produce without laser triggering TTL signal and storbing gate; Time delay array count value i and laser ordinal number count value j resets, i=0, j=0.
More than complete the output of the clock signal of a two field picture, until next CCD high level starts to re-start above-mentioned circulation.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further elaborated; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. the online codified synchronous control system for coded imaging, by host computer, microcontroller and on-site programmable gate array FPGA composition, codified signal exports at same a slice programmable gate device FPGA chip, it is characterized in that: the circuit module that programming logic gate array FPGA realizes comprises frequency management module, pulse-width controlled module, time delay administration module, frequency management module completes the frequency division of clock signal and process of frequency multiplication to reach the clock signal of the precision of desired signal, pulsewidth module completes and realizes the controlled TTL signal of N road pulsewidth to the counting of clock signal, time delay administration module realizes introducing at the TTL signal that N road pulsewidth is controlled counting clock signal, the pulsewidth and the time delay that finally reach N road TTL signal all can be configured.
2., as claimed in claim 1 for the online codified synchronous control system of coded imaging, wherein, microcontroller and the field programmable gate array FPGA of synchro control are programming device.
3. adopt the online codified synchronous control system for coded imaging according to claim 1 to carry out the method controlled, comprise the steps:
Step 1: host computer sends the sequential control parameter encoded to microcontroller;
Step 2: in microcontroller, processing unit carries out decoding and process to time sequence parameter;
Step 3: in microcontroller, communication unit carries out communicating with communication unit in programmable gate device FPGA and FPGA write to the time sequence parameter of decoding;
Step 4:FPGA communication unit completes and the communicating of pulse-width controlled module, and the time sequence parameter to frequency management module, time delay module and pulse-width controlled module write decoding;
Step 5: frequency management module produces the clock signal that N road has different frequency and out of phase;
The clock signal that step 6:N road has out of phase drives time delay administration module, produces the signal that N road has different frequency and relative time delay;
Step 7: pulse-width controlled module is carried out pulsewidth to the signal that N road has different frequency and a relative time delay and widened;
Step 8: export N road and there is the controlled signal of the pulsewidth of relative time delay.
4. as claimed in claim 3 carry out for the online codified synchronous control system of coded imaging the method that controls, it is characterized in that, in real time each time sequence parameter of configuration each road signal.
5. as claimed in claim 4 carry out for the online codified synchronous control system of coded imaging the method that controls, it is characterized in that, output signal number N be not less than 2 natural number.
6. as claimed in claim 4 carry out for the online codified synchronous control system of coded imaging the method that controls, it is characterized in that, host computer comprises the frequency of N road codified signal, relative time delay, pulsewidth and coded system information in the sequential control parameter that alignment microcontroller sends.
7. as claimed in claim 4 carry out for the online codified synchronous control system of coded imaging the method that controls, it is characterized in that, N road codified signal is used for triggering the codified synchro control realizing the device of synchro control in various synchro control process respectively.
8. as claimed in claim 1 for the online codified synchronous control system of coded imaging, be applied to codified technique of laser range gated super-resolution imaging and fluorescence lifetime imaging technology, its synchro control needs the triggering TTL sequence signal on three tunnels, and trigger pulse laser, storbing gate and CCD realize gated imaging respectively; Three tunnels are triggered between TTL sequence and be there is specific matching relationship, and TTL sequence is triggered according to coded system work in three tunnels.
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| CN109357758A (en) * | 2018-09-04 | 2019-02-19 | 南昌大学 | A kind of control device and control method of the imaging of hypersensitive single photon compressed spectrum |
| CN109297905A (en) * | 2018-10-09 | 2019-02-01 | 中国科学院半导体研究所 | Two-door control fluorescence associated imaging device and imaging method |
| CN109297905B (en) * | 2018-10-09 | 2020-08-04 | 中国科学院半导体研究所 | Double-gating related fluorescence imaging device and imaging method |
| CN109253992A (en) * | 2018-10-24 | 2019-01-22 | 中国空气动力研究与发展中心超高速空气动力研究所 | A kind of plasma fluorescence lifetime measurement device and method |
| CN111812667A (en) * | 2019-04-10 | 2020-10-23 | 苏州科瓴精密机械科技有限公司 | Method for improving resolution of laser turntable and robot system |
| CN111812667B (en) * | 2019-04-10 | 2023-06-06 | 苏州科瓴精密机械科技有限公司 | Method for improving resolution of laser turntable and robot system |
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