CN108074828B - 封装结构及其形成方法 - Google Patents

封装结构及其形成方法 Download PDF

Info

Publication number
CN108074828B
CN108074828B CN201711050369.3A CN201711050369A CN108074828B CN 108074828 B CN108074828 B CN 108074828B CN 201711050369 A CN201711050369 A CN 201711050369A CN 108074828 B CN108074828 B CN 108074828B
Authority
CN
China
Prior art keywords
die
dummy
interposer
dummy die
redistribution structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201711050369.3A
Other languages
English (en)
Other versions
CN108074828A (zh
Inventor
施应庆
吴集锡
余振华
吴志伟
林俊成
王卜
卢思维
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN108074828A publication Critical patent/CN108074828A/zh
Application granted granted Critical
Publication of CN108074828B publication Critical patent/CN108074828B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8181—Soldering or alloying involving forming an intermetallic compound at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/81895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10271—Silicon-germanium [SiGe]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10331—Gallium phosphide [GaP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10332—Indium antimonide [InSb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10333—Indium arsenide [InAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10335—Indium phosphide [InP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/14335—Digital signal processor [DSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

实施例是一种方法，该方法包括使用第一电连接件将第一管芯接合至中介片的第一侧，使用第二电连接件将第二管芯接合至中介片的第一侧，将第一伪管芯附接至邻近第二管芯的中介片的第一侧，用密封剂密封第一管芯、第二管芯和第一伪管芯，以及分割中介片和第一伪管芯以形成封装结构。本发明的实施例还提供了一种半导体结构。

Description

封装结构及其形成方法
技术领域
本发明的实施例总体涉及半导体领域，更具体地，涉及封装结构及其形成方法。
背景技术
随着集成电路(IC)的发展，由于各个电部件(即，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。大多数情况下，这种集成密度的改进来自于最小特征尺寸的不断减小，这允许更多的部件集成到给定的区域。
这些集成的改进本质上是二维(2D)的，因为由集成的部件所占据的区域实质位于半导体晶圆的表面上。集成电路增大的密度和相应减小的面积通常超过将集成电路芯片直接接合至衬底的能力。中介片已经用于将球接触区从芯片的区域再分布至中介片的更大的区域。此外，中介片已经允许包括多个芯片的三维(3D)封装件。其它封装件也已经发展为包含3D方面。
发明内容
根据本发明的一个方面，提供了一种方法，包括：使用第一电连接件将第一管芯接合至中介片的第一侧；使用第二电连接件将第二管芯接合至所述中介片的所述第一侧；将第一伪管芯附接至所述中介片的邻近所述第二管芯的所述第一侧；用密封剂密封所述第一管芯、所述第二管芯和所述第一伪管芯；以及分割所述中介片和所述第一伪管芯以形成封装结构。
根据本发明的另一个方面，提供了一种方法，包括：在衬底中形成通孔；在所述衬底的第一侧上形成第一再分布结构，所述第一再分布结构电连接至所述通孔；使用第一电连接件将逻辑管芯接合至所述第一再分布结构，所述第一电连接件电连接至所述第一再分布结构；使用第二电连接件将存储器管芯的堆叠件接合至所述第一再分布结构，所述存储器管芯的堆叠件邻近于所述逻辑管芯，所述第二电连接件电连接至所述第一再分布结构；将伪管芯附接在邻近所述存储器管芯的堆叠件的划线区域中的所述第一再分布结构上方；以及分割所述衬底、所述第一再分布结构和所述伪管芯以形成封装结构。
根据本发明的又一个方面，提供了一种结构，包括：中介片的第一侧，接合至衬底；逻辑管芯和存储器堆叠件，接合至所述中介片的第二侧，所述第二侧与所述第一侧相对；伪管芯，附接至所述中介片的所述第二侧，所述伪管芯邻近于所述逻辑管芯或所述存储器堆叠件；以及模塑材料，沿着所述逻辑管芯的侧壁、所述存储器堆叠件的侧壁和所述伪管芯的侧壁延伸，所述逻辑管芯的顶面和所述伪管芯的顶面透过所述模塑材料暴露。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图14是根据一些实施例的形成封装结构的示例性工艺的截面图和平面图。
图15A至图15F示出了根据一些实施例的封装结构的平面图。
图16A至图16F示出了根据一些实施例的封装结构的平面图。
图17A至图17D示出了根据一些实施例的封装结构的平面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了部件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地做出相应的解释。
可以在特定的上下文中讨论此处公开的实施例，即，封装结构包括邻近有源管芯的伪管芯结构以减少封装结构的翘曲。封装结构的翘曲的这种减少能够通过减小有源管芯与中介片之间的虚焊的可能性来实现更可靠的封装结构。在一些实施例中，伪管芯沿着封装结构的***，诸如在划线区域中或附近。
将参考特定上下文来描述实施例，即，使用衬底上晶圆上芯片(CoWoS)处理的管芯中介片衬底堆叠的封装件。然而，其它实施例也可以应用于其它封装件(诸如管芯管芯衬底堆叠的封装件)并且可以应用其它处理。此处讨论的实施例是提供能够实现或使用本发明的主题的实例，并且本领域普通技术人员将容易理解可以做出的修改仍保持在不同实施例的预期的范围内。以下附图中的相同的参考标号和字符用指定相同的部件。虽然方法实施例可以讨论为以特定的顺序实施，但是其它的方法实施例可以以任何逻辑顺序实施。
图1示出了一个或多个管芯68的形成。管芯68的主体60可以包括任何数量的管芯、衬底、晶体管、有源器件、无源器件等。在实施例中，主体60可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。主体60的半导体材料可以是：硅、锗；化合物半导体，包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或渐变衬底的其它衬底。主体60可以是掺杂的或未掺杂的。在有源表面62中和/或上可以形成诸如晶体管、电容器、电阻器、二极管等器件。
在有源表面62上形成包括一个或多个介电层和相应的金属化图案的互连结构64。介电层中的金属化图案可以诸如通过使用通孔和/或迹线在器件之间传输电信号，并且也可以包含诸如电容器、电阻器、电感器等的各种电子器件。可以互连各个器件和金属化图案以实施一种或多种功能。该功能可以包括存储器结构、处理结构、传感器、放大器、电源分布、输入/输出电路等。此外，在互连结构64中和/或上形成诸如导电柱(例如，包括诸如铜的金属)的管芯连接件66以提供至电路和器件的外部电连接件。在一些实施例中，管芯连接件66突出于互连结构64以形成当管芯68接合至其它结构时使用的柱结构。本领域普通技术人员将意识到，提供的以上实例用于说明的目的。可以使用适合于给定应用的其它电路。
更具体地，可以在互连结构64中形成金属间介电(IMD)层。例如，可以通过诸如旋涂、化学汽相沉积(CVD)、等离子体增强CVD(PECVD)、高密度等离子体化学汽相沉积(HDP-CVD)等的本领域已知的任何合适的方法由低k介电材料(诸如，磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成IMD层。例如，可以通过使用光刻技术在IMD层上沉积和图案化光刻胶材料以暴露IMD层的将变成金属化图案的部分来在IMD层中形成金属化图案。诸如各向异性干蚀刻工艺的蚀刻工艺可以用于在IMD层中形成对应于IMD层的暴露部分的凹槽和/或开口。该凹槽和/或开口可以用扩散阻挡层衬垫并且用导电材料填充。扩散阻挡层可以包括通过原子层沉积(ALD)等沉积的氮化钽、钽、氮化钛、钛、钴钨等或它们的组合的一层或多层。金属化图案的导电材料可以包括通过CVD、物理汽相沉积(PVD)等沉积的铜、铝、钨、银以及它们的组合等。可以诸如通过使用化学机械抛光(CMP)去除IMD层上的任何过量的扩散阻挡层和/或导电材料。
在图2中，将包括互连结构64的主体60分割为单独的管芯68。通常，各管芯68包含诸如器件和金属化图案的相同的电路，但是各管芯可以具有不同的电路。该分割可以包括锯切、切割等。
管芯68的每个均可以包括一个或多个逻辑管芯(例如，中央处理单元、图形处理单元、片上***、场可编程门阵列(FPGA)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械***(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。而且，在一些实施例中，管芯68可以是不同的尺寸(例如，不同高度和/或表面面积)，并且在其它实施例中，管芯68可以是相同的尺寸(例如，相同的高度和/或表面面积)。
图3示出了部件96(见图13)的第一侧的形成。处理期间，衬底70包括一个或多个部件96。部件96可以是中介片或另一管芯。衬底70可以是晶圆。衬底70可以包括块状半导体衬底、SOI衬底、多层半导体衬底等。衬底70的半导体材料可以是：硅、锗；化合物半导体，包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或渐变衬底的其它衬底。衬底70可以是掺杂的或未掺杂的。在衬底70的第一表面72(也可以称为有源表面)中和/或上可以形成诸如晶体管、电容器、电阻器、二极管等的器件。在部件96是中介片的实施例中，部件96通常不包括其中的有源器件，但是中介片可以包括在第一表面中和/或上形成的无源器件。
通孔(TV)74形成为从衬底70的第一表面72延伸至衬底70内。TV74有时也称为衬底通孔或当衬底70是硅衬底时，称为硅通孔。可以通过例如蚀刻、研磨、激光技术、它们的组合等在衬底70中形成凹槽来形成TV 74。可以诸如通过使用氧化技术在凹槽中形成薄介电材料。可以诸如通过CVD、ALD、PVD、热氧化、它们的组合等在衬底70的前侧上方和开口中共形地沉积薄阻挡层。阻挡层可以包括诸如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、它们的组合等的氮化物或氮氧化物。可以在薄阻挡层上方和开口中沉积导电材料。可以通过电化学镀工艺、CVD、ALD、PVD、它们的组合等形成导电材料。导电材料的实例是铜、钨、铝、银、金、它们的组合等。通过例如CMP从衬底70的前侧处去除过量的导电材料和阻挡层。因此，TV74可以包括导电材料和导电材料与衬底70之间的薄阻挡层。
再分布结构76形成在衬底70的第一表面72上方并且用于将集成电路器件(如果存在)和/或TV 74电连接在一起和/或将集成电路器件和/或TV74电连接至外部器件。再分布结构76可以包括一个或多个介电层以及介电层中的相应的金属化图案。金属化图案可以包括通孔和/或迹线以将任何器件和/或TV 74互连在一起和/或将任何器件和/或TV 74互连至外部器件。金属化图案有时称为再分布线(RDL)。介电层可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、低k介电材料(诸如PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料)、它们的化合物、它们的复合物、它们的组合等。可以通过诸如旋涂、CVD、PECVD、HDP-CVD等的本领域中已知的任何合适的方法沉积介电层。可以例如通过使用光刻技术在介电层上沉积和图案化光刻胶材料以暴露介电层的将变成金属化图案的部分来在介电层中形成金属化图案。诸如各向异性干蚀刻工艺的蚀刻工艺可以用于在介电层中形成对应于介电层的暴露部分的凹槽和/或开口。该凹槽和/或开口可以用扩散阻挡层衬垫并且用导电材料填充。扩散阻挡层可以包括通过ALD沉积的TaN、Ta、TiN、Ti、CoW等的一层或多层，并且导电材料可以包括通过CVD、PVD等沉积的铜、铝、钨、银以及它们的组合等。可以诸如通过使用CMP去除介电层上任何过量的扩散阻挡层和/或导电材料。
在导电焊盘上的再分布结构76的顶面处形成电连接件77/78。在一些实施例中，导电焊盘包括凸块下金属(UBM)。在示出的实施例中，在再分布结构76的介电层的开口中形成焊盘。在另一实施例中，焊盘(UBM)可以穿过再分布结构76的介电层的开口延伸并且也可以横跨再分布结构76的顶面延伸。以形成焊盘为例，至少在再分布结构76的介电层中的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，该金属层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层以及位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀法形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层中其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺，诸如使用氧等离子体等，来去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘。在焊盘的形成方式不同的实施例中，可以利用更多光刻胶和图案化步骤。
在一些实施例中，电连接件77/78包括金属柱77，同时金属覆盖层78位于金属柱77上方，该金属覆盖层78可以是焊料帽。包括柱77和覆盖层78的电连接件77/78有时称为微凸块77/78。在一些实施例中，金属柱77包括诸如铜、铝、金、镍、钯等或它们的组合的导电材料并且可以通过溅射、印刷、电镀、化学镀等形成。金属柱77可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱77的顶面上形成金属覆盖层78。金属覆盖层78可以包括镍、锡、锡-铅、金、铜、银、钯、铟、镍-钯-金、镍-金等或它们的组合并且可以通过镀法工艺形成。
在另一实施例中，电连接件77/78不包括金属柱并且是焊料球和/或凸块，诸如可控坍塌芯片连接(C4)凸块、由化学镀镍浸金(ENIG)、化学镀镍钯浸金(ENEPIG)形成的凸块等。在本实施例中，凸块电连接件77/78可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在本实施例中，通过诸如蒸发、电镀、印刷、焊料转移、植球等的这些常用方法首先形成焊料层来形成电连接件77/78。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。
在图4中，例如，通过将电连接件77/78和管芯上的金属柱79以倒装芯片接合的方式形成导电接头91，而将管芯68和管芯88附接至部件96的第一侧。金属柱79可以与金属柱77类似因此不在此处重复描述。可以使用例如拾取和放置工具将管芯68和管芯88放置在电连接件77/78上。在一些实施例中，在金属柱77(如图3所示)、管芯68和管芯88的金属柱79上形成金属覆盖层78。
可以通过与以上参照管芯68描述的类似的工艺形成管芯88。在一些实施例中，管芯88包括一种或多种存储器管芯，诸如存储器管芯(例如，DRAM管芯、SRAM管芯、高带宽存储器(HBM)管芯、混合存储立方体(HMC)管芯等)的堆叠件。在存储器管芯的堆叠件的实施例中，管芯88可以包括存储器管芯和存储器控制器，诸如例如四个或八个存储器管芯与存储器控制器的堆叠件。而且，在一些实施例中，管芯88可以是不同的尺寸(例如，不同高度和/或表面面积)，而在其它实施例中，管芯88可以是相同的尺寸(例如，相同的高度和/或表面面积)。
在一些实施例中，管芯88可以具有与管芯68的高度类似的高度(如图4所示)或在一些实施例中，管芯68和管芯88可以具有不同的高度。
管芯88包括主体80、互连结构84和管芯连接件86。管芯88的主体80可以包括任何数量的管芯、衬底、晶体管、有源器件、无源器件等。在实施例中，主体80可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。主体80的半导体材料可以是硅、锗；化合物半导体，包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或渐变衬底的其它衬底。主体80可以是掺杂的或未掺杂的。在有源表面中和/或上可以形成诸如晶体管、电容器、电阻器、二极管等的器件。
在有源表面上形成包括一个或多个介电层和相应的金属化图案的互连结构84。介电层中的金属化图案可以诸如通过使用通孔和/或迹线在各器件之间传输电信号，并且也可以包含诸如电容器、电阻器、电感器等的各个电子器件。可以互连各个器件和金属化图案以实施一种或多种功能。该功能可以包括存储器结构、处理结构、传感器、放大器、电源分配、输入/输出电路等。此外，在互连结构84中和/或上形成诸如导电柱(例如，包括诸如铜的金属)的管芯连接件86以提供至电路和器件的外部电连接。在一些实施例中，管芯连接件86突出于互连结构84以形成当管芯88接合至其它结构时使用的柱结构。本领域普通技术人员将意识到，提供的以上实例用于说明的目的。可以使用适合于给定应用的其它电路。
更具体地，可以在互连结构84中形成IMD层。例如，可以通过诸如旋涂、CVD、PECVD、HDP-CVD等的本领域已知的任何合适的方法由低k介电材料(诸如，PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成IMD层。可以例如通过使用光刻技术在IMD层上沉积和图案化光刻胶材料以暴露IMD层的将变成金属化图案的部分来在IMD层中形成金属化图案。诸如各向异性干蚀刻工艺的蚀刻工艺可以用于在IMD层中形成对应于IMD层的暴露部分的凹槽和/或开口。该凹槽和/或开口可以用扩散阻挡层衬垫并且用导电材料填充。扩散阻挡层可以包括通过ALD等沉积的氮化钽、钽、氮化钛、钛、钴钨等或它们的组合的一层或多层。金属化图案的导电材料可以包括通过CVD、PVD等沉积的铜、铝、钨、银以及它们的组合等。可以诸如通过使用CMP去除IMD层上的任何过量的扩散阻挡层和/或导电材料。
在管芯连接件66和86分别突出于互连结构64和84的实施例中，金属柱79可以从管芯68和88排除，因为突出的管芯连接件66和86可以用作金属覆盖层78的支柱。
导电接头91通过互连结构84和64以及管芯连接件86和66将管芯68和88中的电路分别电连接至部件96中的再分布结构76和TV 74。
在一些实施例中，在接合电连接件77/78之前，电连接件77/78涂覆有助焊剂(未示出)，诸如免清洗助焊剂。电连接件77/78可以浸入助焊剂中或可以将助焊剂喷射至电连接件77/78。在另一实施例中，也可以将助焊剂施加至电连接件79/78。在一些实施例中，电连接件77/78和/或79/78可以在被回流之前具有形成在其上的环氧助焊剂，在将管芯68和管芯88附接至部件96之后，环氧助焊剂的至少一些环氧部分保留。该保留的环氧部分可以用作底部填充物以减小应力并且保护由回流电连接件77/78/79而产生的接头。
管芯68和88与部件96之间的接合可以是焊料接合或直接金属-金属(诸如铜-铜或锡-锡)接合。在实施例中，管芯68和管芯88通过回流工艺接合至部件96。在这种回流工艺期间，电连接件77/78/79分别与管芯连接件66和86、再分布结构76的焊盘接触，以将管芯68和管芯88物理连接和电连接至部件96。在接合工艺之后，可以在金属柱77和79与金属覆盖层78的界面处形成IMC(未示出)
在图4和随后的附图中，分别示出了用于形成第一封装件和第二封装件的第一封装区域90和第二封装区域92。划线区域94位于邻近的封装区域之间。如图4示出的，第一管芯和多个第二管芯均附接在第一封装区域90和第二封装区域92的每个中。
在一些实施例中，管芯68是片上***(SoC)或图形处理单元(GPU)并且第二管芯是可以由管芯68使用的存储器管芯。在实施例中，管芯88是堆叠的存储器管芯。例如，堆叠的存储器管芯88可以包括低功率(LP)双数据率(DDR)存储器模块，诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块。
在图5中，将底部填充材料100分配至管芯68、管芯88与再分布结构76之间的间隙中。底部填充材料100可以沿着管芯66和管芯88的侧壁向上延伸。底部填充材料100可以是任何可接受的材料，诸如聚合物、环氧树脂、模塑底部填充物等。底部填充材料100可以在管芯68和88附接之后通过毛细管流动工艺形成，或可以在管芯68和88附接之前，通过合适的沉积该方法形成。
图6A、图6B、图6C、图6D、图6E和图6F示出了包括粘合至部件96的伪管芯106的封装结构的平面图。图7是示出封装结构中的伪管芯106的截面图。图7是沿着平面图图6C的线A-A截取的。可以通过使用例如拾取和放置工具将伪管芯106放置在部件96上。
在图6A中，伪管芯106附接在划线区域94中并且沿着沿第一方向(例如，图6A的垂直方向)的划线区域94延伸。在图6B中，伪管芯106附接在同一区域90和/或92的邻近的管芯88之间。在图6C中，伪管芯106附接在划线区域94中并且沿着沿第一方向和第二方向(例如，图6C的垂直和水平方向)的划线区域94延伸并且也介于同一区域90和/或92的邻近的管芯88之间。
在图6D中，伪管芯106附接在同一区域90和/或92的邻近的管芯88之间，并且不在划线区域94中而是在划线区域94附近。在图6E中，除了伪管芯106也附接在区域90和/或92的邻近管芯88的拐角附近之外，伪管芯106的配置与图6D的配置类似。再者，在本实施例中，伪管芯106不在划线区域94中而是在划线区域94附近。在图6F中，伪管芯106附接在区域90和/或92的邻近管芯88的拐角附近，并且不在划线区域94中而是在划线区域94附近。
放置在划线区域94中或附近的伪管芯106可以有助于防止在封装件的分割期间和之后(见图13)在第一封装区域90和第二分装区域92中的翘曲。例如，与没有任何伪管芯106的封装件相比，图6C的实施例(以及之后讨论的图15C中的分割的封装件)可以将封装件的翘曲减少至高达约60％。
伪管芯106可以有助于减少翘曲的一种方式是在实际分割工艺期间对封装件提供支撑。伪管芯106可以防止翘曲的另一种方式是减少部件96与随后形成的密封剂112(见图8)之间的热膨胀系数(CTE)失配，因为伪管芯106具有与部件96类似的CTE并且伪管芯减少了封装件中必需的密封剂112的量。
参照图7，伪管芯106粘合在邻近管芯88的划线区域94中。伪管芯106通过附接结构104附接至部件96。在一些实施例中，附接结构104是将伪管芯106粘合至部件96的粘合剂。在一些实施例中，附接结构104是具有金属覆盖层的一个或多个金属柱(有时称为微凸块)，附接结构104将伪管芯106接合至部件。伪管芯106可以由硅、介电材料等或它们的组合制成。在一些实施例中，伪管芯106实际上是有缺陷的有源管芯，被回收用作伪管芯106。在一些实施例中，伪管芯106的顶面与管芯68的背侧齐平。
在附接结构104是粘合剂的实施例中，粘合剂104位于伪管芯106的底面上并且将伪管芯106粘合至部件96，诸如示出的再分布结构76。粘合剂104可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。可以将粘合剂104施加至伪管芯106的底面或可以将粘合剂104施加在再分布结构76的表面上方。可以使用例如拾取和放置工具，通过粘合剂104将伪管芯106粘合至再分布结构76。可以在伪管芯106粘合之前或之后固化底部填充物100。
在附接结构104是微凸块的实施例中，在伪管芯106的底面上、部件96的顶面上或两者上形成微凸块104。微凸块104可以与接合管芯68和88的微凸块(例如，电连接件77/78)同时形成。微凸块104将伪管芯106接合至部件96，诸如示出的再分布结构76。伪管芯106的微凸块104可以与管芯68和88的电连接件77/78/79/78一起回流。可以通过使用例如拾取和放置工具将伪管芯106放置在微凸块104上。可以在伪管芯106接合之前和之后固化底部填充物100。
在图8中，在各个部件上形成密封剂112。密封剂112可以是模塑料、环氧树脂等，并且可以通过压缩模塑、传递模塑等施加。实施固化步骤以固化密封剂112，诸如热固化、紫外线(UV)固化等。在一些实施例中，管芯68、管芯88和伪管芯106掩埋在密封剂112中，并且在密封剂112的固化之后，可以实施诸如研磨的平坦化步骤以去除密封剂112的过量部分，该过量部分位于管芯68、管芯88和伪管芯106的顶面上方。因此，管芯68、管芯88和伪管芯106的顶面暴露，并且与密封剂112的顶面齐平。在一些实施例中，管芯88和/或伪管芯106可以与管芯68的高度不同，并且在平坦化步骤之后，管芯88和/或伪管芯106将仍由密封剂112覆盖。在一些实施例中，伪管芯106具有大于管芯68和88的高度并且在平坦化步骤之后，管芯68和88仍由密封剂112覆盖。
图9至图12示出了部件96的第二侧的形成。在图9中，翻转图8的结构以为部件96的第二侧的形成做准备。虽然未示出，但是该结构可以放置在载体或支撑结构上以用于图9至图12的工艺。如图9所示，在这个工艺阶段，衬底70和部件96的再分布结构76具有在约50μm至约775μm范围内(诸如约775μm)的组合厚度T1。伪管芯106(包括附接结构104)具有在约30μm至约775μm的范围内(诸如约760μm)的厚度T2。在一些实施例中，管芯68和88的一个或两个(包括导电接头91)具有厚度T2。
在图10中，对衬底70的第二侧实施减薄工艺以将衬底70减薄至第二表面116，直至暴露TV 74。该减薄工艺可以包括蚀刻工艺、研磨工艺等或它们的组合。在一些实施例中，在减薄工艺之后，部件96的衬底70和再分布结构76具有在约30μm至约200μm的范围内(诸如约100μm)的组合厚度T3。
在图11中，再分布结构形成在衬底70的第二表面116上，并且用于将TV 74电连接在一起和/或电连接至外部器件。再分布结构包括一个或多个介电层117以及位于一个或多个介电层117中的金属化图案118。金属化图案可以包括将TV 74互连在一起和/或互连至外部器件的通孔和/或迹线。金属化图案118有时称为再分布线(RDL)。介电层117可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、低k介电材料(诸如PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料)、它们的化合物、它们的复合物、它们的组合等。可以通过诸如旋涂、CVD、PECVD、HDP-CVD等的本领域中已知的任何合适的方法沉积介电层117。可以例如通过使用光刻技术在介电层117上沉积和图案化光刻胶材料以暴露介电层117的将变成金属化图案118的部分来在介电层117中形成金属化图案118。诸如各向异性干蚀刻工艺的蚀刻工艺可以用于在介电层117中形成对应于介电层117的暴露部分的凹槽和/或开口。该凹槽和/或开口可以用扩散阻挡层衬垫并且用导电材料填充。扩散阻挡层可以包括通过ALD沉积的TaN、Ta、TiN、Ti、CoW等的一层或多层，并且导电材料可以包括通过CVD、PVD、镀法等沉积的铜、铝、钨、银以及它们的组合等。可以诸如通过使用CMP去除介电层上任何过量的扩散阻挡层和/或导电材料。
在图12中，电连接件120也形成在金属化图案118上并且电连接至TV 74。在金属化图案118上的再分布结构的顶面处形成电连接件120。在一些实施例中，金属化图案118包括UBM。在示出的实施例中，在再分布结构的介电层117的开口中形成焊盘。在另一实施例中，焊盘(UBM)可以延伸穿过再分布结构的介电层117的开口并且也可以横跨再分布结构的顶面延伸。
以形成焊盘为例，至少在再分布结构的介电层117的一个的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，该金属层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层以及位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成和图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀法形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层中其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层和导电材料的剩余部分形成焊盘。在焊盘的形成方式不同的实施例中，可以利用更多光刻胶和图案化步骤。
在一些实施例中，电连接件120是焊料球和/或凸块，诸如球栅阵列(BGA)球、C4微凸块、ENIG形成的凸块、ENEPIG形成的凸块等。电连接件120可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，通过诸如蒸发、电镀、印刷、焊料转移、植球等的这些常用方法首先形成焊料层来形成电连接件120。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，电连接件120是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱连接件120的顶面上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合并且可以通过镀法工艺形成。
电连接件120可以用于接合至额外的电部件，该额外的电部件可以是半导体衬底、封装衬底、印刷电路板(PCB)等(见图14中的300)。
在图13中，邻近的区域90和92之间的部件96和伪管芯106沿着划线区域94被分割以形成封装部件200，除了别的以外，封装部件200包括管芯68、部件96、管芯88和伪管芯106的部分106’。该分割可以通过锯切、切割等。如上所述，伪管芯106有助于减小在分割工艺期间和之后引起的应力和翘曲。
在分割工艺之后，伪管芯106的剩余部分106’具有与封装部件200的横向长度相连的(coterminous with)侧壁表面(例如，见图13和图14)。
图14示出了封装部件200附接在衬底300上。电连接件120与衬底300的接合焊盘对准并且抵靠衬底300的接合焊盘。可以回流电连接件120以形成衬底300和部件96之间的接合。衬底300可以包括封装衬底，诸如其中包括核心的积层衬底、包括多个层压介电膜的层压衬底、PCB等。衬底300可以包括与封装部件相对的诸如焊料球的电连接件(未示出)，以允许将衬底300安装至另一器件上。底部填充材料(未示出)可以分配在封装部件200和衬底300之间并且围绕电连接件120。底部填充材料可以是任何可接受的材料，诸如聚合物、环氧树脂、模塑底部填充物等。
此外，一个或多个表面器件140可以连接至衬底300。表面器件140可以用于对封装部件200或整个封装件提供额外的功能或编程。在实施例中，表面器件140可以包括期望连接至封装部件200或封装件的其它部分并且与封装部件200或封装件的其它部分结合使用的表面贴装器件(SMD)或集成无源器件(IPD)，集成无源器件包括无源器件，诸如电阻器、电感器、电容器、跳线、这些的组合等。根据各个实施例，可以在衬底300的第一主表面上、衬底300的相对主表面上或两者上放置表面器件400。
图15A、图15B、图15C、图15D、图15E和图15F示出了分别在图6A、图6B、图6C、图6D、图6E和图6F示出的每个伪管芯106的实施例中的分割的封装结构的平面图。这些实施例是关于管芯68对称的，其中，在管芯68的相对两侧上具有管芯88和伪管芯106。
图16A、图16B、图16C、图16D、图16E和图16F示出了分别在图6A、图6B、图6C、图6D、图6E和图6F示出的每个伪管芯106实施例中的其它实施例中的分割的封装结构的平面图。在这些实施例中，分割的封装结构是非对称的，因为管芯88和伪管芯106仅位于管芯68的一侧(例如，图16A、图16B、图16C、图16D、图16E和图16F的平面图的顶侧)上。可以使用与图1至图5和图7至图14的以上描述的那些类似的材料、结构和工艺制造这些封装结构，因此此处不再重复描述。
图17A、图17B和图17C分别示出了在与图6A、图6B和图6C类似的工艺点处以及类似的伪管芯配置106的平面图，除了在这些实施例中，每个封装结构中均存在更多的管芯88。可以使用与图1至图5和图7至图14的以上描述的那些类似的材料、结构和工艺制造这些封装结构，因此此处不再重复描述。
图17D示出了与图17A至图17C中的那些伪管芯106配置类似的另一实施例的平面图，除了在本实施例中，伪管芯106位于区域90和92内而没有位于划线区域94中。可以使用与图1至图5和图7至图14的以上描述的那些类似的材料、结构和工艺制造这些封装结构，因此此处不再重复描述。这种类型的配置(例如，在划线区域94中没有伪管芯106)也可以应用于上述任何先前的配置。
所公开的包括邻近于有源管芯的伪管芯结构的封装结构的实施例可以有助于减少封装结构的翘曲。封装结构的翘曲的这种减少能够通过减小有源管芯和中介片之间的虚焊的可能性来实现更可靠的封装结构。例如，与没有任何伪管芯的封装件相比，公开的实施例可以减少封装件的翘曲约60％。在一些实施例中，伪管芯位于划线区域中或附近有助于防止封装件的分割期间和之后的翘曲。伪管芯可以有助于减少翘曲的一种方式是在实际分割工艺期间对封装件提供支撑。伪管芯可以防止翘曲的另一种方式是由于伪管芯具有与中介片类似的CTE并且伪管芯减少了封装件中必需的密封剂的量，因此可以减少中介片和密封剂之间的CTE失配。
在实施例中，一种方法包括：使用第一电连接件将第一管芯接合至中介片的第一侧；使用第二电连接件将第二管芯接合至中介片的第一侧；将第一伪管芯附接至邻近第二管芯的中介片的第一侧；用密封剂密封第一管芯、第二管芯和第一伪管芯；以及分割中介片和第一伪管芯以形成封装结构。
实施例可以包括一个或多个以下特征。在该方法中，中介片是第三管芯。在该方法中，中介片是包括再分布结构的块状衬底，第一管芯和第二管芯接合至再分布结构。在该方法中，分割包括穿过中介片和第一伪管芯的锯切以形成封装结构。在该方法中，第一管芯包括一个或多个逻辑管芯，并且其中，第二管芯包括一个或多个存储器管芯。该方法还包括：在中介片以及第一管芯和第二管芯之间形成围绕第一电连接件和第二电连接件的底部填充物，在底部填充物上方形成密封剂。该方法还包括：形成穿过中介片延伸的通孔，第一管芯和第二管芯电连接至通孔；在中介片的第二侧上形成第三电连接件，第二侧与第一侧相对，第三电连接件电连接至通孔；使用第三电连接件将封装结构安装至衬底；以及将表面贴装器件(SMD)接合至衬底。在该方法中，第一伪管芯。在该方法中，将第一伪管芯附接至中介片的第一侧包括：用粘合层将第一伪管芯粘合至中介片的第一侧。在该方法中，将第一伪管芯附接至中介片的第一侧包括：用第四电连接件将第一伪管芯接合至中介片的第一侧。
在实施例中，一种方法包括：在衬底中形成通孔；在衬底的第一侧上形成第一再分布结构，第一再分布结构电连接至通孔；使用第一电连接件将逻辑管芯接合至第一再分布结构，第一电连接件电连接至第一再分布结构；使用第二电连接件将存储器管芯的堆叠件接合至第一再分布结构，存储器管芯的堆叠件邻近逻辑管芯，第二电连接件电连接至第一再分布结构；将伪管芯附接在邻近存储器管芯的堆叠件的划线区域中的第一再分布结构上方；以及分割衬底、第一再分布结构和伪管芯以形成封装结构。
实施例可以包括一个或多个以下特征。在该方法中，分割包括穿过衬底、第一再分布结构和位于划线区域中的伪管芯的锯切，以形成封装结构。该方法还包括：在第一再分布结构以及逻辑管芯和存储器管芯的堆叠件之间形成围绕第一电连接件和第二电连接件的底部填充物；以及用密封剂密封逻辑管芯、存储器管芯的堆叠件以及伪管芯，密封剂邻接部分底部填充物。在该方法中，伪管芯由硅制成。在该方法中，将伪管芯附接在第一再分布结构上方包括：用粘合层将伪管芯粘合至第一再分布结构。在该方法中，将伪管芯附接在第一再分布结构上方包括：用第三电连接件将伪管芯接合至第一再分布结构。该方法还包括：减薄衬底的第二侧以暴露通孔的端部，第二侧与第一侧相对；在衬底的第二侧上形成第二再分布结构，第二再分布结构电连接至通孔的暴露端；在第二再分布结构上形成电连接至第二再分布结构的第四电连接件；将第四电连接件接合至第二衬底；以及将第二安装器件(SMD)接合至邻近第四电连接件的一个的第二衬底。
在实施例中，一种结构包括：中介片的接合至衬底的第一侧；接合至中介片的第二侧的逻辑管芯和存储器堆叠件，第二侧与第一侧相对；附接至中介片的第二侧的伪管芯，该伪管芯邻近于逻辑管芯或存储器堆叠件；以及沿着逻辑管芯、存储器堆叠件和伪管芯的侧壁延伸的模塑材料，逻辑管芯和伪管芯的顶面透过模塑材料暴露。
实施例可以包括一个或多个以下特征。在该结构中，伪管芯具有与中介片的横向长度相连的侧壁表面。在该结构中，伪管芯由硅制成。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种方法，包括：
使用第一电连接件将第一管芯接合至中介片的第一侧；
使用第二电连接件将第二管芯接合至所述中介片的所述第一侧，所述第二管芯与所述第一管芯相邻；
使用第三电连接件将第三管芯接合至所述中介片的所述第一侧，所述第三管芯与所述第一管芯相邻；
将第一伪管芯附接至所述中介片的邻近所述第二管芯的所述第一侧；
将第二伪管芯附接至所述中介片的邻近所述第三管芯的所述第一侧，所述第二伪管芯是与所述第一伪管芯物理分隔开的不同伪管芯，其中，所述第二伪管芯、所述第二管芯和所述第三管芯设置在所述第一伪管芯和所述第一管芯之间；
用密封剂密封所述第一管芯、所述第二管芯和所述第一伪管芯；以及
分割所述中介片和所述第一伪管芯以形成封装结构。
2.根据权利要求1所述的方法，其中，所述中介片是第四管芯。
3.根据权利要求1所述的方法，其中，所述中介片是包括再分布结构的块状衬底，所述第一管芯和所述第二管芯接合至所述再分布结构。
4.根据权利要求1所述的方法，其中，所述分割包括锯穿所述中介片和所述第一伪管芯以形成所述封装结构。
5.根据权利要求1所述的方法，其中，所述第一管芯包括一个或多个逻辑管芯，并且所述第二管芯包括一个或多个存储器管芯。
6.根据权利要求1所述的方法，还包括：
在所述中介片与所述第一管芯和所述第二管芯之间并且围绕所述第一电连接件和所述第二电连接件形成底部填充物，在所述底部填充物上方形成所述密封剂。
7.根据权利要求1所述的方法，还包括：
形成延伸穿过所述中介片的通孔，所述第一管芯和所述第二管芯电连接至所述通孔；
在所述中介片的第二侧上形成第三电连接件，所述第二侧与所述第一侧相对，所述第三电连接件电连接至所述通孔；
使用所述第三电连接件将所述封装结构安装至衬底；以及
将表面贴装器件(SMD)接合至所述衬底。
8.根据权利要求1所述的方法，其中，所述第一伪管芯由硅制成。
9.根据权利要求1所述的方法，其中，将所述第一伪管芯附接至所述中介片的所述第一侧包括：
利用粘合层将所述第一伪管芯粘合至所述中介片的所述第一侧。
10.根据权利要求1所述的方法，其中，将所述第一伪管芯附接至所述中介片的所述第一侧包括：
利用第四电连接件将所述第一伪管芯接合至所述中介片的所述第一侧。
11.一种方法，包括：
在衬底中形成通孔；
在所述衬底的第一侧上形成第一再分布结构，所述第一再分布结构电连接至所述通孔；
使用第一电连接件将逻辑管芯接合至所述第一再分布结构，所述第一电连接件电连接至所述第一再分布结构；
使用第二电连接件将存储器管芯的堆叠件接合至所述第一再分布结构，所述存储器管芯的堆叠件邻近于所述逻辑管芯，所述第二电连接件电连接至所述第一再分布结构；
将第一伪管芯附接在邻近所述存储器管芯的堆叠件的划线区域中的所述第一再分布结构上方；
将第二伪管芯附接在所述划线区域的外部的所述第一再分布结构上方，所述第二伪管芯和所述存储器管芯的堆叠件设置在所述第一伪管芯和所述逻辑管芯之间；以及
分割所述衬底、所述第一再分布结构和所述第一伪管芯以形成封装结构。
12.根据权利要求11所述的方法，其中，所述分割包括锯穿所述衬底、所述第一再分布结构和位于所述划线区域中的所述第一伪管芯，以形成所述封装结构。
13.根据权利要求11所述的方法，还包括：在所述第一再分布结构与所述逻辑管芯和所述存储器管芯的堆叠件之间并且围绕所述第一电连接件和所述第二电连接件形成底部填充物；以及
利用密封剂密封所述逻辑管芯、所述存储器单元的堆叠件以及所述第一伪管芯，所述密封剂邻接所述底部填充物的部分。
14.根据权利要求11所述的方法，其中，所述第一伪管芯由硅制成。
15.根据权利要求11所述的方法，其中，将所述第一伪管芯附接在所述第一再分布结构上方包括：
利用粘合层将所述第一伪管芯粘合至所述第一再分布结构。
16.根据权利要求11所述的方法，其中，将所述第一伪管芯附接在所述第一再分布结构上方包括：
利用第三电连接件将所述第一伪管芯接合至所述第一再分布结构。
17.根据权利要求11所述的方法，还包括：
减薄所述衬底的第二侧以暴露所述通孔的端部，所述第二侧与所述第一侧相对；
在所述衬底的所述第二侧上形成第二再分布结构，所述第二再分布结构电连接至所述通孔的暴露的所述端部；
在所述第二再分布结构上形成第四电连接件，并且所述第四电连接件电连接至所述第二再分布结构；
将所述第四电连接件接合至第二衬底；以及
将表面贴装器件(SMD)接合至邻近于所述第四电连接件的一个的所述第二衬底。
18.一种结构，包括：
中介片的第一侧，接合至衬底；
逻辑管芯和存储器堆叠件，接合至所述中介片的第二侧，所述第二侧与所述第一侧相对；
第一伪管芯，附接至邻近于所述逻辑管芯或所述存储器堆叠件的划线区域中的所述中介片的所述第二侧；
第二伪管芯，附接至所述划线区域的外部的所述中介片的所述第二侧，其中，所述第二伪管芯和所述存储器堆叠件设置在所述第一伪管芯和所述逻辑管芯之间；以及
模塑材料，沿着所述逻辑管芯的侧壁、所述存储器堆叠件的侧壁和所述第一伪管芯的侧壁延伸，所述逻辑管芯的顶面和所述第一伪管芯的顶面透过所述模塑材料暴露。
19.根据权利要求18所述的结构，其中，所述第一伪管芯具有与所述中介片的横向长度相连的侧壁表面。
20.根据权利要求18所述的结构，其中，所述第一伪管芯由硅制成。
CN201711050369.3A 2016-11-14 2017-10-31 封装结构及其形成方法 Active CN108074828B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662421775P 2016-11-14 2016-11-14
US62/421,775 2016-11-14
US15/675,288 2017-08-11
US15/675,288 US10529690B2 (en) 2016-11-14 2017-08-11 Package structures and methods of forming the same

Publications (2)

Publication Number Publication Date
CN108074828A CN108074828A (zh) 2018-05-25
CN108074828B true CN108074828B (zh) 2020-01-14

Family

ID=62108707

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711050369.3A Active CN108074828B (zh) 2016-11-14 2017-10-31 封装结构及其形成方法

Country Status (4)

Country Link
US (2) US10529690B2 (zh)
KR (1) KR102103531B1 (zh)
CN (1) CN108074828B (zh)
TW (1) TWI717561B (zh)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10043769B2 (en) 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US10050013B2 (en) * 2015-12-29 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
US10153222B2 (en) 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US11527454B2 (en) 2016-11-14 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11101260B2 (en) * 2018-02-01 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a dummy die of an integrated circuit having an embedded annular structure
US10381339B1 (en) * 2018-03-21 2019-08-13 Globalfoundries Singapore Pte. Ltd. Integrated circuits with memory cell test circuits and methods for producing the same
US10685937B2 (en) 2018-06-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package having dummy structures and method of forming same
US10866373B2 (en) * 2018-06-27 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Optical transceiver and manufacturing method thereof
KR102450575B1 (ko) * 2018-07-10 2022-10-07 삼성전자주식회사 뒤틀림의 제어를 위한 채널을 포함하는 반도체 칩 모듈 및 이의 제조 방법
WO2020042040A1 (zh) * 2018-08-29 2020-03-05 华为技术有限公司 一种下行数据早传方法及装置
KR102534734B1 (ko) 2018-09-03 2023-05-19 삼성전자 주식회사 반도체 패키지
US10867919B2 (en) 2018-09-19 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Electronic device and manufacturing method thereof
US10529637B1 (en) * 2018-10-31 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US20200168527A1 (en) * 2018-11-28 2020-05-28 Taiwan Semiconductor Manfacturing Co., Ltd. Soic chip architecture
US11488906B2 (en) 2019-01-24 2022-11-01 Samsung Electro-Mechanics Co., Ltd. Bridge embedded interposer, and package substrate and semiconductor package comprising the same
KR20200092236A (ko) * 2019-01-24 2020-08-03 삼성전기주식회사 브리지 내장 인터포저, 및 이를 포함하는 패키지 기판 및 반도체 패키지
TWI721383B (zh) * 2019-03-08 2021-03-11 力成科技股份有限公司 具有多個積體電路單元的封裝結構及其製作方法
US11626448B2 (en) 2019-03-29 2023-04-11 Lumileds Llc Fan-out light-emitting diode (LED) device substrate with embedded backplane, lighting system and method of manufacture
US10861799B1 (en) 2019-05-17 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy die placement without backside chipping
US11133282B2 (en) * 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11244879B2 (en) * 2019-09-26 2022-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
US11315860B2 (en) * 2019-10-17 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing process thereof
US11621244B2 (en) * 2019-11-15 2023-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
KR20210059417A (ko) * 2019-11-15 2021-05-25 삼성전자주식회사 보강 구조물을 갖는 반도체 패키지
US11621173B2 (en) 2019-11-19 2023-04-04 Lumileds Llc Fan out structure for light-emitting diode (LED) device and lighting system
TWI747288B (zh) * 2019-12-12 2021-11-21 友達光電股份有限公司 晶片
US11610921B2 (en) * 2019-12-12 2023-03-21 Au Optronics Corporation Chip having a flexible substrate
US11777066B2 (en) 2019-12-27 2023-10-03 Lumileds Llc Flipchip interconnected light-emitting diode package assembly
US11664347B2 (en) 2020-01-07 2023-05-30 Lumileds Llc Ceramic carrier and build up carrier for light-emitting diode (LED) array
US11211262B2 (en) * 2020-01-16 2021-12-28 International Business Machines Corporation Electronic apparatus having inter-chip stiffener
US11462418B2 (en) * 2020-01-17 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11476217B2 (en) 2020-03-10 2022-10-18 Lumileds Llc Method of manufacturing an augmented LED array assembly
US11521959B2 (en) * 2020-03-12 2022-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Die stacking structure and method forming same
DE102020119293A1 (de) 2020-03-12 2021-09-16 Taiwan Semiconductor Manufacturing Co., Ltd. Die-stapelstruktur und verfahren zum bilden derselben
US11380611B2 (en) * 2020-03-30 2022-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Chip-on-wafer structure with chiplet interposer
US11948930B2 (en) * 2020-04-29 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacturing the same
US11929261B2 (en) 2020-05-01 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
DE102020130996A1 (de) * 2020-05-01 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-package und verfahren zu dessen herstellung
DE102020130962A1 (de) * 2020-05-29 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und herstellungsverfahren
US11894318B2 (en) 2020-05-29 2024-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11552074B2 (en) * 2020-06-15 2023-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of fabricating the same
US11631647B2 (en) * 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
KR20220007192A (ko) * 2020-07-10 2022-01-18 삼성전자주식회사 언더필이 구비된 반도체 패키지 및 이의 제조 방법
KR20220023848A (ko) * 2020-08-20 2022-03-03 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR20220030638A (ko) 2020-09-03 2022-03-11 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US11430708B2 (en) * 2020-11-06 2022-08-30 Advanced Semiconductor Engineering, Inc. Package structure and circuit layer structure including dummy trace and manufacturing method therefor
US20220148953A1 (en) * 2020-11-09 2022-05-12 Qualcomm Incorporated Hybrid reconstituted substrate for electronic packaging
US20220157777A1 (en) * 2020-11-13 2022-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package having dummy dies and method of forming the same
US11515268B2 (en) * 2021-03-05 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
WO2023145388A1 (ja) * 2022-01-25 2023-08-03 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置及び電子機器
US20230253748A1 (en) * 2022-02-08 2023-08-10 e-con Systems India Private Limited Method for Securing the Electrical Contacts in a Connector System
CN117954335A (zh) * 2024-03-22 2024-04-30 甬矽半导体(宁波)有限公司 基于重构晶圆的封装方法和基于重构晶圆的封装结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194804A (zh) * 2010-03-04 2011-09-21 台湾积体电路制造股份有限公司 封装结构
CN105006456A (zh) * 2014-04-24 2015-10-28 爱思开海力士有限公司 半导体封装件及其制造方法
US9478504B1 (en) * 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212315A (ja) * 2008-03-04 2009-09-17 Elpida Memory Inc 半導体装置及びその製造方法
JP2011134990A (ja) * 2009-12-25 2011-07-07 Renesas Electronics Corp 半導体装置およびその製造方法
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US20130075892A1 (en) 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
US8779599B2 (en) * 2011-11-16 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages including active dies and dummy dies and methods for forming the same
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
KR101376396B1 (ko) * 2012-03-30 2014-03-20 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
TWI508249B (zh) 2012-04-02 2015-11-11 矽品精密工業股份有限公司 封裝件、半導體封裝結構及其製法
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8963335B2 (en) 2012-09-13 2015-02-24 Invensas Corporation Tunable composite interposer
US9209156B2 (en) * 2012-09-28 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuits stacking approach
US9129944B2 (en) * 2013-01-18 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US8866290B2 (en) * 2013-03-15 2014-10-21 Intel Corporation Molded heat spreaders
TWI597786B (zh) 2013-12-19 2017-09-01 矽品精密工業股份有限公司 半導體封裝結構及其製法
US9209048B2 (en) * 2013-12-30 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Two step molding grinding for packaging applications
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
TWI590416B (zh) 2014-11-26 2017-07-01 台灣積體電路製造股份有限公司 封裝及形成封裝的方法
US10032651B2 (en) 2015-02-12 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US10043769B2 (en) * 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194804A (zh) * 2010-03-04 2011-09-21 台湾积体电路制造股份有限公司 封装结构
CN105006456A (zh) * 2014-04-24 2015-10-28 爱思开海力士有限公司 半导体封装件及其制造方法
US9478504B1 (en) * 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication

Also Published As

Publication number Publication date
KR20180054419A (ko) 2018-05-24
TWI717561B (zh) 2021-02-01
KR102103531B1 (ko) 2020-04-23
US20180138151A1 (en) 2018-05-17
TW201818514A (zh) 2018-05-16
CN108074828A (zh) 2018-05-25
US10867965B2 (en) 2020-12-15
US20190109119A1 (en) 2019-04-11
US10529690B2 (en) 2020-01-07

Similar Documents

Publication Publication Date Title
CN108074828B (zh) 封装结构及其形成方法
CN108074872B (zh) 封装件结构及其形成方法
US11373969B2 (en) Semiconductor package and method of forming the same
CN110034026B (zh) 封装件结构和方法
CN109309074B (zh) 半导体封装件及其形成方法
CN108122861B (zh) 具有虚设管芯的封装结构、半导体装置及其形成方法
US10978346B2 (en) Conductive vias in semiconductor packages and methods of forming same
US11515267B2 (en) Dummy die placement without backside chipping
US11527454B2 (en) Package structures and methods of forming the same
US20230307338A1 (en) Package structures and methods of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant