CN111431400A - Switched capacitor circuit for realizing multi-voltage output for BCD (binary coded decimal) process and realization method - Google Patents
Switched capacitor circuit for realizing multi-voltage output for BCD (binary coded decimal) process and realization method Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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- H02M1/0054—Transistor switching losses
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
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Abstract
The invention provides a switched capacitor circuit for realizing multi-voltage output for a BCD process and a realization method thereof, wherein the grid starting voltage of an individual NMOS (N-channel metal oxide semiconductor) tube is reduced by a two-stage voltage doubling technology, so that the POWER consumption in the circuit can be greatly reduced.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a switched capacitor circuit.
Background
At present, along with the development of scientific technology, household appliances are continuously miniaturized and integrated, the requirement on chips is increased, the smaller the area requirement on the chips is, the better the chip is, and the lower the cost is, the better the chip is. In the internal circuit portion of the chip, an operating voltage higher than the external voltage is sometimes required to enable the chip to operate normally. In the conventional technology, when a charge pump circuit exists in the circuit, as the output voltage of the charge pump is larger, the grid voltage required when an NMOS tube in the circuit is started is larger, and the grid voltage needs to be separately provided with large starting voltage for the grid of the NMOS tube, so that the power consumption of a large power supply exists in the whole charge pump circuit, and the optimization design of the whole circuit is not facilitated.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a switched capacitor circuit for realizing multi-voltage output in a BCD (binary coded decimal) process and an implementation method thereof. According to the invention, through a two-stage voltage doubling technology, the grid starting voltage of the single NMOS tube is reduced, the power consumption of a power supply in a circuit can be greatly reduced, and the technical problems in the related field can be effectively solved.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a switched capacitor circuit for realizing multi-voltage output in a BCD process comprises P-channel enhanced MOS transistors PM1-PM4, N-channel enhanced MOS transistors NM1-NM4, capacitors C1-C4, rectifier diodes D1 and D2, an inverter INV1, a VIN input port, a C L K logic input port and a VBST output port;
the source electrode of the P-channel enhanced MOS tube PM1 is connected with the source electrode of the P-channel enhanced MOS tube PM2, the anode of the rectifier diode D1 and the VBST output port, the drain electrode of the P-channel enhanced MOS tube PM2 is connected with the grid electrode of the P-channel enhanced MOS tube PM2, the drain electrode of the N-channel enhanced MOS tube NM1, the grid electrode of the N-channel enhanced MOS tube NM2 and the upper plate of the capacitor C1, and the grid electrode of the P-channel enhanced MOS tube PM2 is connected with the drain electrode of the N-channel enhanced MOS tube NM1, the drain electrode of the N-channel;
the source electrode of the P-channel enhanced MOS tube PM2 is connected with the source electrode of the P-channel enhanced MOS tube PM1, the anode of the rectifier diode D1 and the VBST output port, the drain electrode of the P-channel enhanced MOS tube PM1 is connected with the grid electrode of the P-channel enhanced MOS tube PM1, the drain electrode of the N-channel enhanced MOS tube NM2, the grid electrode of the N-channel enhanced MOS tube NM1 and the upper plate of the capacitor C3, and the grid electrode of the P-channel enhanced MOS tube PM1 is connected with the drain electrode of the N-channel enhanced MOS tube NM2, the drain electrode of the N-channel;
the source electrode of the N-channel enhanced MOS tube NM1 is connected with the source electrode of a P-channel enhanced MOS tube PM3, the source electrode of a P-channel enhanced MOS tube PM4 and the source electrode of an N-channel enhanced MOS tube NM2, and the drain electrode of the N-channel enhanced MOS tube PM1 is connected with the drain electrode of the P-channel enhanced MOS tube PM2, the gate electrode of the N-channel enhanced MOS tube NM2 and the upper electrode plate of a capacitor C1;
the source electrode of the N-channel enhanced MOS tube NM2 is connected with the source electrode of a P-channel enhanced MOS tube PM3, the source electrode of the P-channel enhanced MOS tube PM4 and the source electrode of the N-channel enhanced MOS tube NM1, the drain electrode is connected with the drain electrode of the P-channel enhanced MOS tube PM2, the grid electrode of the P-channel enhanced MOS tube PM1, the grid electrode of the N-channel enhanced MOS tube NM1 and the upper plate electrode of a capacitor C3, and the grid electrode is connected with the drain electrode of the P-channel enhanced MOS tube PM1, the grid electrode of the P-channel enhanced MOS tube PM2, the grid electrode of the N-channel;
the P-channel enhanced MOS transistors PM1 and PM2 and the N-channel enhanced MOS transistors NM1 and NM2 serve as switching tubes in the circuit and jointly form a second-layer boosting circuit of the switched capacitor circuit;
the source electrode of the P-channel enhanced MOS tube PM3 is connected with the source electrode of an N-channel enhanced MOS tube NM1, the source electrode of an N-channel enhanced MOS tube NM2 and the source electrode of a P-channel enhanced MOS tube PM4, the drain electrode of the P-channel enhanced MOS tube PM4 is connected with the grid electrode of the P-channel enhanced MOS tube NM3, the drain electrode of the N-channel enhanced MOS tube NM3, the grid electrode of the N-channel enhanced MOS tube NM4 and the upper electrode plate of a capacitor C2, and the grid electrode of the P-channel enhanced MOS tube PM4, the grid electrode of the N-channel enhanced MOS tube NM 3;
the source electrode of the P-channel enhanced MOS tube PM4 is connected with the source electrode of an N-channel enhanced MOS tube NM1, the source electrode of an N-channel enhanced MOS tube NM2 and the source electrode of a P-channel enhanced MOS tube PM3, the drain electrode is connected with the grid electrode of the P-channel enhanced MOS tube PM3, the grid electrode of an N-channel enhanced MOS tube NM3, the drain electrode of the N-channel enhanced MOS tube NM4 and the upper electrode plate of a capacitor C4, and the grid electrode is connected with the drain electrode of the P-channel enhanced MOS tube PM3, the drain electrode of the N-channel enhanced MOS tube NM3, the grid electrode of;
the source electrode of the N-channel enhanced MOS tube NM3 is connected with the source electrode of the N-channel enhanced MOS tube NM4, the anode of a rectifier diode D2 and a VIN input port, the drain electrode is connected with the drain electrode of a P-channel enhanced MOS tube PM3, the grid electrode of the P-channel enhanced MOS tube PM4, the grid electrode of the N-channel enhanced MOS tube NM4 and the upper polar plate of a capacitor C2, and the grid electrode is connected with the drain electrode of a P-channel enhanced MOS tube PM4, the drain electrode of an N-channel enhanced MOS tube NM4, the grid electrode of a P-channel enhanced MOS tube;
the source electrode of the N-channel enhanced MOS tube NM4 is connected with the source electrode of the N-channel enhanced MOS tube NM3, the anode of a rectifier diode D2 and a VIN input port, the drain electrode is connected with the drain electrode of a P-channel enhanced MOS tube PM4, the grid electrode of the P-channel enhanced MOS tube PM3, the grid electrode of the N-channel enhanced MOS tube NM3 and the upper polar plate of a capacitor C4, and the grid electrode is connected with the grid electrode of a P-channel enhanced MOS tube PM4, the drain electrode of the N-channel enhanced MOS tube NM3, the drain electrode of the P-channel enhanced MOS tube;
the P-channel enhanced MOS transistors PM3 and PM4 and the N-channel enhanced MOS transistors NM3 and NM4 serve as switching tubes in the circuit and jointly form a first-layer boosting circuit of the switched capacitor circuit;
the upper polar plate of the capacitor C1 is connected with a P-channel enhanced MOS tube PM1 drain electrode, a P-channel enhanced MOS tube PM2 grid electrode, an N-channel enhanced MOS tube NM1 drain electrode and an N-channel enhanced MOS tube NM2 grid electrode, and the lower polar plate is connected with a C L K logic input port, an inverter INV1 input end and a lower polar plate of the capacitor C2;
the upper polar plate of the capacitor C2 is connected with a P-channel enhanced MOS tube PM3 drain electrode, a P-channel enhanced MOS tube PM4 grid electrode, an N-channel enhanced MOS tube NM3 drain electrode and an N-channel enhanced MOS tube NM4 grid electrode, and the lower polar plate is connected with a C L K logic input port, an inverter INV1 input end and a lower polar plate of the capacitor C1;
the upper polar plate of the capacitor C3 is connected with a P-channel enhanced MOS tube PM2 drain electrode, a P-channel enhanced MOS tube PM1 grid electrode, an N-channel enhanced MOS tube NM2 drain electrode and an N-channel enhanced MOS tube NM1 grid electrode, and the lower polar plate is connected with the output end of the inverter INV1 and the lower polar plate of the capacitor C4;
the upper polar plate of the capacitor C4 is connected with a P-channel enhanced MOS tube PM4 drain electrode, a P-channel enhanced MOS tube PM3 grid electrode, an N-channel enhanced MOS tube NM4 drain electrode and an N-channel enhanced MOS tube NM3 grid electrode, and the lower polar plate is connected with the output end of the inverter INV1 and the lower polar plate of the capacitor C3;
the anode of the rectifier diode D1 is connected with the source electrode of a P-channel enhancement type MOS tube PM1, the source electrode of a P-channel enhancement type MOS tube PM2 and a VBST output port, and the cathode of the rectifier diode D2 is connected with the cathode of the rectifier diode D2;
the anode of the rectifier diode D2 is connected with the source of an N-channel enhancement type MOS tube NM3, the source of an N-channel enhancement type MOS tube NM4 and a VIN input port, and the cathode of the rectifier diode D1 is connected with the cathode of the rectifier diode D1;
the input port of the inverter INV1 is connected with the C L K logic input port, the lower pole plate of the capacitor C1 and the lower pole plate of the capacitor C2, and the output port of the inverter INV1 is connected with the lower pole plate of the capacitor C3 and the lower pole plate of the capacitor C4;
the capacitors C1-C4 function as charging capacitors in the circuit, and the rectifier diodes D1 and D2 function to prevent the VBST voltage from flowing backwards.
The invention also provides a method for realizing the switched capacitor circuit for realizing the multi-voltage output in the BCD process, which comprises the following specific steps:
when a switching capacitor circuit for realizing multi-voltage output in a BCD process works, the first layer of boosting circuit charges a capacitor C2 when a C L K logic port is input to a high-level V1 because P-channel enhanced MOS tube PM1-PM4 and an N-channel enhanced MOS tube NM1-NM4 serve as switching tubes to be used in the circuit, so that the voltages of upper plates of the capacitors C2 and C4 are VIN, the switching tube serving as the N-channel enhanced MOS tube NM4 is turned on, the gate voltage of the P-channel enhanced MOS tube PM3 is pulled down, the switching tube serving as the P-channel enhanced MOS tube PM3 is turned on, the source voltage of the P-channel enhanced MOS tube PM3 is equal to the upper plate voltage of the capacitor C2 and is turned to be VIN + V6867, the voltage of the C L K logic port voltage is in a low-level V1 through an INV1, the capacitor C1 is in a discharging state, the voltage of the C1 is kept as the gate voltage of the P-channel enhanced MOS tube NM1, and the gate voltage of the N-channel enhanced MOS tube PM1 is not turned on, so that the P1 is not turned on the gate of the P-channel enhanced MOS tube PM 1;
similarly, when the voltage of the second-layer boosting circuit is at a high level, the N-channel enhancement type MOS transistor NM2 and the P-channel enhancement type MOS transistor PM1 are conducted, the N-channel enhancement type MOS transistor NM1 and the P-channel enhancement type MOS transistor PM2 are not conducted, the voltage of the source end of the P-channel enhancement type MOS transistor PM3 is increased to VIN + V1 by the first-layer boosting circuit, so that the voltage is continuously increased to VIN + V1+ V1 by the second-layer boosting circuit, the voltage of the lower plates of the C3 and the C4 is increased to V1 by the inverter INV1, the voltage of the source electrode of the P-channel enhancement type MOS transistor PM4 is increased to VIN + V1 by charging of the capacitor C4 by the first-layer boosting module, the voltage is continuously increased to VIN + V1+ V1 by the second-layer boosting circuit, the cycle characteristic of the logic voltage of the C L K is integrated, and the stable VIN + V1+ V1 voltage is output at the.
The invention has the beneficial effects that:
1. the integrated circuit of the invention has simple design, is completely suitable for the conventional BCD process, and can be widely applied to a series of POWER chips such as DC-DC, L DO, POWER SWITCH and the like.
2. The grid voltage of the MOS tube serving as the switch tube in the voltage doubling module can not change due to the change of the output voltage, and the power consumption of the circuit can be effectively reduced.
Drawings
Fig. 1 is a schematic diagram of a switched capacitor circuit for realizing multi-voltage output in a conventional BCD process according to the present invention.
FIG. 2 is a simplified circuit diagram of the present invention when the output of the C L K logic port is high.
FIG. 3 is a simplified circuit diagram of the present invention when the output of the C L K logic port is low.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
A switch capacitor circuit for realizing multi-voltage output of a conventional BCD process mainly comprises P-channel enhanced MOS transistors PM1-PM4, N-channel enhanced MOS transistors NM1-NM4, capacitors C1-C4, rectifier diodes D1 and D2, an inverter INV1, an input port VIN, a logic input port C L K and a VBST output port, as shown in figure 1.
The source electrode of the P-channel enhanced MOS tube PM1 is connected with the source electrode of the P-channel enhanced MOS tube PM2, the anode of the rectifier diode D1 and the VBST output port, the drain electrode of the P-channel enhanced MOS tube PM2 is connected with the grid electrode of the P-channel enhanced MOS tube PM2, the drain electrode of the N-channel enhanced MOS tube NM1, the grid electrode of the N-channel enhanced MOS tube NM2 and the upper plate of the capacitor C1, and the grid electrode of the P-channel enhanced MOS tube PM2 is connected with the drain electrode of the N-channel enhanced MOS tube NM1, the drain electrode of the N-channel; the source electrode of the P-channel enhanced MOS tube PM2 is connected with the source electrode of the P-channel enhanced MOS tube PM1, the anode of the rectifier diode D1 and the VBST output port, the drain electrode of the P-channel enhanced MOS tube PM1 is connected with the grid electrode of the P-channel enhanced MOS tube PM1, the drain electrode of the N-channel enhanced MOS tube NM2, the grid electrode of the N-channel enhanced MOS tube NM1 and the upper plate of the capacitor C3, and the grid electrode of the P-channel enhanced MOS tube PM1 is connected with the drain electrode of the N-channel enhanced MOS tube NM2, the drain electrode of the N-channel; the source electrode of the N-channel enhanced MOS tube NM1 is connected with the source electrode of a P-channel enhanced MOS tube PM3, the source electrode of a P-channel enhanced MOS tube PM4 and the source electrode of an N-channel enhanced MOS tube NM2, and the drain electrode of the N-channel enhanced MOS tube PM1 is connected with the drain electrode of the P-channel enhanced MOS tube PM2, the gate electrode of the N-channel enhanced MOS tube NM2 and the upper electrode plate of a capacitor C1; the source electrode of the N-channel enhancement type MOS transistor NM2 is connected with the source electrode of a P-channel enhancement type MOS transistor PM3, the source electrode of a P-channel enhancement type MOS transistor PM4 and the source electrode of an N-channel enhancement type MOS transistor NM1,
the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM2, the grid electrode of the P-channel enhancement type MOS tube PM1, the grid electrode of the N-channel enhancement type MOS tube NM1 and the upper plate electrode of the capacitor C3, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the grid electrode of the P-channel enhancement type MOS tube PM2, the grid electrode of the N-channel enhancement type MOS tube NM2 and the upper plate electrode of the capacitor C39. The P-channel enhancement type MOS tubes PM1 and PM2 and the N-channel enhancement type MOS tubes NM1 and NM2 serve as switching tubes in the circuit and jointly form a second-layer boosting circuit of the switched capacitor circuit.
The source electrode of the P-channel enhanced MOS tube PM3 is connected with the source electrode of an N-channel enhanced MOS tube NM1, the source electrode of an N-channel enhanced MOS tube NM2 and the source electrode of a P-channel enhanced MOS tube PM4, the drain electrode of the P-channel enhanced MOS tube PM4 is connected with the grid electrode of the P-channel enhanced MOS tube NM3, the drain electrode of the N-channel enhanced MOS tube NM3, the grid electrode of the N-channel enhanced MOS tube NM4 and the upper electrode plate of a capacitor C2, and the grid electrode of the P-channel enhanced MOS tube PM4, the grid electrode of the N-channel enhanced MOS tube NM 3; the source electrode of the P-channel enhanced MOS tube PM4 is connected with the source electrode of an N-channel enhanced MOS tube NM1, the source electrode of an N-channel enhanced MOS tube NM2 and the source electrode of a P-channel enhanced MOS tube PM3, the drain electrode is connected with the grid electrode of the P-channel enhanced MOS tube PM3, the grid electrode of an N-channel enhanced MOS tube NM3, the drain electrode of the N-channel enhanced MOS tube NM4 and the upper electrode plate of a capacitor C4, and the grid electrode is connected with the drain electrode of the P-channel enhanced MOS tube PM3, the drain electrode of the N-channel enhanced MOS tube NM3, the grid electrode of; the source electrode of the N-channel enhanced MOS tube NM3 is connected with the source electrode of the N-channel enhanced MOS tube NM4, the anode of a rectifier diode D2 and a VIN input port, the drain electrode is connected with the drain electrode of a P-channel enhanced MOS tube PM3, the grid electrode of the P-channel enhanced MOS tube PM4, the grid electrode of the N-channel enhanced MOS tube NM4 and the upper polar plate of a capacitor C2, and the grid electrode is connected with the drain electrode of a P-channel enhanced MOS tube PM4, the drain electrode of an N-channel enhanced MOS tube NM4, the grid electrode of a P-channel enhanced MOS tube; the source electrode of the N-channel enhanced MOS tube NM4 is connected with the source electrode of the N-channel enhanced MOS tube NM3, the anode of the rectifier diode D2 and the VIN input port, the drain electrode is connected with the drain electrode of the P-channel enhanced MOS tube PM4, the grid electrode of the P-channel enhanced MOS tube PM3, the grid electrode of the N-channel enhanced MOS tube NM3 and the upper polar plate of the capacitor C4, and the grid electrode is connected with the grid electrode of the P-channel enhanced MOS tube PM4, the drain electrode of the N-channel enhanced MOS tube NM3, the drain electrode of the P-channel enhanced MOS tube. The P-channel enhancement type MOS tubes PM3 and PM4 and the N-channel enhancement type MOS tubes NM3 and NM4 serve as switching tubes in the circuit and jointly form a first-layer voltage boosting circuit of the switched capacitor circuit.
The upper plate of the capacitor C1 is connected with a drain of a P-channel enhanced MOS tube PM1, a gate of a P-channel enhanced MOS tube PM2, a drain of an N-channel enhanced MOS tube NM1 and a gate of an N-channel enhanced MOS tube NM1, the lower plate is connected with a C1K logic input port, an input end of the inverter INV1 and a lower plate of the capacitor C1, the upper plate of the capacitor C1 is connected with a drain of the P-channel enhanced MOS tube PM1, a gate of the P-channel enhanced MOS tube PM1, a drain of the N-channel enhanced MOS tube NM1 and a gate of the N-channel enhanced MOS tube NM1, the lower plate is connected with a C1K logic input port, an input end of the inverter INV1 and a lower plate of the capacitor C1, the upper plate of the capacitor C1 is connected with a drain of the P-channel enhanced MOS tube PM1, a gate of the P-channel enhanced MOS tube NM1, a drain of the N-channel enhanced MOS tube NM1, a lower plate is connected with a drain of the N-channel enhanced MOS tube PMN-channel enhanced MOS tube NM1, a drain of the capacitor C1, a drain of the N-channel enhanced MOS tube NM1, a drain of the capacitor C1, a gate of the N-channel enhanced MOS tube NM1, a gate of the N-channel enhanced MOS tube NM 72, a gate of the N-channel enhanced MOS tube NM1, a gate of the N-channel enhanced MOS tube, a gate of the anode of the N-.
A method for realizing a switched capacitor circuit for realizing multi-voltage output in a BCD process specifically comprises the following steps:
when the circuit works, the first-stage boost module uses a P-channel enhanced MOS transistor PM-PM and an N-channel enhanced MOS transistor NM-NM as switching transistors in the circuit, so that the voltages of upper plates of a capacitor C and a capacitor C are VIN, when a C K logic port input is at a high level V, the capacitor C is charged, the voltage of the upper plate of the capacitor C is changed into VIN + V, the switching transistor NM serving as the N-channel enhanced MOS transistor NM is conducted, the grid voltage of the P-channel enhanced MOS transistor PM is reduced, the switching transistor serving as the P-channel enhanced MOS transistor PM is conducted, the voltage of the source of the P-channel enhanced MOS transistor PM is equal to the voltage of the upper plate of the capacitor C and is changed into V + V, meanwhile, the C K logic port voltage is at a low level-V through INV, the capacitor C is in a discharging state, the C upper plate voltage keeps VIN unchanged, so that the grid voltage of the N-channel enhanced MOS transistor NM is unchanged, the switching transistor NM serving as the switching transistor N-channel enhanced MOS transistor is not conducted, the P-channel enhanced MOS transistor PM is changed into a P-channel enhanced MOS transistor V + V, when the P-V voltage is increased to a second-V voltage, the first-V voltage, the P-V voltage is increased, the P-V voltage is increased, the P boost module, the first-V voltage is increased as the first-V boost module, the first-V voltage is increased, the first-V voltage is increased, the first-V voltage of the P boost module, the first-V.
In summary, the invention provides a multi-path high-speed broadband overcurrent detection circuit for a load switch, which can effectively perform overcurrent detection and ensure the safety and reliability of the circuit. Compared with the prior overcurrent detection circuit, the method has the advantages that the whole circuit design is simple, the overcurrent of the circuit is well protected, the internal power consumption of the circuit is low, and the overcurrent protection effect on other circuits is good.
Claims (2)
1. A switched capacitor circuit for realizing multi-voltage output in a BCD (bipolar-CMOS-DMOS) process is characterized in that:
the switched capacitor circuit for realizing multi-voltage output in the BCD process comprises P-channel enhanced MOS transistors PM1-PM4, N-channel enhanced MOS transistors NM1-NM4, capacitors C1-C4, rectifier diodes D1 and D2, an inverter INV1, a VIN input port, a C L K logic input port and a VBST output port;
the source electrode of the P-channel enhanced MOS tube PM1 is connected with the source electrode of the P-channel enhanced MOS tube PM2, the anode of the rectifier diode D1 and the VBST output port, the drain electrode of the P-channel enhanced MOS tube PM2 is connected with the grid electrode of the P-channel enhanced MOS tube PM2, the drain electrode of the N-channel enhanced MOS tube NM1, the grid electrode of the N-channel enhanced MOS tube NM2 and the upper plate of the capacitor C1, and the grid electrode of the P-channel enhanced MOS tube PM2 is connected with the drain electrode of the N-channel enhanced MOS tube NM1, the drain electrode of the N-channel;
the source electrode of the P-channel enhanced MOS tube PM2 is connected with the source electrode of the P-channel enhanced MOS tube PM1, the anode of the rectifier diode D1 and the VBST output port, the drain electrode of the P-channel enhanced MOS tube PM1 is connected with the grid electrode of the P-channel enhanced MOS tube PM1, the drain electrode of the N-channel enhanced MOS tube NM2, the grid electrode of the N-channel enhanced MOS tube NM1 and the upper plate of the capacitor C3, and the grid electrode of the P-channel enhanced MOS tube PM1 is connected with the drain electrode of the N-channel enhanced MOS tube NM2, the drain electrode of the N-channel;
the source electrode of the N-channel enhanced MOS tube NM1 is connected with the source electrode of a P-channel enhanced MOS tube PM3, the source electrode of a P-channel enhanced MOS tube PM4 and the source electrode of an N-channel enhanced MOS tube NM2, and the drain electrode of the N-channel enhanced MOS tube PM1 is connected with the drain electrode of the P-channel enhanced MOS tube PM2, the gate electrode of the N-channel enhanced MOS tube NM2 and the upper electrode plate of a capacitor C1;
the source electrode of the N-channel enhanced MOS tube NM2 is connected with the source electrode of a P-channel enhanced MOS tube PM3, the source electrode of the P-channel enhanced MOS tube PM4 and the source electrode of the N-channel enhanced MOS tube NM1, the drain electrode is connected with the drain electrode of the P-channel enhanced MOS tube PM2, the grid electrode of the P-channel enhanced MOS tube PM1, the grid electrode of the N-channel enhanced MOS tube NM1 and the upper plate electrode of a capacitor C3, and the grid electrode is connected with the drain electrode of the P-channel enhanced MOS tube PM1, the grid electrode of the P-channel enhanced MOS tube PM2, the grid electrode of the N-channel;
the P-channel enhanced MOS transistors PM1 and PM2 and the N-channel enhanced MOS transistors NM1 and NM2 serve as switching tubes in the circuit and jointly form a second-layer boosting circuit of the switched capacitor circuit;
the source electrode of the P-channel enhanced MOS tube PM3 is connected with the source electrode of an N-channel enhanced MOS tube NM1, the source electrode of an N-channel enhanced MOS tube NM2 and the source electrode of a P-channel enhanced MOS tube PM4, the drain electrode of the P-channel enhanced MOS tube PM4 is connected with the grid electrode of the P-channel enhanced MOS tube NM3, the drain electrode of the N-channel enhanced MOS tube NM3, the grid electrode of the N-channel enhanced MOS tube NM4 and the upper electrode plate of a capacitor C2, and the grid electrode of the P-channel enhanced MOS tube PM4, the grid electrode of the N-channel enhanced MOS tube NM 3;
the source electrode of the P-channel enhanced MOS tube PM4 is connected with the source electrode of an N-channel enhanced MOS tube NM1, the source electrode of an N-channel enhanced MOS tube NM2 and the source electrode of a P-channel enhanced MOS tube PM3, the drain electrode is connected with the grid electrode of the P-channel enhanced MOS tube PM3, the grid electrode of an N-channel enhanced MOS tube NM3, the drain electrode of the N-channel enhanced MOS tube NM4 and the upper electrode plate of a capacitor C4, and the grid electrode is connected with the drain electrode of the P-channel enhanced MOS tube PM3, the drain electrode of the N-channel enhanced MOS tube NM3, the grid electrode of;
the source electrode of the N-channel enhanced MOS tube NM3 is connected with the source electrode of the N-channel enhanced MOS tube NM4, the anode of a rectifier diode D2 and a VIN input port, the drain electrode is connected with the drain electrode of a P-channel enhanced MOS tube PM3, the grid electrode of the P-channel enhanced MOS tube PM4, the grid electrode of the N-channel enhanced MOS tube NM4 and the upper polar plate of a capacitor C2, and the grid electrode is connected with the drain electrode of a P-channel enhanced MOS tube PM4, the drain electrode of an N-channel enhanced MOS tube NM4, the grid electrode of a P-channel enhanced MOS tube;
the source electrode of the N-channel enhanced MOS tube NM4 is connected with the source electrode of the N-channel enhanced MOS tube NM3, the anode of a rectifier diode D2 and a VIN input port, the drain electrode is connected with the drain electrode of a P-channel enhanced MOS tube PM4, the grid electrode of the P-channel enhanced MOS tube PM3, the grid electrode of the N-channel enhanced MOS tube NM3 and the upper polar plate of a capacitor C4, and the grid electrode is connected with the grid electrode of a P-channel enhanced MOS tube PM4, the drain electrode of the N-channel enhanced MOS tube NM3, the drain electrode of the P-channel enhanced MOS tube;
the P-channel enhanced MOS transistors PM3 and PM4 and the N-channel enhanced MOS transistors NM3 and NM4 serve as switching tubes in the circuit and jointly form a first-layer boosting circuit of the switched capacitor circuit;
the upper polar plate of the capacitor C1 is connected with a P-channel enhanced MOS tube PM1 drain electrode, a P-channel enhanced MOS tube PM2 grid electrode, an N-channel enhanced MOS tube NM1 drain electrode and an N-channel enhanced MOS tube NM2 grid electrode, and the lower polar plate is connected with a C L K logic input port, an inverter INV1 input end and a lower polar plate of the capacitor C2;
the upper polar plate of the capacitor C2 is connected with a P-channel enhanced MOS tube PM3 drain electrode, a P-channel enhanced MOS tube PM4 grid electrode, an N-channel enhanced MOS tube NM3 drain electrode and an N-channel enhanced MOS tube NM4 grid electrode, and the lower polar plate is connected with a C L K logic input port, an inverter INV1 input end and a lower polar plate of the capacitor C1;
the upper polar plate of the capacitor C3 is connected with a P-channel enhanced MOS tube PM2 drain electrode, a P-channel enhanced MOS tube PM1 grid electrode, an N-channel enhanced MOS tube NM2 drain electrode and an N-channel enhanced MOS tube NM1 grid electrode, and the lower polar plate is connected with the output end of the inverter INV1 and the lower polar plate of the capacitor C4;
the upper polar plate of the capacitor C4 is connected with a P-channel enhanced MOS tube PM4 drain electrode, a P-channel enhanced MOS tube PM3 grid electrode, an N-channel enhanced MOS tube NM4 drain electrode and an N-channel enhanced MOS tube NM3 grid electrode, and the lower polar plate is connected with the output end of the inverter INV1 and the lower polar plate of the capacitor C3;
the anode of the rectifier diode D1 is connected with the source electrode of a P-channel enhancement type MOS tube PM1, the source electrode of a P-channel enhancement type MOS tube PM2 and a VBST output port, and the cathode of the rectifier diode D2 is connected with the cathode of the rectifier diode D2;
the anode of the rectifier diode D2 is connected with the source of an N-channel enhancement type MOS tube NM3, the source of an N-channel enhancement type MOS tube NM4 and a VIN input port, and the cathode of the rectifier diode D1 is connected with the cathode of the rectifier diode D1;
the input port of the inverter INV1 is connected with the C L K logic input port, the lower pole plate of the capacitor C1 and the lower pole plate of the capacitor C2, and the output port of the inverter INV1 is connected with the lower pole plate of the capacitor C3 and the lower pole plate of the capacitor C4;
the capacitors C1-C4 function as charging capacitors in the circuit, and the rectifier diodes D1 and D2 function to prevent the VBST voltage from flowing backwards.
2. A method for implementing the switched capacitor circuit for implementing multi-voltage output by using the BCD process of claim 1, comprising the following steps:
when a switching capacitor circuit for realizing multi-voltage output in a BCD process works, the first layer of boosting circuit charges a capacitor C2 when a C L K logic port is input to a high-level V1 because P-channel enhanced MOS tube PM1-PM4 and an N-channel enhanced MOS tube NM1-NM4 serve as switching tubes to be used in the circuit, so that the voltages of upper plates of the capacitors C2 and C4 are VIN, the switching tube serving as the N-channel enhanced MOS tube NM4 is turned on, the gate voltage of the P-channel enhanced MOS tube PM3 is pulled down, the switching tube serving as the P-channel enhanced MOS tube PM3 is turned on, the source voltage of the P-channel enhanced MOS tube PM3 is equal to the upper plate voltage of the capacitor C2 and is turned to be VIN + V6867, the voltage of the C L K logic port voltage is in a low-level V1 through an INV1, the capacitor C1 is in a discharging state, the voltage of the C1 is kept as the gate voltage of the P-channel enhanced MOS tube NM1, and the gate voltage of the N-channel enhanced MOS tube PM1 is not turned on, so that the P1 is not turned on the gate of the P-channel enhanced MOS tube PM 1;
similarly, when the voltage of the second-layer boosting circuit is at a high level, the N-channel enhancement type MOS transistor NM2 and the P-channel enhancement type MOS transistor PM1 are conducted, the N-channel enhancement type MOS transistor NM1 and the P-channel enhancement type MOS transistor PM2 are not conducted, the voltage of the source end of the P-channel enhancement type MOS transistor PM3 is increased to VIN + V1 by the first-layer boosting circuit, so that the voltage is continuously increased to VIN + V1+ V1 by the second-layer boosting circuit, the voltage of the lower plates of the C3 and the C4 is increased to V1 by the inverter INV1, the voltage of the source electrode of the P-channel enhancement type MOS transistor PM4 is increased to VIN + V1 by charging of the capacitor C4 by the first-layer boosting module, the voltage is continuously increased to VIN + V1+ V1 by the second-layer boosting circuit, the cycle characteristic of the logic voltage of the C L K is integrated, and the stable VIN + V1+ V1 voltage is output at the.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113315371A (en) * | 2021-04-13 | 2021-08-27 | 西安拓尔微电子有限责任公司 | Self-adaptive charge pump control circuit and control method for four-switch-tube buck-boost converter |
| CN113938004A (en) * | 2021-08-31 | 2022-01-14 | 西安电子科技大学 | Novel voltage-multiplying inverter, power supply voltage conversion circuit and electronic product |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000074468A (en) * | 1999-05-21 | 2000-12-15 | 김영환 | High voltage driving circuit |
| US20110018520A1 (en) * | 2009-07-24 | 2011-01-27 | Takashi Imura | Reference voltage circuit and electronic device |
| CN110011526A (en) * | 2019-04-22 | 2019-07-12 | 西安拓尔微电子有限责任公司 | It is a kind of that circuit is protected based on the voltage-controlled UVLO applied to EA circuit |
| CN110061705A (en) * | 2019-04-22 | 2019-07-26 | 西安拓尔微电子有限责任公司 | A kind of built-in Regulator circuit and its implementation with temperature-compensating |
| CN110719093A (en) * | 2019-10-08 | 2020-01-21 | 西安拓尔微电子有限责任公司 | Multi-path high-speed broadband overcurrent detection circuit for load switch and control method |
| CN212381117U (en) * | 2020-03-13 | 2021-01-19 | 西安拓尔微电子有限责任公司 | Switched capacitor circuit for realizing multi-voltage output for BCD (binary coded decimal) process |
-
2020
- 2020-03-13 CN CN202010173207.4A patent/CN111431400B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000074468A (en) * | 1999-05-21 | 2000-12-15 | 김영환 | High voltage driving circuit |
| US20110018520A1 (en) * | 2009-07-24 | 2011-01-27 | Takashi Imura | Reference voltage circuit and electronic device |
| CN110011526A (en) * | 2019-04-22 | 2019-07-12 | 西安拓尔微电子有限责任公司 | It is a kind of that circuit is protected based on the voltage-controlled UVLO applied to EA circuit |
| CN110061705A (en) * | 2019-04-22 | 2019-07-26 | 西安拓尔微电子有限责任公司 | A kind of built-in Regulator circuit and its implementation with temperature-compensating |
| CN110719093A (en) * | 2019-10-08 | 2020-01-21 | 西安拓尔微电子有限责任公司 | Multi-path high-speed broadband overcurrent detection circuit for load switch and control method |
| CN212381117U (en) * | 2020-03-13 | 2021-01-19 | 西安拓尔微电子有限责任公司 | Switched capacitor circuit for realizing multi-voltage output for BCD (binary coded decimal) process |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113315371A (en) * | 2021-04-13 | 2021-08-27 | 西安拓尔微电子有限责任公司 | Self-adaptive charge pump control circuit and control method for four-switch-tube buck-boost converter |
| CN113315371B (en) * | 2021-04-13 | 2024-05-10 | 拓尔微电子股份有限公司 | Self-adaptive charge pump control circuit and control method for four-switching-tube buck-boost converter |
| CN113938004A (en) * | 2021-08-31 | 2022-01-14 | 西安电子科技大学 | Novel voltage-multiplying inverter, power supply voltage conversion circuit and electronic product |
| CN113938004B (en) * | 2021-08-31 | 2024-04-05 | 西安电子科技大学 | Voltage doubling inverter, power supply voltage conversion circuit and electronic product |
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