CN111371413A

CN111371413A - Analog front-end circuit suitable for human pulse signals

Info

Publication number: CN111371413A
Application number: CN202010199706.0A
Authority: CN
Inventors: 岳宏卫; 肖鑫
Original assignee: Guilin University of Electronic Technology
Current assignee: Guilin University of Electronic Technology
Priority date: 2020-03-20
Filing date: 2020-03-20
Publication date: 2020-07-03

Abstract

The invention discloses an analog front-end circuit suitable for human pulse signals, which comprises capacitors C1, C '1, C2, C' 2 and C_LAnd C'_LPseudo resistance R_pseudoAnd R'_pseudoAnd a transconductance amplifier. The pseudo resistor comprises PMOS tubes M15, M16, M19 and M20, and NMOS tubes M17, M18 and Mc. The analog front-end circuit can realize an extremely low-frequency cut-off point, reduces the whole area of a chip, reduces the cost of chip flow, is beneficial to improving the integration level, and meets the requirements of small volume and low power consumption of the biomedical portable equipment. In addition, the resistance value of the pseudo resistor structure can reach G omega to the maximum extent, and compared with the existing pseudo resistor structure, the pseudo resistor structure improves the linearity of the pseudo resistor, improves the integration level and has total harmonic distortion less than 1%.

Description

Analog front-end circuit suitable for human pulse signals

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to an analog front-end circuit suitable for human pulse signals.

Background

With the rapid development of social economy and science and technology, people pay more attention to the self health condition, and the field of biological medical treatment is rapidly developed. In addition, the microelectronic technology and the biomedicine are continuously combined and innovated, so that the system is more convenient, intelligent and efficient. For example, some portable devices such as smartphones and smartbands have functions such as heart rate monitoring and blood oxygen measurement. Medical care elements are continuously introduced into portable electronic products, so that the information of pulse, blood oxygen, body temperature, blood pressure and the like which indicate the health level of a human body can be more easily acquired.

However, since the human body pulse signal has characteristics of small amplitude, low frequency, and easy interference, the signal preprocessing is essential. The high-performance signal processing circuit has the functions of amplifying weak amplitude signals and filtering irrelevant signals except the main signal frequency, and can provide input guarantee for subsequent analog-to-digital conversion. Meanwhile, the signal processing circuit should be designed with consideration of not introducing excessive noise and offset, and should have high Common Mode Rejection Ratio (CMRR) and Power Supply Rejection Ratio (PSRR).

As the frequency of the human pulse signal is concentrated in 0.5Hz-5Hz, and the maximum frequency does not exceed 40Hz, an analog front end circuit of the human pulse signal needs to be designed with an extremely low frequency cut-off point to remove the noise frequency except the signal. In order to meet the design requirement of an extremely low frequency cut-off point, the following schemes are currently implemented: 1. discrete device resistors and capacitors are used to achieve very low frequency cut-off design requirements, but such schemes increase the power consumption of the integrated circuit and are not conducive to integration. 2. The design requirement of the extremely-low frequency cut-off point is met by using the integrated resistor and the integrated capacitor, the integration of the circuit can be improved by the scheme, but the existing integrated resistor does not exceed megaohm (M omega) at most, the integrated capacitor does not exceed 50pF, and in addition, due to the process, the resistor is easily influenced, and the accuracy of the resistance value of the resistor is greatly influenced. Therefore, the design requirement of the extremely low frequency cut-off point is far from being met by the scheme. 3. The filter circuit is specially designed, and the scheme can meet the design requirement of the extremely low frequency cut-off point, but additionally increases the power consumption and does not meet the requirement of low power consumption. 4. The MOS tube pseudo-resistor structure is adopted to meet the design requirement of the extremely-low frequency cut-off point, but the current pseudo-resistor structure has poor linearity and large fluctuation of the resistance value of the pseudo-resistor.

Disclosure of Invention

The invention provides an analog front-end circuit suitable for human pulse signals, aiming at the problems of small amplitude and low frequency of the human pulse signals.

In order to solve the problems, the invention is realized by the following technical scheme:

an analog front-end circuit suitable for human pulse signals comprises capacitors C1, C '1, C2, C' 2 and C_LAnd C'_LPseudo resistance R_pseudoAnd R'_pseudoAnd a transconductance amplifier OTA; one end of the capacitor C1 forms a forward input end of the analog front-end circuit and is connected with an input voltage signal Vin +, and the other end of the capacitor C1 is connected with a forward input end of the OTA; one end of the capacitor C '1 forms a reverse input end of the analog front-end circuit and is connected with an input voltage signal Vin-, and the other end of the capacitor C' 1 is connected with a reverse input end of the transconductance amplifier; one end of the capacitor C2 is connected with the positive input end of the transconductance amplifier, and the other end is connected with the reverse output end of the transconductance amplifier; one end of the capacitor C '2 is connected with the reverse input end of the transconductance amplifier, and the other end of the capacitor C' 2 is connected with the forward output end of the transconductance amplifier; pseudo resistance R_pseudoThe A end of the transconductance amplifier is connected with the positive input end of the transconductance amplifier, and the B end of the transconductance amplifier is connected with the negative output end of the transconductance amplifier; pseudo resistance R'_pseudoThe A end of the transconductance amplifier is connected with the reverse input end of the transconductance amplifier, and the B end of the transconductance amplifier is connected with the forward output end of the transconductance amplifier; capacitor C_LIs connected to the inverting output terminal of the transconductance amplifier and forms the inverting output terminal of the analog front-end circuit, a capacitor C_LThe other end of the connecting rod is connected with the ground end; c 'of capacitor'_LIs connected to the inverting output terminal of the transconductance amplifier and forms the forward output terminal of the analog front-end circuit, a capacitor C'_LThe other end of the connecting rod is connected with the ground end.

In the scheme, the types of the capacitors C1 and C '1 are the same, the types of the capacitors C2 and C' 2 are the same, and the capacitor C is_LAnd C'_LThe models of the devices are the same.

In the above scheme, the pseudo resistor R_pseudoAnd R'_pseudoThe structure of (2) is the same.

In the scheme, the pseudo resistor comprises PMOS tubes M15, M16, M19 and M20, and NMOS tubes M17, M18 and Mc; a gate of the PMOS transistor M15, a gate of the PMOS transistor M16, a source and a substrate of the NMOS transistor M17, a source and a substrate of the NMOS transistor M18, and a PMOThe grid electrode of the S tube M19, the grid electrode of the PMOS tube M20 and the drain electrode of the NMOS tube Mc are connected; the drain electrode of the PMOS tube M15 is connected with the substrate, the grid electrode of the NMOS tube M18 and the source electrode of the PMOS tube M19; the drain electrode of the PMOS tube M16 is connected with the substrate, the grid electrode of the NMOS tube M17 and the source electrode of the PMOS tube M20; the source electrode of the PMOS tube M15 is connected with the source electrode of the PMOS tube M16; the drain electrode of the NMOS tube M17 is connected with the drain electrode of the NMOS tube M18 and is connected with a voltage VDD; the NMOS tube Mc substrate is connected with the drain electrode and is connected with a voltage VSS; grid and voltage V of NMOS tube Mc_controlConnecting; the substrate and the drain of the PMOS tube M19 are connected, and an A end of the pseudo resistor is formed; the substrate and the drain of the PMOS transistor M20 are connected and form the B terminal of the pseudo resistor.

In the scheme, the models of the PMOS tubes M15, M16, M19 and M20 are the same, and the models of the NMOS tubes M17 and M18 are the same.

In the scheme, the transconductance amplifier comprises PMOS tubes M1, M2, M7-M14, NMOS tubes M3-M6, resistors Rs1-Rs4 and a current source Ibias; the grid electrode of the PMOS tube M1 forms the positive input end of the transconductance amplifier; the grid electrode of the PMOS tube M2 forms the inverting input end of the transconductance amplifier; the grid and the drain of the PMOS tube M9, the grid of the PMOS tube M10 and one end of a direct current power supply Ibias are connected, and the other end of the direct current power supply Ibias is grounded; the substrate and the source electrode of the PMOS transistor M2, the source electrode and the substrate of the PMOS transistor M1 and the drain electrode of the PMOS transistor M10 are connected; the grid electrode of the PMOS tube M7, the grid electrode of the PMOS tube M8, the substrate and the source electrode of the PMOS tube M12 and the substrate and the source electrode of the PMOS tube M13 are connected; the drain and the gate of the PMOS tube M11 are connected with the drain and the gate of the PMOS tube M12; the drain and the gate of the PMOS tube M13 are connected with the drain and the gate of the PMOS tube M14; the drain electrode of the PMOS tube M1, the drain electrode and the grid electrode of the NMOS tube M4 and the grid electrode of the NMOS tube M3 are connected; the drain electrode of the PMOS tube M2, the drain electrode and the grid electrode of the NMOS tube M5 and the grid electrode of the NMOS tube M6 are connected; the substrate and the source of the PMOS transistor M9, the substrate and the source of the PMOS transistor M10, the substrate and the source of the PMOS transistor M7 and the substrate and the source of the PMOS transistor M8 are connected with a voltage VDD; the substrate and the source of the PMOS transistor M3 are connected with one end of a resistor Rs 1; the substrate and the source of the NMOS tube M4 are connected with one end of a resistor Rs 2; the substrate and the source of the NMOS tube M5 are connected with one end of a resistor Rs 3; the substrate and the source of the PMOS transistor M6 are connected with one end of a resistor Rs 4; the other end of the resistor Rs1-Rs4 is simultaneously grounded; the drain electrode of the NMOS tube M3, the drain electrode of the NMOS tube M7 and the substrate and the source electrode of the PMOS tube M11 are connected, and a positive output end Vout + of the transconductance amplifier is formed; the drain of the NMOS transistor M6, the drain of the PMOS transistor M8, and the substrate and source of the PMOS transistor M13 are connected and form the inverting output terminal Vout-of the transconductance amplifier.

In the scheme, the models of PMOS tubes M1 and M2 are the same, the models of NMOS tubes M3, M4, M5 and M6 are the same, the models of PMOS tubes M7 and M8 are the same, the models of PMOS tubes M9 and M10 are the same, the models of PMOS tubes M11, M12, M13 and M14 are the same, and the models of resistors Rs1-Rs4 are the same.

Compared with the prior art, the analog front-end circuit can realize an extremely low-frequency cut-off point, reduces the whole area of a chip, reduces the cost of chip flow, is favorable for improving the integration level, and meets the requirements of small volume and low power consumption of biomedical portable equipment. In addition, the resistance value of the pseudo resistor structure can reach G omega to the maximum extent, and compared with the existing pseudo resistor structure, the pseudo resistor structure improves the linearity of the pseudo resistor and the integration level, and the Total Harmonic Distortion (THD) is less than 1%.

Drawings

FIG. 1 is a block diagram of an analog front-end circuit for human body pulse signals;

FIG. 2 is a circuit schematic of the OTA of FIG. 1;

FIG. 3 is a circuit diagram of the pseudo resistor of FIG. 1;

FIGS. 4(a) and (b) are schematic diagrams of two common pseudo resistor structures;

FIG. 5 is a graph of the adjustment of different low cut-off points f by varying different voltages_LA graph of (a).

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings in conjunction with specific examples.

An analog front-end circuit for human pulse signals, whose overall circuit structure is shown in fig. 1, comprises: capacitors C1, C' 1、C2、C’2、C_L、C’_LPseudo resistance R_pseudo、R’_pseudoAnd OTA (transconductance amplifier). One end of the capacitor C1 forms a forward input terminal of the analog front-end circuit and is connected to the input voltage signal Vin +, and the other end of the capacitor C1 is connected to a forward input terminal of the OTA. One end of the capacitor C '1 forms an inverse input end of the analog front-end circuit and is connected with an input voltage signal Vin-, and the other end of the capacitor C' 1 is connected with an inverse input end of the transconductance amplifier. One end of the capacitor C2 is connected to the positive input terminal of the transconductance amplifier, and the other end is connected to the negative output terminal of the transconductance amplifier. One end of the capacitor C' 2 is connected with the reverse input end of the transconductance amplifier, and the other end is connected with the forward output end of the transconductance amplifier. Pseudo resistance R_pseudoThe terminal a is connected with the positive input end of the transconductance amplifier, and the terminal B is connected with the negative output end of the transconductance amplifier. Pseudo resistance R'_pseudoThe terminal a is connected with the inverting input terminal of the transconductance amplifier, and the terminal B is connected with the forward output terminal of the transconductance amplifier. Capacitor C_LIs connected to the inverting output terminal of the transconductance amplifier and forms the inverting output terminal of the analog front-end circuit, a capacitor C_LThe other end of the connecting rod is connected with the ground end. C 'of capacitor'_LIs connected to the inverting output terminal of the transconductance amplifier and forms the forward output terminal of the analog front-end circuit, a capacitor C'_LThe other end of the connecting rod is connected with the ground end. The types of the capacitors C1 and C '1 are the same, the types of the capacitors C2 and C' 2 are the same, and the capacitor C is_LAnd C'_LAre of the same type, the dummy resistance R_pseudoAnd R'_pseudoThe structure of (a) is completely the same.

The analog front-end circuit of the invention adopts a fully differential structure and is divided into an amplification part, a high-pass part and a low-pass part according to the processing effect of signals: the amplification factor of the amplification part is determined by capacitors C1, C '1, C2 and C' 2, and the capacitor coupling structure circuit is used for determining the amplification factor of a weak signal; the high-pass filtering part is composed of a pseudo resistor R_pseudo、R’_pseudoThe capacitors C2 and C' 2 are realized, and the pseudo-resistor structure and the capacitors form a low cut-off frequency point; the low pass filter part is composed of gm (transconductance) of OTA and capacitor C_L、C’_LImplementation, transconductance amplifierThe transconductance gm of the amplifier and the load capacitance form a high cut-off frequency point.

Through C₁/C₂The ratio of (A) determines the amplification a required for the signal_v：

Since noise is present in the signal, it is necessary to suppress this part of the noise. Pseudo resistance R_pseudoAnd C2 form a low-frequency high-pass pole f_L：

And a pseudo resistance R_pseudoThe resistance value can be varied by adjusting the voltage to achieve a suitably low cut-off frequency. And gm (transconductance) and C of OTA (transconductance amplifier)_LForming a high cut-off frequency point f_H：

At this time, a band-pass filter is formed to achieve the effect of suppressing noise other than the pulse signal.

The analog front-end circuit of the invention has stable closed-loop gain and low noise characteristic. The circuit gain is determined by C1 and C2, and is approximately equal to C1/C2. The input end uses the capacitor C1 as AC coupling to reduce the DC offset voltage from the electrode, the AC coupling structure solves the DC drift problem, and can also reduce the common mode interference and improve the power supply rejection ratio of the circuit. DC feedback via pseudo-resistor R_pseudoProvided that it generates an extremely high resistance value, can provide a stable DC operating point, and a pseudo resistance R_pseudoAnd a low-frequency high-pass pole is formed with the feedback capacitor C2, so that the interference of low-frequency noise can be reduced. The circuit adopts a fully differential form to enhance the power supply rejection ratio and the common mode rejection ratio, thereby reducing the interference of power supply noise and common mode noise. Intermediate frequency gain A of circuit_mAlso determined by C1 and C2:

approximately equal to the ratio of C1 and C2. It is necessary to select a suitable gain for the intermediate frequency of the amplifier, because a lower gain affects the amplification performance of the whole circuit, and an excessively high gain reduces the accuracy of the amplifier.

Structure of the OTA of the invention referring to fig. 2, the circuit comprises: PMOS transistors M1, M2, M7-M14, NMOS transistors M3-M6, resistors Rs1-Rs4, and a current source Ibias. The gate of the PMOS transistor M1 forms the positive input terminal of the transconductance amplifier. The gate of the PMOS transistor M2 forms the inverting input of the transconductance amplifier. The grid and the drain of the PMOS tube M9, the grid of the PMOS tube M10 and one end of the DC power supply Ibias are connected, and the other end of the DC power supply Ibias is grounded. The substrate and the source of the PMOS transistor M2, the source and the substrate of the PMOS transistor M1 and the drain of the PMOS transistor M10 are connected. The grid electrode of the PMOS transistor M7, the grid electrode of the PMOS transistor M8, the substrate and the source electrode of the PMOS transistor M12 and the substrate and the source electrode of the PMOS transistor M13 are connected. The drain and the gate of the PMOS tube M11 are connected with the drain and the gate of the PMOS tube M12. The drain and the gate of the PMOS tube M13 are connected with the drain and the gate of the PMOS tube M14. The drain of the PMOS transistor M1, the drain and the gate of the NMOS transistor M4, and the gate of the NMOS transistor M3 are connected. The drain of the PMOS transistor M2, the drain and the gate of the NMOS transistor M5, and the gate of the NMOS transistor M6 are connected. The substrate and source of PMOS transistor M9, the substrate and source of PMOS transistor M10, the substrate and source of PMOS transistor M7, and the substrate and source of PMOS transistor M8 are connected to voltage VDD. The substrate and source of the PMOS transistor M3 are connected to one end of a resistor Rs 1. The substrate and source of the NMOS transistor M4 are connected to one end of a resistor Rs 2. The substrate and source of the NMOS transistor M5 are connected to one end of a resistor Rs 3. The substrate and source of the PMOS transistor M6 are connected to one end of a resistor Rs 4. The other end of the resistor Rs1-Rs4 is simultaneously grounded. The drain of the NMOS transistor M3, the drain of the NMOS transistor M7, and the substrate and source of the PMOS transistor M11 are connected, and form the positive output terminal Vout + of the transconductance amplifier. The drain of the NMOS transistor M6, the drain of the PMOS transistor M8, and the substrate and source of the PMOS transistor M13 are connected and form the inverting output terminal Vout-of the transconductance amplifier. The model of the PMOS tubes M1 is the same as that of the PMOS tube M2, the model of the NMOS tubes M3, M4, M5 and M6 is the same, the model of the PMOS tubes M7 is the same as that of the PMOS tubes M8, the model of the PMOS tubes M9 is the same as that of the PMOS tubes M10, the model of the PMOS tubes M11, the model of the PMOS tubes M12, the model of the PMOS tubes M13 is the same as that of the PMOS tubes M14, and the model of the resistors Rs1-Rs 4.

The OTA circuit comprises a common mode feedback module and a two-stage amplification module. The common-mode feedback module comprises PMOS tubes M11, M12, M13 and M14; the two-stage amplification module comprises PMOS tubes M1, M2, M9 and M10, NMOS tubes M3, M4, M5 and M6, resistors Rs1-Rs4 and a current source Ibias. The OTA adopts a fully differential structure, the OTA circuit consists of a common-mode feedback circuit and a two-stage amplifier, wherein the common-mode feedback circuit can provide a stable direct current working point, and the amplifying circuit adopts two-stage source follower cascade connection. Since the negative feedback of the differential circuit cannot control the output voltage of the amplifier, an additional common mode feedback circuit is required to stabilize the output dc level of the fully differential amplifier. The circuit uses PMOS tube as input pair, and can reduce flicker noise interference in low frequency band by increasing the area of input pair tubes M1 and M2. By respectively connecting resistors in series at the source ends of the NMOS tubes M3, M4, M5 and M6, the output impedance of the OTA circuit can be improved, the distortion of signals is reduced, the linearity is improved, and the circuit noise is reduced. The input voltage is firstly applied to the gates of the input pair transistors M1 and M2 of the source follower, so that the sources of the PMOS transistors M1 and M2 drive the load, and then the output voltage of the first-stage operational amplifier is used as the input voltage of the second-stage symmetric source follower, wherein most of the voltage of the input voltage drops on the resistor Rs.

Pseudo resistor R of the invention_pseudoAnd R'_pseudoReferring to fig. 3, the circuit includes PMOS transistors M15, M16, M19 and M20, and NMOS transistors M17, M18 and Mc. The grid electrode of the PMOS tube M15, the grid electrode of the PMOS tube M16, the source electrode and the substrate of the NMOS tube M17, the source electrode and the substrate of the NMOS tube M18, the grid electrode of the PMOS tube M19, the grid electrode of the PMOS tube M20 and the drain electrode of the NMOS tube Mc are connected. The drain electrode of the PMOS transistor M15 is connected with the substrate, the gate electrode of the NMOS transistor M18 and the source electrode of the PMOS transistor M19. The drain electrode of the PMOS transistor M16 is connected with the substrate, the gate electrode of the NMOS transistor M17 and the source electrode of the PMOS transistor M20. The source of the PMOS transistor M15 is connected to the source of the PMOS transistor M16. NMOS tube MThe drain of the transistor 17 is connected to the drain of the NMOS transistor M18 and to the voltage VDD. The NMOS transistor Mc is connected with the drain electrode and the voltage VSS. Grid and voltage V of NMOS tube Mc_controlAnd (4) connecting. The substrate and the drain of the PMOS transistor M19 are connected and form the a terminal of the pseudo resistor. The substrate and the drain of the PMOS transistor M20 are connected and form the B terminal of the pseudo resistor. The PMOS tubes M15, M16, M19 and M20 are the same in model, the NMOS tubes M17 and M18 are the same in model, and the resistors Rs1-Rs4 are the same in model.

The important part of the pseudo resistance is the auxiliary circuit, which is used to ensure the MOS transistor to operate in the subthreshold region to obtain a high impedance. The auxiliary circuit of the pseudo resistor shown in fig. 4(a) may be such that the gate is connected to node AB. The auxiliary circuit of the pseudo resistor shown in fig. 4(b) may also be that the gates of two MOS transistors are connected to obtain a constant gate voltage. The pseudo-resistance of FIGS. 4(a) and (b) is at low V_ABCan obtain high impedance, but at high V_ABIn the case of (2), since the PMOS transistor takes carriers, the impedance decreases, thus causing deterioration in linearity.

In order to solve the problems, the invention uses a differential pair transistor as an operating area control circuit, in addition, transistors M19 and M20 are added at two ends of a pseudo resistor, and a node V of the differential pair transistor is used_EIs equal to node V_CAnd V_DMinus V of NMOS tubes M17, M18_GSAverage value of (d):

NMOS transistor M_cAs a current source, from voltage V_controlControl, V_controlThe closer the voltage value of (a) is to the negative voltage VSS, the smaller the current Ic through Mc and the voltage value V_GS3，4Decreasing, causes the impedance of transistors M15, M16 to increase. The structure works in a subthreshold region, and the resistance value can be regulated and controlled from M omega to G omega. Controlling V of MOS transistors with differential pairs_GS. The feasibility of the circuit was verified using the Cadence spectra simulation design environment and tsmc.18um simulation technology parameters.

Based on Cadence spectrum simulation of a 0.18um CMOS process, an input signal has the frequency of 0.5Hz and the amplitude of 0.5mV, wherein a sine wave with the phase of 0 degree is accessed to an input signal end Vin +, and a sine wave with the phase of 180 degrees is accessed to an input signal end Vin-. The circuit was AC analyzed and the simulation results are shown in FIG. 5, varying the impedance of the pseudo-resistor to vary the different low cut-off points f based on different Vcontrol_L. As can be seen from the figure, the voltage Vcontrol changes from-1.65V to-1.3V, the low cut-off frequency point changes from 0.5Hz to 300Hz, the overall power consumption of the circuit is about 3uW, the CMRR is 110dB, and the PSRR is 68 dB. These simulation results demonstrate the effectiveness of the present invention.

It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and thus the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.

Claims

1. An analog front-end circuit suitable for human pulse signals is characterized by comprising capacitors C1, C '1, C2, C' 2 and C_LAnd C'_LPseudo resistance R_pseudoAnd R'_pseudoAnd a transconductance amplifier;

one end of the capacitor C1 forms a forward input end of the analog front-end circuit and is connected with an input voltage signal Vin +, and the other end of the capacitor C1 is connected with a forward input end of the OTA; one end of the capacitor C '1 forms a reverse input end of the analog front-end circuit and is connected with an input voltage signal Vin-, and the other end of the capacitor C' 1 is connected with a reverse input end of the transconductance amplifier;

one end of the capacitor C2 is connected with the positive input end of the transconductance amplifier, and the other end is connected with the reverse output end of the transconductance amplifier; one end of the capacitor C '2 is connected with the reverse input end of the transconductance amplifier, and the other end of the capacitor C' 2 is connected with the forward output end of the transconductance amplifier;

pseudo resistance R_pseudoIs connected with the positive input end of the transconductance amplifierThe B end is connected with the reverse output end of the transconductance amplifier; pseudo resistance R'_pseudoThe A end of the transconductance amplifier is connected with the reverse input end of the transconductance amplifier, and the B end of the transconductance amplifier is connected with the forward output end of the transconductance amplifier;

capacitor C_LIs connected to the inverting output terminal of the transconductance amplifier and forms the inverting output terminal of the analog front-end circuit, a capacitor C_LThe other end of the connecting rod is connected with the ground end; c 'of capacitor'_LIs connected to the inverting output terminal of the transconductance amplifier and forms the forward output terminal of the analog front-end circuit, a capacitor C'_LThe other end of the connecting rod is connected with the ground end.

2. The analog front-end circuit for human pulse signals of claim 1, wherein the capacitors C1 and C '1 are the same type, the capacitors C2 and C' 2 are the same type, and the capacitor C is_LAnd C'_LThe models of the devices are the same.

3. The analog front-end circuit for human pulse signals of claim 1, wherein the pseudo resistor R is a resistor_pseudoAnd R'_pseudoThe structure of (2) is the same.

4. The analog front-end circuit for human pulse signals of claim 3, wherein the pseudo-resistors comprise PMOS transistors M15, M16, M19 and M20, and NMOS transistors M17, M18 and Mc;

the grid electrode of the PMOS tube M15, the grid electrode of the PMOS tube M16, the source electrode and the substrate of the NMOS tube M17, the source electrode and the substrate of the NMOS tube M18, the grid electrode of the PMOS tube M19, the grid electrode of the PMOS tube M20 and the drain electrode of the NMOS tube Mc are connected;

the drain electrode of the PMOS tube M15 is connected with the substrate, the grid electrode of the NMOS tube M18 and the source electrode of the PMOS tube M19; the drain electrode of the PMOS tube M16 is connected with the substrate, the grid electrode of the NMOS tube M17 and the source electrode of the PMOS tube M20;

the source electrode of the PMOS tube M15 is connected with the source electrode of the PMOS tube M16; the drain electrode of the NMOS tube M17 is connected with the drain electrode of the NMOS tube M18 and is connected with a voltage VDD; the NMOS tube Mc substrate is connected with the drain electrode and is connected with a voltage VSS;grid and voltage V of NMOS tube Mc_controlConnecting;

the substrate and the drain of the PMOS tube M19 are connected, and an A end of the pseudo resistor is formed; the substrate and the drain of the PMOS transistor M20 are connected and form the B terminal of the pseudo resistor.

5. The analog front-end circuit for human pulse signals of claim 4, wherein the PMOS transistors M15, M16, M19 and M20 are the same type, and the NMOS transistors M17 and M18 are the same type.

6. The analog front-end circuit of claim 1, wherein the transconductance amplifier comprises PMOS transistors M1, M2, M7-M14, NMOS transistors M3-M6, resistors Rs1-Rs4, and a current source Ibias;

the grid electrode of the PMOS tube M1 forms the positive input end of the transconductance amplifier; the grid electrode of the PMOS tube M2 forms the inverting input end of the transconductance amplifier;

the grid and the drain of the PMOS tube M9, the grid of the PMOS tube M10 and one end of a direct current power supply Ibias are connected, and the other end of the direct current power supply Ibias is grounded; the substrate and the source electrode of the PMOS transistor M2, the source electrode and the substrate of the PMOS transistor M1 and the drain electrode of the PMOS transistor M10 are connected;

the grid electrode of the PMOS tube M7, the grid electrode of the PMOS tube M8, the substrate and the source electrode of the PMOS tube M12 and the substrate and the source electrode of the PMOS tube M13 are connected;

the drain and the gate of the PMOS tube M11 are connected with the drain and the gate of the PMOS tube M12; the drain and the gate of the PMOS tube M13 are connected with the drain and the gate of the PMOS tube M14;

the drain electrode of the PMOS tube M1, the drain electrode and the grid electrode of the NMOS tube M4 and the grid electrode of the NMOS tube M3 are connected; the drain electrode of the PMOS tube M2, the drain electrode and the grid electrode of the NMOS tube M5 and the grid electrode of the NMOS tube M6 are connected;

the substrate and the source of the PMOS transistor M9, the substrate and the source of the PMOS transistor M10, the substrate and the source of the PMOS transistor M7 and the substrate and the source of the PMOS transistor M8 are connected with a voltage VDD;

the substrate and the source of the PMOS transistor M3 are connected with one end of a resistor Rs 1; the substrate and the source of the NMOS tube M4 are connected with one end of a resistor Rs 2; the substrate and the source of the NMOS tube M5 are connected with one end of a resistor Rs 3; the substrate and the source of the PMOS transistor M6 are connected with one end of a resistor Rs 4; the other end of the resistor Rs1-Rs4 is simultaneously grounded;

the drain electrode of the NMOS tube M3, the drain electrode of the NMOS tube M7 and the substrate and the source electrode of the PMOS tube M11 are connected, and a positive output end Vout + of the transconductance amplifier is formed; the drain of the NMOS transistor M6, the drain of the PMOS transistor M8, and the substrate and source of the PMOS transistor M13 are connected and form the inverting output terminal Vout-of the transconductance amplifier.

7. The analog front-end circuit suitable for human pulse signals of claim 6, wherein the PMOS transistors M1 and M2 have the same type, the NMOS transistors M3, M4, M5 and M6 have the same type, the PMOS transistors M7 and M8 have the same type, the PMOS transistors M9 and M10 have the same type, the PMOS transistors M11, M12, M13 and M14 have the same type, and the resistors Rs1-Rs4 have the same type.