CN111341788A - 薄膜晶体管及显示面板 - Google Patents
薄膜晶体管及显示面板 Download PDFInfo
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- CN111341788A CN111341788A CN201911213326.1A CN201911213326A CN111341788A CN 111341788 A CN111341788 A CN 111341788A CN 201911213326 A CN201911213326 A CN 201911213326A CN 111341788 A CN111341788 A CN 111341788A
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Abstract
提供了一种薄膜晶体管和一种显示面板,其中,通过双栅极结构改善了薄膜晶体管的电流特性,并且通过将双栅极的顶栅极(或底栅极)划分为两个电极并向邻近源极区域的顶栅极施加反向偏置电压改善了薄膜晶体管的输出特性。通过使用高度集成的大电流器件增大显示面板的开口率(或透射率)而容易地实现了高分辨率显示面板或透明显示面板。
Description
相关申请的交叉引用
本申请要求2018年12月18日提交的韩国专利申请第10-2018-0163871号的优先权,该申请通过引用并入本文中用于所有目的,如同全文记载于本文中一样。
技术领域
示例性实施例涉及一种薄膜晶体管和一种显示面板。
背景技术
响应于信息社会的发展,对用于显示图像的各种类型的显示装置的要求越来越高。在这方面,诸如液晶显示(LCD)装置和有机发光二极管(OLED)显示装置的一系列显示装置得到了广泛应用。
例如,这种显示装置包括显示面板,多个子像素以矩阵形式设置在显示面板中。显示装置能够通过控制由多个子像素呈现的发光水平来显示图像。此外,发光元件和驱动发光元件的电路元件可以设置在每个子像素中。
在现有显示面板中,可能存在难以使用设置在子像素中的电路元件增大子像素的开口率的问题,因此,实现高分辨率显示装置可能会有很大的困难。
发明内容
示例性实施例的一个目的是改善电流特性,同时减小设置在显示面板的子像素中的薄膜晶体管的尺寸。
示例性实施例的另一个目的是稳定薄膜晶体管的输出特性,同时改善薄膜晶体管的电流特性。
示例性实施例的另一个目的是通过具有高电流特性和提高的可靠性的薄膜晶体管来增大显示面板的开口率(或透射率)。
根据一个方面,示例性实施例可以提供一种薄膜晶体管,所述薄膜晶体管包括:有源层,所述有源层包括源极区域、漏极区域、第一沟道区域和第二沟道区域,所述第一沟道区域和所述第二沟道区域设置在所述源极区域和所述漏极区域之间并且通过作为导电区域的连接图案彼此间隔开;第一栅极,所述第一栅极设置在所述有源层的一个表面上方并对应于所述第一沟道区域的至少一部分和所述第二沟道区域的至少一部分;第二栅极和第三栅极,所述第二栅极和所述第三栅极设置在所述有源层的另一个表面上方并分别对应于所述第一沟道区域和所述第二沟道区域。
在该薄膜晶体管中,当第一栅极电压被施加到所述第一栅极并且第二栅极电压被施加到所述第三栅极时,形成在所述第二沟道区域中的电场增强,并且当反向偏置电压被施加到所述第二栅极时,所述漏极区域的电场分散。
根据另一个方面,示例性实施例可以提供一种显示面板,所述显示面板包括:第一栅极;第一栅极绝缘层,所述第一栅极绝缘层设置在所述第一栅极上方;有源层,所述有源层设置在所述第一栅极绝缘层上方,并包括源极区域、漏极区域、第一沟道区域和第二沟道区域,所述第一沟道区域和所述第二沟道区域设置在所述源极区域和所述漏极区域之间并且通过作为导电区域的连接图案彼此间隔开;第二栅极绝缘层,所述第二栅极绝缘层设置在所述有源层上方;第二栅极,所述第二栅极设置在所述第二栅极绝缘层上方,其中,所述第一栅极和所述第二栅极中的一个被划分为分别对应于所述第一沟道区域和所述第二沟道区域的两个子栅极,所述第一栅极和所述第二栅极中的另一个对应于所述第一沟道区域的至少一部分和所述第二沟道区域的至少一部分。
根据另一个方面,示例性实施例可以提供一种显示面板,所述显示面板包括:有源层,所述有源层包括源极区域、漏极区域、第一沟道区域和第二沟道区域,所述第一沟道区域和所述第二沟道区域设置在所述源极区域和所述漏极区域之间并且位于基板上方;以及顶部栅极,被划分成两个子栅极,所述两个子栅极分开设置于所述有源层上方并且不同电压被施加到所述两个子栅极。。
根据另一个方面,示例性实施例可以提供一种显示面板,所述显示面板包括:有源层,所述有源层包括源极区域、漏极区域、第一沟道区域和第二沟道区域,所述第一沟道区域和所述第二沟道区域设置在所述源极区域和所述漏极区域之间并且位于基板上方;以及底部栅极,被划分成两个子栅极,所述两个子栅极分开设置于所述有源层下方并且不同电压被施加到所述两个子栅极。
根据示例性实施例,能够通过设置在薄膜晶体管上方/下方的双栅极结构来改善薄膜晶体管的电流特性。
根据示例性实施例,能够通过将双栅极的顶栅极(或底栅极)分离为两个电极并向邻近源极区域的顶栅极施加反向偏置电压来改善薄膜晶体管的输出特性。
根据示例性实施例,能够通过使用高度集成的大电流器件增大显示面板的开口率(或透射率)来提高高分辨率显示装置的可靠性。
附图说明
结合附图,将通过以下详细描述更清楚地理解本公开的上述和其他目的、特征及优点,在附图中:
图1示出了根据示例性实施例的显示装置的示意性配置;
图2示出了根据示例性实施例的在显示面板中排列的子像素的电路结构和驱动时序图;
图3和图4示出了根据示例性实施例的在显示面板中排列的子像素的示意性结构;
图5示出了根据示例性实施例的在显示面板中设置的薄膜晶体管的一种结构;
图6示出了根据示例性实施例的在显示面板中设置的薄膜晶体管的另一种结构;
图7示出了根据示例性实施例的在显示面板中设置的薄膜晶体管的再一种结构;
图8A至图8C示出了根据示例性实施例的薄膜晶体管的等效电路的示例;并且
图9示出了根据示例性实施例的改善薄膜晶体管的输出特性的效果。
具体实施方式
在下文中,将详细参考示例性实施例,示例性实施例的示例在附图中示出。在本文件中,应当参考附图,在附图中,相同的附图标记和标号将用于指示相同或相似的组件。在本公开的以下描述中,在本公开的主题可能由于并入本公开中的已知功能和组件的详细描述而变得不清楚的情况下,将省略该已知功能和组件的详细描述。
还应当理解,虽然本文可以使用诸如“第一”、“第二”、“A”、“B”、“(a)”、和“(b)”的术语描述各种元件,但是这些术语仅用于区分一个元件和其他元件。这些元件的实质、序列、顺序或数量不受这些术语的限制。应当理解,当一个元件被称为“连接”、“耦接”或“链接”到另一个元件时,它不仅可以“直接连接、耦接或链接”到另一个元件,而且还可以通过“中间”元件“间接连接、耦接或链接”到另一个元件。
图1示出了根据示例性实施例的显示装置100的示意性配置。
参考图1,根据示例性实施例的显示装置100可以包括包含有源区域A/A和非有源区域N/A的显示面板110,以及用于驱动显示面板110的诸如栅极驱动电路120、数据驱动电路130和控制器140的组件。
在显示面板110中,设置有多条栅极线GL和多条数据线DL,并且多个子像素SP设置在多条栅极线GL和多条数据线DL相交的区域中。多个子像素SP中的每一个可以包括电路元件,并且两个或更多个子像素SP可以提供单个像素。
栅极驱动电路120由控制器140控制,以依次向设置在显示面板110中的多条栅极线GL输出扫描信号,从而控制驱动多个子像素SP的时间点。此外,栅极驱动电路120可以输出发光信号以控制子像素SP的发光时间。可以一体地或分离地设置输出扫描信号的电路和输出发光信号的电路。
栅极驱动电路120可以包括一个或多个栅极驱动集成电路(IC)。根据驱动***,栅极驱动电路120可以设置在显示面板110的一侧或两侧上。
每个栅极驱动IC可以通过带载自动封装(TAB)方法或玻璃上芯片(COG)方法连接到显示面板110的接合焊盘,可以使用直接设置在显示面板110中的面板内栅极(GIP)结构实现,或者在某些情况下,可以与显示面板110集成。或者,每个栅极驱动IC可以使用安装在连接到显示面板110的薄膜上方的膜上芯片(COF)结构实现。
数据驱动电路130从控制器140接收图像数据,并且将图像数据转换为模拟数据电压。此外,数据驱动电路130在通过栅极线GL施加扫描信号的时间点分别向数据线DL输出数据电压,使得子像素SP呈现出与图像数据相对应的发光强度。
数据驱动电路130可以包括一个或多个源极驱动IC,并且每个源极驱动IC可以包括移位寄存器、锁存电路、数模转换器(DAC)、输出缓冲器等。
每个源极驱动IC可以通过带载自动封装(TAB)方法或通过玻璃上芯片(COG)方法连接到显示面板110的接合焊盘,可以直接安装在显示面板110上方,或者在某些情况下,可以与显示面板110集成。此外,每个源极驱动IC可以使用安装在连接到显示面板110的薄膜上方的膜上芯片(COF)结构实现。在这种情况下,每个源极驱动IC可以安装在连接到显示面板110的薄膜上方,并且可以通过薄膜上方的线路电连接到显示面板110。
控制器140向栅极驱动电路120和数据驱动电路130供应各种控制信号,以控制栅极驱动电路120和数据驱动电路130的操作。
控制器140控制栅极驱动电路120,以在由帧定义的时间点输出扫描信号。控制器140将从外部源接收的图像数据转换为数据驱动电路130可读取的数据信号格式,并且将所转换的图像数据输出到数据驱动电路130。
控制器140从外部源(例如,主机***)除了接收图像数据之外,还接收包括垂直同步信号Vsync、水平同步信号Hsync、输入数据使能(DE)信号、时钟(CLK)信号等的各种时序信号。
控制器140可以使用从外部源接收的各种时序信号生成各种控制信号,并且将控制信号输出到栅极驱动电路120和数据驱动电路130。
例如,控制器140输出包括栅极起始脉冲(GSP)信号、栅极移位时钟(GSC)信号、栅极输出使能(GOE)信号等的各种栅极控制信号GCS,以控制栅极驱动电路120。
这里,栅极起始脉冲控制栅极驱动电路120的一个或多个栅极驱动IC的操作起始时间。栅极移位时钟是通常输入到一个或多个栅极驱动IC以控制扫描信号的移位时间的时钟信号。栅极输出使能信号指示一个或多个栅极驱动IC的时序信息。
此外,控制器140输出包括源极起始脉冲(SSP)信号、源极采样时钟(SSC)信号、源极输出使能(SOE)信号等的各种数据控制信号DCS,以控制数据驱动电路130。
这里,源极起始脉冲控制数据驱动电路130的一个或多个源极驱动IC的数据采样起始时间。源极采样时钟是控制每个源极驱动IC中的数据的采样时间的时钟信号。源极输出使能信号控制数据驱动电路130的输出时间。
显示装置100还可以包括电力管理集成电路(PMIC),以向显示面板110、栅极驱动电路120、数据驱动电路130等供应各种形式的电压或电流,或者控制向显示面板110、栅极驱动电路120、数据驱动电路130等供应的各种形式的电压或电流。
此外,除栅极线GL和数据线DL之外,供应各种信号或电压的信号线或电压线也可以设置在显示面板110中。
此外,每个子像素SP可以容纳用于驱动子像素的多个电路元件。
图2示出了根据示例性实施例的设置在显示面板110中的子像素SP的电路结构和驱动时序图。
参考图2,多个晶体管T1、T2、T3、T4、T5和T6、电容器Cst以及发光元件EL可以设置在子像素SP中。
也就是说,图2示出了设置有六个晶体管T1、T2、T3、T4、T5和T6以及一个电容器Cst的6T1C结构。然而,构成子像素SP的电路元件可以根据显示装置100(即,显示装置100的类型或配置)进行不同的设置。
此外,虽然图示为设置在子像素SP中的晶体管T1、T2、T3、T4、T5和T6是p型晶体管,但是在某些情况下,这些晶体管可以设置为n型晶体管。
第一晶体管T1由第一扫描信号SCAN1控制并且控制向第一节点N1施加数据电压Vdata。这种第一晶体管T1可以称为“开关晶体管”。
第二晶体管T2由第二节点N2的电压控制并且控制驱动电压VDD的供应。这里,驱动电压VDD可以是驱动子像素SP的高电位电压。这种第二晶体管T2可以称为“驱动晶体管”。
第三晶体管T3由第二扫描信号SCAN2控制并且电连接在第二节点N2和第三节点N3之间。这种第三晶体管T3可以称为“补偿晶体管”。
第四晶体管T4由发光信号EM控制并且控制施加到第一节点N1的基准电压Vref。这种第四晶体管T4可以称为“第一发光晶体管”。
第五晶体管T5由发光信号EM控制并且电连接在第三节点N3和第四节点N4之间。这种第五晶体管T5可以称为“第二发光晶体管”。
第六晶体管T6由第二扫描信号SCAN2控制并且控制施加到第四节点N4的基准电压Vref。这种第六晶体管T6可以称为“初始化晶体管”。
电容器Cst可以电连接在第一节点N1和第二节点N2之间,并且可以在发光元件EL发光的时段期间保持数据电压Vdata。
例如,发光元件EL可以是有机发光二极管(OLED),在该有机发光二极管(OLED)中,阳极连接到第四节点N4,并且基电压VSS被施加到阴极。这里,基电压VSS可以是驱动子像素SP的低电位电压。
参考图2所示的驱动时序,当发光信号EM在第一时段P1中处于低电平时,可以以低电平施加第二扫描信号SCAN2。
因此,在第四晶体管T4和第五晶体管T5导通的状态下,第三晶体管T3和第六晶体管T6可以导通。第一节点N1、第二节点N2、第三节点N3和第四节点N4可以初始化到基准电压Vref。
在第二时段P2中,可以在第二扫描信号SCAN2处于低电平的同时施加具有低电平的第一扫描信号SCAN1和具有高电平的发光信号EM。
因此,可以导通第一晶体管T1,并且可以关断第四晶体管T4和第五晶体管T5。
此外,数据电压Vdata可以施加到第一节点N1,并且通过从驱动电压VDD减去第二晶体管T2的阈值电压而获得的电压可以施加到第二节点N2。在第二时段P2中,第一晶体管导通。因此,可以将数据电压Vdata施加到第一节点N1。并且,在第二时段P2中,由于第二扫描信号SCAN2处于低电平,从而第三晶体管T3和第六晶体管T6导通。因此,第二节点N2和第三节点N3电连接。因此,第二晶体管T2可以像二极管一样被驱动。因此,驱动电压VDD可以通过第三节点N3施加到第二节点N2。此时,可以将电压(驱动电压VDD-第二晶体管T2的阈值电压Vth)施加到第二节点N2。也就是说,可以在第二时段P2中执行数据电压Vdata的施加和第二晶体管T2的阈值电压补偿。
在第三时段P3中,可以在发光信号EM处于高电平的同时施加具有高电平的第一扫描信号SCAN1和第二扫描信号SCAN2。因此,第一节点N1和第二节点N2可能浮动。由于第一晶体管T1截止,第一节点N1可能浮动。由于第三晶体管T3截止,第二节点N2可能浮动。
在第四时段P4中,可以在第一扫描信号SCAN1和第二扫描信号SCAN2处于高电平的状态下施加具有低电平的发光信号EM。
因此,第四晶体管T4和第五晶体管T5导通,并且与数据电压Vdata相对应的电流被供应到发光元件EL,使得发光元件EL能够发射具有与数据电压Vdata相对应的发光强度的光。由于第四晶体管T4导通,第一节点N1可以放电。并且,可以根据第一节点N1的电压电平的变化来改变第二节点N2的电压电平(即,第二节点N2的电压电平的变化取决于作为第一节点N1的电压电平的数据电压Vdata)。当第二节点N2的电压电平变化时,第二晶体管T2可以导通。电流可以流经第二晶体管T2,并且电流可以对应于第二节点N2的电压电平的变化。即,电流可以对应于施加到第一节点N1的数据电压Vdata。并且,由于第五晶体管导通,发光元件EL可以根据流经第二晶体管T2的电流发光。
这种子像素SP可以划分为设置有上述电路元件等的区域以及通过发光元件EL发光的区域。
图3和图4示出了根据示例性实施例的设置在显示面板110中的子像素SP的示意性结构。
参考图3,根据示例性实施例的在显示面板110中排列的每个子像素SP包括非透明区和透明区,非透明区为设置有用于驱动子像素SP的多个电路元件的电路区域CA,透明区为呈现出与图像数据相对应的亮度的发光区域EA。
电路区域CA可以是不开放的区域,以防止设置在电路区域CA中的电路元件等被外部光等损坏。
发光区域EA可以是上方显示与子像素SP的驱动相对应的图像的开放区域。
电路区域CA和发光区域EA可以在子像素SP中设置为彼此不重叠。
这里,发光区域EA在子像素SP中占据的面积的比例越高,子像素SP呈现的图像的质量会越好。因此,有必要增大子像素SP的开口率。
此外,在根据示例性实施例的显示装置100是透明显示装置100的情况下,透明区域TA可以设置在子像素SP中,以便增大显示面板110的透明度。
参考图4,子像素SP可以包括设置有电路元件的电路区域CA、指示与图像数据相对应的发光强度的发光区域EA、以及透明区域TA。
这里,电路区域CA和发光区域EA可以设置为彼此重叠。
子像素SP中除电路区域CA和发光区域EA之外的区域可以是透明区域TA。
因此,可以通过在子像素SP中设置透明区域TA来实现透明显示装置100。
如上所述,当显示装置100是透明的时,有必要增大透明区域TA在子像素中设置的比例,以便增大显示装置100的透明度。
也就是说,有必要最小化电路区域CA的比例,以便增大显示面板110的开口率或透明度。
示例性实施例提供了一种通过将设置在子像素SP的电路区域CA中的薄膜晶体管配置为高度集成的大电流器件来增大显示面板110的开口率或透明度的方法。
图5示出了根据示例性实施例的在显示面板110中设置的薄膜晶体管。
参考图5,缓冲层BUF可以设置在基板SUB上方,并且第一栅极GE1可以设置在缓冲层BUF上方。
第一栅极绝缘层GI1可以设置在第一栅极GE1上方,并且有源层ACT可以设置在第一栅极绝缘层GI1上方。
该有源层ACT包括p+(或n+)掺杂源极区域SE和漏极区域DE,并且可以包括第一沟道区域CH1和第二沟道区域CH2,第一沟道区域CH1和第二沟道区域CH2设置在源极区域SE和漏极区域DE之间并且通过导电区域间隔开。
设置在第一沟道区域CH1和第二沟道区域CH2之间的导电区域可以在对源极区域SE和漏极区域DE进行掺杂的工艺中形成。这种导电区域可以称为“连接图案CP”。
第一沟道区域CH1的长度L1和第二沟道区域CH2的长度L2可以是相同的。
第二栅极绝缘层GI2可以设置在有源层ACT上方,第二栅极GE2和第三栅极GE3可以设置在第二栅极绝缘层GI2上方。层间介电层ILD可以设置在第二栅极GE2和第三栅极GE3上方。
第二栅极GE2和第三栅极GE3可以设置为彼此间隔开。
第二栅极GE2可以设置为对应于第一沟道区域CH1,并且第三栅极GE3可以设置为对应于第二沟道区域CH2。
这里,虽然已经示出了使得设置在有源层ACT上方的栅极被划分为两个栅极GE2和GE3的结构,但是根据需要,可以设置使得设置在有源层ACT下方的栅极被划分为两个栅极的结构。
也就是说,两个栅极可以设置在有源层ACT的底面下方以分别对应于第一沟道区域CH1和第二沟道区域CH2,并且一个栅极可以设置在有源层ACT上方以对应于第一沟道区域CH1和第二沟道区域CH2。
例如,薄膜晶体管可以是驱动设置在显示面板110的子像素SP中的发光元件EL的驱动晶体管。也就是说,根据示例性实施例的薄膜晶体管的源极区域SE或漏极区域DE可以电连接到设置在子像素SP中的发光元件EL的阳极。在某些情况下,根据示例性实施例的薄膜晶体管可以是设置在子像素SP中的除驱动晶体管之外的薄膜晶体管,或者可以是包含在驱动电路中的薄膜晶体管。
参考图5所示结构中的薄膜晶体管的驱动方法,第一栅极电压VG1可以施加到设置在有源层ACT下的第一栅极GE1。
由于第一栅极GE1被设置为对应于第一沟道区域CH1和第二沟道区域CH2,所以当第一栅极电压VG1被施加到第一栅极GE1时,沟道形成在第一沟道区域CH1和第二沟道区域CH2中,使得载流子能够从源极区域SE移动到漏极区域DE。
这里,虽然已经示出了使得第一栅极GE1也设置在连接图案CP下的结构,但是根据需要,第一栅极GE1可以具有使得第一栅极被设置为仅对应于第一沟道区域CH1和第二沟道区域CH2的U形平面结构。也就是说,在某些情况下,第一栅极GE1可以设置为与连接图案CP的至少一部分不重叠。
然后,第二栅极电压VG2被施加到第三栅极GE3,该第三栅极GE3设置在有源层ACT上方以对应于第二沟道区域CH2并且邻近漏极区域DE。
当第二栅极电压VG2被施加到设置为与第二沟道区域CH2相对应的第三栅极GE3时,可以增加从源极区域SE移动到漏极区域DE的载流子的量,使得能够改善薄膜晶体管的电流特性。
第二栅极电压VG2可以与第一栅极电压VG1相同。或者,第二栅极电压VG2可以是不同于第一栅极电压VG1的电压。
也就是说,根据设置在第一栅极GE1和有源层ACT之间的第一栅极绝缘层GI1的厚度以及设置在有源层ACT和第三栅极GE3之间的第二栅极绝缘层GI2的厚度,第一栅极电压VG1和第二栅极电压VG2可以是相同的或者可以是彼此不同的。
或者,第一栅极电压VG1和第二栅极电压VG2可以不同地施加以控制薄膜晶体管的电流特性。
如上所述,当栅极电压VG被施加到设置在有源层ACT下的第一栅极GE1和设置在有源层ACT上的第三栅极GE3时,能够增强形成在第二沟道区域CH2中的电场,以增加从源极区域SE移动到漏极区域DE的载流子的量。
因此,能够在减小薄膜晶体管的尺寸的同时改善薄膜晶体管的电流特性。
然后,反向偏置电压Bbias可以施加到第二栅极GE2,该第二栅极GE2设置在有源层ACT上方并且邻近源极区域SE以对应于第一沟道区域CH1。
反向偏置电压Bbias可以是与第一栅极电压VG1和第二栅极电压VG2不同的恒定电压。例如,当薄膜晶体管是n型晶体管时,第一栅极电压VG1和第二栅极电压VG2可以是5V,反向偏置电压Bbias可以是0V。或者,当薄膜晶体管是p型晶体管时,第一栅极电压VG1和第二栅极电压VG2可以是-5V,反向偏置电压Bbias可以是0V。也就是说,反向偏置电压Bbias可以是低于第一栅极电压VG1和第二栅极电压VG2的绝对值的恒定电压。然而,这种情况仅仅是示例,并且根据示例性实施例的施加到薄膜晶体管的栅极电压VG和反向偏置电压Bbias不限于上述示例。反向偏置电压可以是大于或小于0V的电压。也就是说,反向偏置电压可以是与栅极电压不同的恒定电压。然而,优选的是,由于反向偏置电压不是用于驱动薄膜晶体管的电压,从而反向偏置电压的绝对值小于栅极电压的绝对值。
当反向偏置电压Bbias被施加到设置为与第一沟道区域CH1相对应的第二栅极GE2时,漏极区域DE的电场被分散,使得薄膜晶体管输出的电流能够稳定地输出。
也就是说,可以通过第一栅极GE1和设置为与第二沟道区域CH2相对应的第三栅极GE3增加薄膜晶体管输出的电流,并且可以通过设置为与第一沟道区域CH1相对应的第二栅极GE2稳定电场。
因此,可以在减小薄膜晶体管的尺寸的同时输出大电流,以减小翘曲效应(Kinkeffect),从而改善薄膜晶体管的输出特性。
可以通过调整设置在第一栅极GE1上方的第一栅极绝缘层GI1的厚度和设置在第二栅极GE2下方的第二栅极绝缘层GI2的厚度来控制薄膜晶体管的特性。
例如,能够通过使第一栅极绝缘层GI1的厚度小于第二栅极绝缘层GI2的厚度来增大薄膜晶体管的S因数(S-factor)的斜率。或者,能够通过使设置在施加了反向偏置电压Bbias的第二栅极GE2下的第二栅极绝缘层GI2的厚度小于第一栅极绝缘层GI1的厚度来减小S因数的斜率。
如上所述,由于薄膜晶体管包括施加了反向偏置电压Bbias的第二栅极GE2,所以能够通过执行第一栅绝缘层GI1和第二栅绝缘层GI2的厚度调整来实现具有各种特性的薄膜晶体管。
这里,如图5所示,第一栅极GE1两侧的边界可以设置为与第一沟道区域CH1的外边界以及第二沟道区域CH2的外边界对齐。然而,在某些情况下,该边界可以设置在第一沟道区域CH1和第二沟道区域CH2的外边界内侧,以调整电场。
图6示出了根据示例性实施例的设置在显示面板110中的薄膜晶体管的另一种结构。
参考图6,缓冲层BUF设置在基板SUB上方,第一栅极GE1设置在缓冲层BUF上方。第一栅极绝缘层GI1设置在第一栅极GE1上方。
具有源极区域SE、第一沟道区域CH1、连接图案CP、第二沟道区域CH2和漏极区域DE的有源层ACT设置在第一栅极绝缘层GI1上方。
第二栅极绝缘层GI2设置在有源层ACT上方。
在第二栅极绝缘层GI2上,第二栅极GE2可以设置在对应于第一沟道区域CH1的区域中,并且第三栅极GE3可以设置在对应于第二沟道区域CH2的区域中。
这里,设置在有源层ACT下的第一栅极GE1可以设置为对应于第一沟道区域CH1的至少一部分和第二沟道区域CH2的至少一部分。
此时,第一栅极GE1的两个边界中的至少一个可以位于第一沟道区域CH1和第二沟道区域CH2的外边界内侧。即,第一沟道区域CH1和第二沟道区域CH2的至少一个延伸超过第一栅极GE1,以具有与第一栅极GE1不重叠的部分。
例如,第一栅极GE1的两个边界中的邻近源极区域SE的一个边界可以位于从第一沟道区域CH1的外边界向内距离D1的位置处。
或者,第一栅极GE1的两个边界中的邻近漏极区域DE的另一个边界可以位于从第二沟道区域CH2的外边界向内距离D2的位置处。
此外,如图6所示,第一栅极GE1的两个边界可以分别位于第一沟道区域CH1和第二沟道区域CH2的外边界内侧。
设置在有源层ACT上方的第二栅极GE2和第三栅极GE3可以设置为分别与第一沟道区域CH1和第二沟道区域CH2的边界对齐。
也就是说,第一栅极GE1的两个边界可以位于第二栅极GE2和第三栅极GE3的外边界内侧,使得能够调整漏极区域DE的电场。
根据有源层ACT中的漏极区域DE的掺杂结构,第一栅极GE1的边界可以位于第三栅极GE3的外边界外侧。
图7示出了根据示例性实施例的设置在显示面板110中的薄膜晶体管的再一种结构。
参考图7,第一栅极GE1设置在有源层ACT下,以对应于第一沟道区域CH1和第二沟道区域CH2。
在有源层ACT上,第二栅极GE2设置为对应于第一沟道区域CH1,并且第三栅极GE3设置为对应于第二沟道区域CH2。
这里,轻掺杂漏极区域LDD可以设置在有源层ACT中并邻近漏极区域DE以减少漏电流。
由于轻掺杂漏极区域LDD设置在邻近漏极区域DE的区域中,所以第一栅极GE1可以与轻掺杂漏极区域LDD的至少一部分重叠。
因此,第一栅极GE1的两个边界中的邻近漏极区域DE的一个边界可以位于从第三栅极GE3的外边界向外距离D3的位置处。即,第一栅极GE1和漏极区域DE之间的水平距离D4小于第三栅极GE3和漏极区域DE之间的水平距离(D3+D4)。
这里,第一栅极GE1的该边界可以位于从漏极区域DE向内距离D4的位置处。换句话说,第一栅极GE1可以位于第三栅极GE3外侧同时位于漏极区域DE内侧。
图8A至图8C示出了根据示例性实施例的薄膜晶体管的等效电路的示例。
参考图8A,根据示例性实施例的薄膜晶体管可以包括施加了第一栅极电压VG1的第一栅极GE1、施加了反向偏置电压Bbias的第二栅极GE2以及施加了第二栅极电压VG2的第三栅极GE3。
这里,根据栅极绝缘层GI的厚度、薄膜晶体管的电流特性等,第一栅极电压VG1和第二栅极电压VG2可以是相同的电压,或者可以是不同的电压。
反向偏置电压Bbias可以是不同于第一栅极电压VG1和第二栅极电压VG2的电压,并且可以是恒定电压。例如,如上所述,反向偏置电压Bbias可以是小于第一栅极电压VG1和第二栅极电压VG2的绝对值的恒定值(例如,0V)。
由于栅极电压VG被施加到薄膜晶体管的第一栅极GE1和第三栅极GE3,所以可以增强施加到第二沟道区域CH2的电场,从而改善薄膜晶体管的电流特性。
此外,由于反向偏置电压Bbias被施加到设置为与有源层ACT的第一沟道区域CH1相对应的第二栅极GE2,所以漏极区域DE的电场被分散,使得能够稳定薄膜晶体管的输出特性。
这里,当施加到第一栅极GE1的第一栅极电压VG1和施加到第三栅极GE3的第二栅极电压VG2彼此相等时,第一栅极GE1和第三栅极GE3可以电连接。
参考图8B,根据示例性实施例的薄膜晶体管可以包括第一栅极GE1、第二栅极GE2和第三栅极GE3。
这里,第一栅极GE1和第三栅极GE3可以彼此电连接,并且栅极电压VG可以施加到第一栅极GE1和第三栅极GE3。
当栅极电压VG被施加到设置在有源层ACT两侧上方的第一栅极GE1和第三栅极GE3时,电场增强以改善薄膜晶体管的电流特性。
此外,通过使反向偏置电压Bbias施加到第二栅极GE2,可以在提供薄膜晶体管的高电流特性的同时稳定薄膜晶体管的输出特性。
这里,施加了反向偏置电压Bbias的第二栅极GE2在某些情况下可以电连接到源极区域SE。
参考图8C,能够通过使第一栅极电压VG1施加到第一栅极GE1并且将第二栅极电压VG2施加到第三栅极GE3来改善薄膜晶体管的电流特性。
第二栅极GE2可以电连接到源极区域SE。也就是说,第二栅极GE2可以在不设置将反向偏置电压Bbias施加到第二栅极GE2的单独线路的情况下电连接到源极区域SE,并且漏极区域DE的电场可以被分散,使得能够稳定薄膜晶体管的输出特性。
图9示出了根据示例性实施例的改善薄膜晶体管的输出特性的效果。
参考图9,如上方的图所示,在薄膜晶体管设置有双栅极结构以改善薄膜晶体管的电流特性的情况下,可能会发生漏极区域DE的输出特性随着栅极电压VGa、VGb和VGc增大而迅速增强的翘曲效应。
相反,如下方的图所示,如示例性实施例的在设置在有源层ACT顶部(或底部)的顶栅极被设置为划分为第二栅极GE2和第三栅极GE3,并且反向偏置电压Bbias被施加到第二栅极GE2的情况下,能够看出,漏极区域DE的输出特性即使在栅极电压VGa、VGb和VGc增大时也是恒定的。
根据如上所述的示例性实施例,由于施加了反向偏置电压Bbias的栅极设置在具有多栅极结构的薄膜晶体管中,所以能够改善薄膜晶体管的电流特性。
因此,可以在减小薄膜晶体管的尺寸的同时提供具有改善的电流特性和可靠性的薄膜晶体管。
此外,能够通过利用上述高度集成的大电流器件驱动子像素SP来增大子像素SP的开口率或透射率,使得能够实现高分辨率显示面板110或透明显示面板110。
提供上述描述和附图以举例说明本公开的特定原理。本公开相关领域技术人员能够在不背离本公开的原理的情况下进行各种修改和变更。本文所公开的上述实施例应当解释为说明本公开的原理和范围,而不是限制本公开的原理和范围。应当理解,本公开的范围应当由所附权利要求书限定,并且其所有等同物均落入本公开的范围内。
Claims (20)
1.一种薄膜晶体管,包括:
有源层,所述有源层包括源极区域、漏极区域、第一沟道区域和第二沟道区域,所述第一沟道区域和所述第二沟道区域设置在所述源极区域和所述漏极区域之间并且通过作为导电区域的连接图案彼此间隔开;
第一栅极,所述第一栅极设置在所述有源层的一个表面上方并对应于所述第一沟道区域的至少一部分和所述第二沟道区域的至少一部分;以及
第二栅极和第三栅极,所述第二栅极和所述第三栅极设置在所述有源层的另一个表面上方并分别对应于所述第一沟道区域和所述第二沟道区域。
2.根据权利要求1所述的薄膜晶体管,其中,当第一栅极电压被施加到所述第一栅极并且第二栅极电压被施加到所述第三栅极时,形成在所述第二沟道区域中的电场增强,并且
当反向偏置电压被施加到所述第二栅极时,所述漏极区域的电场分散。
3.根据权利要求2所述的薄膜晶体管,其中,所述第一栅极电压和所述第二栅极电压相同,并且所述反向偏置电压是与所述第一栅极电压和所述第二栅极电压不同的恒定电压。
4.根据权利要求3所述的薄膜晶体管,其中,所述反向偏置电压是低于所述第一栅极电压的绝对值和所述第二栅极电压的绝对值的恒定电压。
5.根据权利要求1所述的薄膜晶体管,其中,所述第一栅极和所述第三栅极彼此电连接,并且所述第二栅极和所述源极区域彼此电连接。
6.根据权利要求1所述的薄膜晶体管,其中,所述第一栅极的两个边界被设置为分别与所述第一沟道区域的外边界以及所述第二沟道区域的外边界对齐。
7.根据权利要求1所述的薄膜晶体管,其中,所述第一栅极的两个边界中的至少一个边界位于比所述第一沟道区域的外边界和所述第二沟道区域的外边界更为内侧的位置,或者
其中,所述第一栅极的两个边界中的至少一个位于比所述第二栅极的外边界和所述第三栅极的外边界更为外侧的位置。
8.根据权利要求7所述的薄膜晶体管,其中,所述有源层中的与所述第一栅极的所述边界和所述第三栅极的所述外边界之间的区域相对应的区域是轻掺杂漏极区域。
9.根据权利要求1所述的薄膜晶体管,其中,所述第一沟道区域的长度等于所述第二沟道区域的长度,并且所述第二栅极和所述第三栅极设置在同一层中。
10.根据权利要求2所述的薄膜晶体管,其中,所述反向偏置电压与所述第二栅极电压在不同的时段施加。
11.根据权利要求2所述的薄膜晶体管,其中,所述第一栅极电压、所述第二栅极电压以及所述反向偏置电压依次施加。
12.一种显示面板,包括:
第一栅极;
第一栅极绝缘层,所述第一栅极绝缘层设置在所述第一栅极上方;
有源层,所述有源层设置在所述第一栅极绝缘层上方,并包括源极区域、漏极区域、第一沟道区域和第二沟道区域,所述第一沟道区域和所述第二沟道区域设置在所述源极区域和所述漏极区域之间并且通过作为导电区域的连接图案彼此间隔开;
第二栅极绝缘层,所述第二栅极绝缘层设置在所述有源层上方;以及
第二栅极,所述第二栅极设置在所述第二栅极绝缘层上方,
其中,所述第一栅极和所述第二栅极中的一个被划分为分别对应于所述第一沟道区域和所述第二沟道区域的两个子栅极,所述第一栅极和所述第二栅极中的另一个对应于所述第一沟道区域的至少一部分和所述第二沟道区域的至少一部分。
13.根据权利要求12所述的显示面板,其中,第一栅极电压被施加到所述第一栅极和所述第二栅极中的所述另一个,并且,第二栅极电压被施加到一个子栅极,并且反向偏置电压被施加到另一个子栅极,
其中,所述反向偏置电压与所述第二栅极电压在不同的时段施加。
14.根据权利要求12所述的显示面板,
其中,第一栅极电压被施加到所述第一栅极和所述第二栅极中的所述另一个,并且,第二栅极电压被施加到一个子栅极,并且反向偏置电压被施加到另一个子栅极,
其中,所述第一栅极电压、所述第二栅极电压以及所述反向偏置电压依次施加。
15.根据权利要求12所述的显示面板,包括多个子像素,
其中,所述多个子像素的每个子像素包括发光元件和用于驱动所述发光元件的驱动晶体管,
其中,所述驱动晶体管包括所述第一栅极、所述第一栅极绝缘层、所述有源层、所述第二栅极绝缘层以及所述第二栅极。
16.根据权利要求12所述的显示面板,其中,所述显示面板包括透明区和非透明区。
17.一种显示面板,包括:
有源层,所述有源层包括源极区域、漏极区域、第一沟道区域和第二沟道区域,所述第一沟道区域和所述第二沟道区域设置在所述源极区域和所述漏极区域之间并且位于基板上方;以及
顶部栅极,被划分成两个子栅极,所述两个子栅极分开设置于所述有源层上方并且不同的电压被施加到所述两个子栅极。
18.根据权利要求17所述的显示面板,其中,电压在不同的时段被施加在所述两个子栅极上。
19.根据权利要求17所述的显示面板,其中,所述显示面板包括透明区和非透明区。
20.根据权利要求17所述的显示面板,进一步包括:
底部栅极,被划分成两个子栅极,所述两个子栅极分开设置于所述有源层下方,并且不同的电压被施加到所述两个子栅极。
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