CN111258363B - Ultra-low power consumption reference circuit and sampling method thereof - Google Patents

Ultra-low power consumption reference circuit and sampling method thereof Download PDF

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CN111258363B
CN111258363B CN202010094479.5A CN202010094479A CN111258363B CN 111258363 B CN111258363 B CN 111258363B CN 202010094479 A CN202010094479 A CN 202010094479A CN 111258363 B CN111258363 B CN 111258363B
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transistor
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input signal
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clock input
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CN111258363A (en
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刘帘曦
云梦晗
黄文斌
邢奕赫
朱樟明
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Xidian University
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Xidian University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L5/00—Automatic control of voltage, current, or power

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Abstract

The invention discloses an ultra-low power consumption reference circuit and a sampling method thereof, wherein the ultra-low power consumption reference circuit comprises: the band-gap reference module is used for generating a first self-starting voltage, a second self-starting voltage and a reference voltage according to a first clock input signal; the first self-starting module is used for providing a first self-starting voltage for the band gap reference module according to a first clock input signal; the second self-starting module is used for providing a second self-starting voltage for the band gap reference module according to the first clock input signal; and the sampling and holding module is used for sampling and holding the reference voltage according to the second clock input signal and the third clock input signal to obtain an output signal. According to the ultra-low power consumption reference circuit, the first self-starting module, the second self-starting module and the sampling and holding module are additionally arranged on the periphery of the band gap reference module, so that the band gap reference module intermittently works, the power consumption of the reference circuit is greatly reduced, and meanwhile, the good stability of the output voltage is kept.

Description

Ultra-low power consumption reference circuit and sampling method thereof
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to an ultra-low power consumption reference circuit and a sampling method thereof.
Background
In the applications of the internet of things and most wireless communication, low power consumption is required for related receiving circuits or transmitting circuits, and therefore, a reference circuit capable of generating low power consumption is very critical and essential for the whole application.
The low-power reference circuit is an important part of an analog circuit and generally needs to normally work within a wider temperature range, so that the low-power reference circuit not only requires low power consumption, but also needs stable performance and better temperature characteristic, and simultaneously requires fine adjustment of the amplitude of the output reference voltage according to actual requirements. In order to obtain a low-power-consumption reference, a conventional bandgap reference circuit based on BJT transistors can provide a stable reference voltage at a level of μ a, and in order to implement a voltage reference at a level of nA in the prior art, MOS transistors in the bandgap reference circuit are mostly operated in a sub-threshold region to generate the voltage reference.
However, the low-power reference structure based on the MOS transistor is sensitive to process parameters and temperature, the application environment is limited, and the voltage reference robustness is extremely poor and the performance is unstable.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an ultra-low power consumption reference circuit and a sampling method thereof.
The invention provides an ultra-low power consumption reference circuit, which comprises a band gap reference module, a first self-starting module, a second self-starting module and a sampling and holding module, wherein,
the band-gap reference module is used for generating a first self-starting voltage, a second self-starting voltage and a reference voltage according to a first clock input signal;
the first self-starting module is connected with the band-gap reference module and used for providing a first self-starting voltage for the band-gap reference module according to the first clock input signal;
the second self-starting module is connected with the band-gap reference module and used for providing a second self-starting voltage for the band-gap reference module according to the first clock input signal;
and the sampling and holding module is connected with the band-gap reference module and is used for sampling and holding the reference voltage according to a second clock input signal and a third clock input signal to obtain an output signal.
In one embodiment of the present invention, the first self-starting module comprises an inverter INV1Transistor M1Transistor M3And a capacitor C1Wherein, in the step (A),
the inverter INV1Of the transistor M3The grid of the inverter INV is connected with the first clock signal input end1And the transistor M1Gate of (1), the transistor M2Of the transistor M, the transistor M1Is connected with a first output terminal of the band-gap reference module, the transistor M1And the transistor M2The drain electrode ofTransistor M3Of said transistor M, said transistor M2Source electrode of, the transistor M3And the capacitor C1Is connected to the capacitor C1And the other end of the same is grounded.
In one embodiment of the present invention, the second self-starting module comprises an inverter INV2Transistor M4Transistor M6And a capacitor C2Wherein, in the step (A),
the inverter INV2Of the transistor M6The grid of the inverter INV is connected with the first clock signal input end2And the transistor M4Gate of (1), the transistor M5Of the transistor M, the transistor M4Is connected with a second output terminal of the bandgap reference module, the transistor M4And the transistor M5Drain electrode of, the transistor M6Of said transistor M, said transistor M5Source electrode of, the transistor M6And the capacitor C2Is connected to the capacitor C2And the other end of the same is grounded.
In one embodiment of the invention, the sample and hold module comprises a unity gain module, a first switching module, a second switching module, and a third switching module, wherein,
the first switch module is connected with the band-gap reference module and is used for carrying out first switch sampling and holding processing on the reference voltage according to the second clock input signal and the third clock input signal to obtain a first switch sampling and holding signal;
the second switch module is connected with the first switch module and is used for performing second switch sampling and holding processing on the first switch sampling and holding signal according to the second clock input signal and the third clock input signal to obtain a second switch sampling and holding signal;
the unit gain module is connected with the second switch module and the signal output end and is used for holding the second switch sample-hold signal;
the third switching module is connected to the unit gain module, and configured to perform third switching sample-and-hold processing on the second switching sample-and-hold signal according to the second clock input signal and the third clock input signal to obtain a third switching sample-and-hold signal;
the second switch module is further connected to the third switch module, and is further configured to perform fourth switch sample-and-hold processing on the third switch sample-and-hold signal according to the second clock input signal and the third clock input signal to obtain an output signal.
In one embodiment of the invention, the first switch module comprises an inverter INV3Inverter INV4Transistor M11Transistor M16Wherein, in the step (A),
the inverter INV3And said second clock signal input terminal, said transistor M11Gate of (1), the transistor M13The inverter INV3And the transistor M12The inverter INV4With said third clock signal input terminal, said transistor M14Gate of (1), the transistor M16The inverter INV4And the transistor M15Of the transistor M, the transistor M11Source electrode of, the transistor M11Drain electrode of, the transistor M12Source electrode of, the transistor M14Source electrode of, the transistor M14Drain electrode of, the transistor M15Is connected with a third output terminal of the band-gap reference module, the transistor M12Substrate of (1), said transistor M15The substrates of the transistors M are all connected with VDD12And the transistor M13Source electrode of, the transistor M13Drain electrode of, the transistor M16Source electrode of, the transistor M16Drain electrode of, the transistor M15The drain of the first switch module is connected with the second switch module and the third switch module.
In one embodiment of the invention, the second switch module comprises an inverter INV5Inverter INV6Transistor M21Transistor M26Wherein, in the step (A),
the inverter INV5And said second clock signal input terminal, said transistor M21Gate of (1), the transistor M23The inverter INV5And the transistor M22The inverter INV6With said third clock signal input terminal, said transistor M24Gate of (1), the transistor M26The inverter INV6And the transistor M25Of the transistor M, the transistor M21Source electrode of, the transistor M21Drain electrode of, the transistor M22Source electrode of, the transistor M24Source electrode of, the transistor M24Drain electrode of, the transistor M25Is connected with the first switch module and the third switch module, the transistor M22Substrate of (1), said transistor M25The substrate of (a) is connected with the third switch module and the unity gain module, the transistor M22And the transistor M23Source electrode of, the transistor M23Drain electrode of, the transistor M26Source electrode of, the transistor M26Drain electrode of, the transistor M25The drain electrode of the unit gain module is connected with the signal output end and the unit gain module.
In one embodiment of the present invention, the third switch module comprises an inverter INV7Inverter INV8Transistor M31Transistor M36Wherein, in the step (A),
the inverter INV7And said second clock signal input terminal, said transistor M31Gate of (1), the transistor M33The inverter INV7And the transistor M32The inverter INV8With said third clock signal input terminal, said transistor M34Gate of (1), the transistor M36The inverter INV8And the transistor M35Of the transistor M, the transistor M31Source electrode of, the transistor M31Drain electrode of, the transistor M32Source electrode of, the transistor M34Source electrode of, the transistor M34Drain electrode of, the transistor M35Is connected to the second switch module and the unity gain module, the transistor M32Substrate of (1), said transistor M35The substrates of the transistors M are all connected with VDD32And the transistor M33Source electrode of, the transistor M33Drain electrode of, the transistor M36Source electrode of, the transistor M36Drain electrode of, the transistor M35Is connected with the first switch module and the second switch module.
In one embodiment of the present invention, the transistor M11Transistor M13Transistor M21Transistor M23Transistor M31Transistor M33Same size, the transistors M14Transistor M16Transistor M24Transistor M26Transistor M34Transistor M36Same size, the transistors M12Transistor M22Transistor M32Same size, the transistors M15Transistor M25Transistor M35Same size, the transistors M11Size of the transistor M12Half of the size of the transistor M14Size of the transistor M15Half of the size of the transistor M15Is smaller than the transistor M12。
In one embodiment of the invention, the unity gain module comprises an amplifier AL, a capacitor C3Wherein, in the step (A),
the positive input end of the amplifier AL, the second switch module and the signal outputOutput terminal and capacitor C3The reverse input end of the amplifier AL is connected with the second switch module and the third switch module, the output end of the amplifier AL is connected with the second switch module and the third switch module, the power supply end of the amplifier AL is connected with VDD, and the capacitor C3The other end of the first and second electrodes is grounded.
Another embodiment of the present invention provides a sampling method based on an ultra-low power consumption reference circuit, which is characterized in that the sampling method includes the following steps:
step 1, controlling a first clock input signal to enable a band gap reference module to be in a working mode, outputting a first self-starting voltage, a second self-starting voltage and a reference voltage in the working mode, and controlling a second clock input signal and a third clock input signal to enable a sample-and-hold module to be in a sampling mode, so as to sample the reference voltage in the sampling mode and obtain an output signal;
step 2, controlling the first clock input signal to enable the bandgap reference module to be in a non-working mode, and controlling the second clock input signal and the third clock input signal to enable the sample-and-hold module to be in a hold mode, so as to hold the output signal in the hold mode;
step 3, controlling the first clock input signal to enable the bandgap reference module to be in the working mode again, enabling the bandgap reference module to be in the working mode quickly by the first self-starting voltage and the second self-starting voltage through the first self-starting module and the second self-starting module respectively, outputting a new first self-starting voltage, a new second self-starting voltage and a new reference voltage in the working mode, and controlling the second clock input signal and the third clock input signal to enable the sample-and-hold module to be in the sampling mode, so as to sample the new reference voltage in the sampling mode to obtain a new output signal;
step 4, controlling the first clock input signal to enable the bandgap reference module to be in the non-operating mode, and controlling the second clock input signal and the third clock input signal to enable the sample-and-hold module to be in the hold mode, so as to hold the new output signal in the hold mode;
and 5, repeatedly executing the step 3 and the step 4 within preset time.
Compared with the prior art, the invention has the beneficial effects that:
according to the ultra-low power consumption reference circuit, the first self-starting module, the second self-starting module and the sampling and holding module are additionally arranged on the periphery of the band gap reference module, so that the band gap reference module intermittently works, the power consumption of the reference circuit is greatly reduced, and meanwhile, the good stability of output voltage is kept; the method for adding the sampling and holding module, the first self-starting module and the second self-starting module at the periphery of the band-gap reference module is simple in mode and suitable for multiple different band-gap reference cores.
Drawings
Fig. 1 is a schematic structural diagram of an ultra-low power consumption reference circuit according to an embodiment of the present invention;
fig. 2 is a specific circuit schematic diagram of a first self-starting module in an ultra-low power consumption reference circuit according to an embodiment of the present invention;
fig. 3 is a specific circuit schematic diagram of a second self-starting module in an ultra-low power reference circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a sample-and-hold module in an ultra-low power consumption reference circuit according to an embodiment of the present invention;
fig. 5 is a specific circuit schematic diagram of a first switch module in an ultra-low power reference circuit according to an embodiment of the present invention;
fig. 6 is a specific circuit schematic diagram of a second switch module in an ultra-low power reference circuit according to an embodiment of the present invention;
fig. 7 is a specific circuit schematic diagram of a third switch module in an ultra-low power reference circuit according to an embodiment of the present invention;
FIG. 8 is a specific circuit diagram of a bandgap reference module in an ultra-low power reference circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of waveforms between an emulated input signal and an ideal output signal of an ultra-low power consumption reference circuit according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of waveforms between an analog input signal and an actual output signal of an ultra-low power consumption reference circuit according to an embodiment of the present invention;
fig. 11 is a schematic diagram illustrating partial amplification of a waveform between an analog input signal and an actual output signal of an ultra-low power consumption reference circuit according to an embodiment of the present invention;
fig. 12 is a schematic flowchart of a sampling method based on an ultra-low power consumption reference circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of an ultra-low power consumption reference circuit according to an embodiment of the present invention. The embodiment provides an ultra-low power consumption reference circuit, which comprises:
a band-gap reference module, a first self-starting module, a second self-starting module and a sampling and holding module, wherein,
the band-gap reference module is used for generating a first self-starting voltage, a second self-starting voltage and a reference voltage according to a first clock input signal;
the first self-starting module is connected with the band gap reference module and used for providing a first self-starting voltage for the band gap reference module according to a first clock input signal;
the second self-starting module is connected with the band gap reference module and used for providing a second self-starting voltage for the band gap reference module according to the first clock input signal;
and the sampling and holding module is connected with the band-gap reference module and is used for sampling and holding the reference voltage according to the second clock input signal and the third clock input signal to obtain an output signal.
In particular, although the conventional MOS transistor-based low-power reference structure can provide a stable reference voltage at the nA level, the voltage reference is extremely poor in robustness and unstable in performance, and is sensitive to process parameters and temperature, so that the application environment is limited. Based on the existing problems, the embodiment proposes an ultra-low power consumption reference circuit, in which a bandgap reference module can not only provide a stable reference voltage at the nA level, in order to solve the above problems in the prior art, in this embodiment, a first self-start module, a second self-start module and a sample-and-hold module are added at the periphery of the bandgap reference module, and the first self-start module and the second self-start module can respectively provide a first self-start voltage and a second self-start voltage for the bandgap reference module to help the bandgap reference module to quickly establish a working point and enter a normal working state, therefore, power consumption is reduced, and the sampling and holding module on the periphery of the band gap reference module samples and holds the reference voltage output by the band gap reference module in real time, so that the stability of the band gap reference module for providing the reference voltage is improved. The band gap reference module, the first self-starting module and the second self-starting module are inputted with a first clock signal CLK1Control when the first clock input signal CLK1When the clock input signal CLK is at a high level, the band gap reference module, the first self-starting module and the second self-starting module work normally, the band gap reference module outputs a first self-starting voltage, a second self-starting voltage and a reference voltage, the first self-starting module and the second self-starting module respectively sample and store the first self-starting voltage and the second self-starting voltage, the first self-starting voltage and the second self-starting voltage are respectively provided for the band gap reference module as starting voltages in the next period, and when the first clock input signal CLK is input, the first self-starting module and the second self-starting module work normally1When the level is low, the band gap reference module is closed and does not work, and at the moment, the first self-starting module and the second self-starting module respectively keep and store the first self-starting voltage and the second self-starting voltage to prepare for starting work of the band gap reference module in the next period; the sample-and-hold module is output by the second clockIncoming signal CLK2A second clock input signal CLK3Control when the second clock is input with the signal CLK2Or a second clock input signal CLK3When the level is high, the sampling and holding module is in a sampling mode, performs sampling storage processing on the reference voltage, and when a second clock input signal CLK is input2And a second clock input signal CLK3When the voltage is at a low level, the sample-and-hold module is in a hold mode, and performs hold-and-store processing on the reference voltage. The bandgap reference module of this embodiment may be a conventional bandgap reference circuit, and preferably, an amplifier is designed in the conventional bandgap reference circuit.
In the embodiment, the first self-starting module and the second self-starting module are added at the periphery of the band gap reference module, so that the band gap reference module intermittently works, the power consumption of the reference circuit is greatly reduced, and the good stability of the output voltage is kept; in the embodiment, by adding the sample-and-hold module, the first self-starting module and the second self-starting module to the periphery, the method is simple, and is suitable for multiple different band-gap reference cores.
Further, the first self-starting module of the present embodiment includes an inverter INV1Transistor M1Transistor M3And a capacitor C1。
Specifically, referring to fig. 2, fig. 2 is a specific circuit schematic diagram of a first self-starting module in an ultra-low power consumption reference circuit according to an embodiment of the present invention, where in the first self-starting module of the embodiment: inverter INV1Input terminal of (1), transistor M3The grid of which is connected with the input end of the first clock signal, an inverter INV1And transistor M1Gate of (1), transistor M2Is connected to the gate of transistor M1Drain electrode of and a first output end V of the bandgap reference moduleAConnected, transistor M1Source and transistor M2Drain electrode of (1), transistor M3Of the transistor M2Source electrode of (1), transistor M3Source electrode and capacitor C1Is connected to a capacitor C1And the other end of the same is grounded. When the first clock signal input end inputs the first clockInput signal CLK1When the voltage level is high, the first self-starting module of the embodiment applies the voltage V at the key node a of the bandgap reference circuitASamples are stored in a capacitor C1Up until the next period T the first clock input signal CLK1When the high level of the capacitor C is reached1Stored voltage VAReversely charging the key point A to help the band-gap reference module to quickly establish the working point, thereby reducing the average power consumption when the first clock input signal CLK is input at the first clock signal input end1When the voltage is at a low level, the first self-starting module keeps storing the first self-starting voltage and prepares for starting the band gap reference module in the next period. The key node a in this embodiment is preferably a positive input terminal or a negative input terminal of an internal amplifier of the bandgap reference module.
Further, the second self-starting module of this embodiment includes an inverter INV2Transistor M4Transistor M6And a capacitor C2。
Specifically, referring to fig. 3, fig. 3 is a specific circuit schematic diagram of a second self-starting module in an ultra-low power consumption reference circuit according to an embodiment of the present invention, where in the second self-starting module of the embodiment: inverter INV2Input terminal of (1), transistor M6The grid of which is connected with the input end of the first clock signal, an inverter INV2And transistor M4Gate of (1), transistor M5Is connected to the gate of transistor M4And a second output terminal V of the bandgap reference moduleBConnected, transistor M4Source and transistor M5Drain electrode of (1), transistor M6Of the transistor M5Source electrode of (1), transistor M6Source electrode and capacitor C2Is connected to a capacitor C2And the other end of the same is grounded. Similar to the first self-start module, when the first clock input terminal inputs the first clock input signal CLK1When the voltage level is high, the second self-starting module of the embodiment can convert the voltage V at the key node B of the bandgap reference circuitBSample and hold the sample stored in the capacitor C2Up until the first clock input signal of the next cycleNumber CLK1When the high level of the capacitor C is reached2Stored voltage VBReversely charging the key point B to help the band-gap reference module to further quickly establish a working point so as to reduce average power consumption when the first clock input signal CLK is input from the first clock signal input end1When the voltage is at a low level, the second self-starting module keeps storing the second self-starting voltage and prepares for starting the band gap reference module in the next period. In this embodiment, the key node B is preferably a positive input end or a negative input end of an amplifier inside the bandgap reference module, and if the key node a is selected as the positive input end of the amplifier, the key node B is selected as the negative input end of the amplifier.
Further, the sample-and-hold module of the present embodiment includes a unity gain module, a first switch module, a second switch module, and a third switch module.
Specifically, referring to fig. 4, fig. 4 is a schematic structural diagram of a sample-and-hold module in an ultra-low power consumption reference circuit according to an embodiment of the present invention, where the sample-and-hold module in the embodiment includes a unity gain module, a first switch module, a second switch module, and a third switch module, specifically:
and the first switch module is used for carrying out first switch sampling and holding processing on the reference voltage according to the second clock input signal and the third clock input signal to obtain a first switch sampling and holding signal. Referring to fig. 5, fig. 5 is a specific circuit diagram of a first switch module in an ultra-low power consumption reference circuit according to an embodiment of the present invention. The first switch module of this embodiment includes an inverter INV3Inverter INV4Transistor M11Transistor M16Specifically: inverter INV3Input terminal of (1), second clock signal input terminal, transistor M11Gate of (1), transistor M13Is connected to the grid electrode of the inverter INV3And transistor M12Is connected to the grid electrode of the inverter INV4Input terminal of (1), third clock signal input terminal, transistor M14Gate of (1), transistor M16Is connected to the grid electrode of the inverter INV4And transistor M15Is connected to the gate of transistor M11Source electrode of (1), transistor M11Drain electrode of (1), transistor M12Source electrode of (1), transistor M14Source electrode of (1), transistor M14Drain electrode of (1), transistor M15Is connected with the third output end of the band-gap reference module, and a transistor M12Substrate of (1), transistor M15The substrates of the transistors M are all connected with VDD12And the transistor M13Source electrode of (1), transistor M13Drain electrode of (1), transistor M16Source electrode of (1), transistor M16Drain electrode of (1), transistor M15The drain electrode of the first switch module is connected with the first switch module and the second switch module.
Preferably, the transistor M11Transistor M13Same size, transistors M14Transistor M16Same size, transistors M11Size of transistor M12Half of the size, transistor M14Size of transistor M15Half of the size, transistor M15Smaller than transistor M12And (4) size.
Transistor M of the present embodiment11Transistor M13Are the same size and are transistors M12At half the size, transistor M can be cancelled12Transistor M, a charge injection effect occurring during switching14Transistor M16Are the same size and are transistors M15Half the size of the transistor M can be offset15The charge injection effect generated during switching can reduce the undesirable ripple generated at the output end of the first switch module, improve the sampling precision, and the inverter INV3And transistor M11Gate of (1), transistor M13The grid electrodes of the first and second switches are respectively connected to form a first input end of the first switch module, and the inverter INV4And transistor M14Gate of (1), transistor M16The grid electrodes of the first and second switching modules are respectively connected to form a second input end of the first switching module, and the transistor M11And the source and drain of transistor M12Source electrode of (1), transistor M14Source and drain of (1), transistor M15The source electrodes of the first and second switches are connected to form a third output of the first switch moduleInput terminal, transistor M12Substrate of (2) and transistor M15Are connected to form a fourth input terminal of the first switching module, a transistor M12Drain electrode of (1), transistor M13Source and drain of (1), transistor M16Source and drain of (1), transistor M15The drain electrodes of the first and second switching modules are connected to form the output end of the first switching module; is supplied with a second clock input signal CLK2Controlled transistor M11Transistor M12Transistor M13Formed branch and receiving third clock input signal CLK3Controlled transistor M14Transistor M15Transistor M16The formed branch is connected in parallel between the third input end of the first switch module and the output end of the first switch module, and the transistor M15Smaller than transistor M12Size, therefore at the second clock input signal CLK2The undesirable ripple generated during the jump is also small, when the second clock input signal CLK2At high level, the transistor M12Is turned on when the third clock inputs signal CLK3At high level, the transistor M15Is turned on when the second clock input signal CLK is set2And a third clock input signal CLK3When the circuit is turned from low level to high level, the two branches are charged together to increase the charging speed, and a second clock input signal CLK is set2First from low to high, i.e. third clock input signal CLK3Is compared with a second clock input signal CLK2Postponing t4 from toggling low to high may reduce the second clock input signal CLK2Or a third clock input signal CLK3And undesirable ripples of the first switch module are generated during turning, so that the first switch sampling and holding processing is performed on the reference voltage to obtain a first switch sampling and holding signal.
And the second switch module is used for carrying out second switch sampling and holding processing on the first switch sampling and holding signal according to the second clock input signal and the third clock input signal to obtain a second switch sampling and holding signal. Referring to fig. 6, fig. 6 is a specific circuit diagram of a second switch module in an ultra-low power consumption reference circuit according to an embodiment of the present inventionEmbodiment the second switch module includes an inverter INV5Inverter INV6Transistor M21Transistor M26Specifically: inverter INV5Input terminal of (1), second clock signal input terminal, transistor M21Gate of (1), transistor M23Is connected to the grid electrode of the inverter INV5And transistor M22Is connected to the grid electrode of the inverter INV6Input terminal of (1), third clock signal input terminal, transistor M24Gate of (1), transistor M26Is connected to the grid electrode of the inverter INV6And transistor M25Is connected to the gate of transistor M21Source electrode of (1), transistor M21Drain electrode of (1), transistor M22Source electrode of (1), transistor M24Source electrode of (1), transistor M24Drain electrode of (1), transistor M25And the transistor M in the first switch module12And the transistor M13Source electrode of (1), transistor M13Drain electrode of (1), transistor M16Source electrode of (1), transistor M16Drain electrode of (1), transistor M15Is connected to the third switching module, transistor M22Substrate of (1), transistor M25The substrate of the transistor M is connected with the third switch module and the unit gain module, and the transistor M22And the transistor M23Source electrode of (1), transistor M23Drain electrode of (1), transistor M26Source electrode of (1), transistor M26Drain electrode of (1), transistor M25Drain electrode of and signal output terminal VOUTAnd the unit gain module is connected.
Preferably, the transistor M11Transistor M13Transistor M21Transistor M23Same size, transistors M14Transistor M16Transistor M24Transistor M26Same size, transistors M12Transistor M22Same size, transistors M15Transistor M25Same size, transistors M21Size of transistor M22Half of the size, transistor M24Size of transistor M25Half of the size, transistor M25Small sizeIn the transistor M22。
The second switch module has the same circuit structure as the first switch module, and is specifically implemented as the first switch module, which is not repeated here, and the second switch sample-and-hold signal is obtained by performing the first switch sample-and-hold processing on the first switch sample-and-hold signal through the second switch module.
And the unit gain module is used for carrying out holding processing on the second switch sampling and holding signal. Referring to fig. 4, the unity gain module of the present embodiment includes an amplifier AL and a capacitor C3Specifically: the forward input of the amplifier AL and the transistor M in the second switching module22And the transistor M23Source electrode of (1), transistor M23Drain electrode of (1), transistor M26Source electrode of (1), transistor M26Drain electrode of (1), transistor M25Drain electrode, signal output terminal, and capacitor C3Is connected to the inverting input of the amplifier AL and the transistor M in the second switching module22Substrate of (1), transistor M25Is connected to the third switching module, the output of the amplifier AL is connected to the transistor M in the second switching module22Substrate of (1), transistor M25The substrate of the amplifier AL is connected with the third switch module, the power supply end of the amplifier AL is connected with VDD, and the capacitor C3The other end of the first and second electrodes is grounded. In the unit gain module of this embodiment, the amplifier AL can control the voltages at the third input terminal, the fourth input terminal and the output terminal of the second switch circuit module to be the same in the hold mode by clamping, so as to suppress the leakage current and make the capacitor C3The voltage across can be kept constant.
And the third switching module is used for carrying out third switching sampling and holding processing on the second switching sampling and holding signal according to the second clock input signal and the third clock input signal to obtain a third switching sampling and holding signal. Referring to fig. 7, fig. 7 is a specific circuit diagram of a first switch module in an ultra-low power consumption reference circuit according to an embodiment of the present invention. The third switch module of this embodiment includes an inverter INV7Inverter INV8Transistor M31Transistor M36Specifically: inverter INV7Input terminal of (1), second clock signal input terminal, transistor M31Gate of (1), transistor M33Is connected to the grid electrode of the inverter INV7And transistor M32Is connected to the grid electrode of the inverter INV8Input terminal of (1), third clock signal input terminal, transistor M34Gate of (1), transistor M36Is connected to the grid electrode of the inverter INV8And transistor M35Is connected to the gate of transistor M31Source electrode of (1), transistor M31Drain electrode of (1), transistor M32Source electrode of (1), transistor M34Source electrode of (1), transistor M34Drain electrode of (1), transistor M35And the transistor M in the second switch module22Substrate of (1), transistor M25The output terminal of the amplifier AL in the unit gain module, and a transistor M32Substrate of (1), transistor M35The substrates of the transistors M are all connected with VDD32And the transistor M33Source electrode of (1), transistor M33Drain electrode of (1), transistor M36Source electrode of (1), transistor M36Drain electrode of (1), transistor M35And the transistor M in the first switch module12And the transistor M13Source electrode of (1), transistor M13Drain electrode of (1), transistor M16Source electrode of (1), transistor M16Drain electrode of (1), transistor M15Drain electrode of (1), transistor M in the second switching module21Source electrode of (1), transistor M21Drain electrode of (1), transistor M22Source electrode of (1), transistor M24Source electrode of (1), transistor M24Drain electrode of (1), transistor M25Is connected to the source of (a).
Preferably, the transistor M11Transistor M13Transistor M21Transistor M23Transistor M31Transistor M33Same size, transistors M14Transistor M16Transistor M24Transistor M26Transistor M34Transistor M36Same size, transistors M12Transistor M22Transistor M32Same size, transistors M15Transistor M25Transistor M35Same size, transistors M31Size of transistor M32Half of the size, transistor M34Size of transistor M35Half of the size, transistor M35Smaller than transistor M32。
In this embodiment, the third switch module has the same circuit structure as the first switch module, and is specifically implemented as the first switch module, which is not described herein again, and the third switch module is used to perform third switch sample-and-hold processing on the second switch sample-and-hold signal to obtain a third switch sample-and-hold signal. Wherein the third switching module and the amplifier AL in the unity gain module act together to switch the transistor M in the second switching module22And a transistor M25The source, drain and substrate of (A) are clamped at the same potential, thereby suppressing substrate leakage and enabling the capacitor C3The upper voltage fluctuates only in a very small range DeltaV 1 in the whole period T, the holding time is prolonged, the period that the whole circuit can normally work is prolonged, and the average power consumption is reduced.
And the second switch module is also used for carrying out fourth switch sampling and holding processing on the third switch sampling and holding signal according to the second clock input signal and the third clock input signal to obtain an output signal. In this embodiment, the second switch module performs a fourth switch sample-and-hold process on the third switch sample-and-hold signal held by the third switch module and the unity gain module together to obtain the final output signal of the sample-and-hold module.
Note that the transistor M of this embodiment is11Transistor M16Transistor M21Transistor M26Transistor M31Transistor M36The sizes of the reference blocks are the width-to-length ratios corresponding to the transistors, and the specific circuit implementation of the bandgap reference module in the embodiment is not limited, for example, the bandgap reference module may be a conventional MOS transistor-based low-power-consumption reference structure and is used for providing a reference voltage.
For verifying the ultra-low power reference circuit provided in this embodiment, please refer to fig. 8, where fig. 8 is a circuit diagram of an ultra-low power reference circuit provided in this embodiment of the present inventionA specific circuit schematic diagram of a bandgap reference module in an ultra-low power consumption reference circuit, during verification, the bandgap reference module in this embodiment adopts a specific circuit shown in fig. 8, which is not described in detail herein, the first start module and the second start module respectively adopt specific circuits shown in fig. 2 and 3, and the first switch module, the second switch module, the third switch module and the unity gain module in the sample-and-hold module respectively adopt specific circuits shown in fig. 5, 6, 7 and 4. Referring to fig. 9, fig. 10 and fig. 11, fig. 9 is a schematic diagram of waveforms between an artificial input signal and an ideal output signal of an ultra-low power consumption reference circuit according to an embodiment of the present invention, fig. 10 is a schematic diagram of waveforms between an artificial input signal and an actual output signal of an ultra-low power consumption reference circuit according to an embodiment of the present invention, fig. 11 is a schematic diagram of partial amplification of waveforms between an artificial input signal and an actual output signal of an ultra-low power consumption reference circuit according to an embodiment of the present invention, where T in fig. 9 is a first clock input signal CLK1A second clock input signal CLK2A third clock input signal CLK3Common period, t1For a first clock input signal CLK1Duration of high level, i.e. time for the bandgap reference module to remain in operation, T and T1The difference is the hold time of the sample-and-hold module, t2For a first clock input signal CLK1Jump from low level to high level and second clock input signal CLK2A third clock input signal CLK3The time difference of jumping from low level to high level must be larger than the time needed for establishing the normal working point of the band-gap reference module in order to make the circuit work normally, t3And t4Is the sample time, t, of the sample and hold module4Is the third clock input signal CLK3Compared with a second clock input signal CLK2The time of jumping from the high level to the low level is delayed, because the power consumption of the first switch module, the second switch module and the third switch module is extremely low and can be ignored, assuming that the average power consumption of the bandgap reference module in normal operation is P, the first clock input signal CLK1The duty ratio of (a) is a (preferably, a ═ t)1T), then the average work of the circuitP' is a P, so that the first clock input signal CLK is only controlled1The duty ratio of the bandgap reference module is at an extremely low level, the overall power consumption of the bandgap reference module can be greatly reduced, and the embodiment can reduce the first clock input signal CLK by reducing the setup time of the bandgap reference module and increasing the period T1The duty cycle of (c). The parameters adopted in the simulation test of the embodiment include: VDD 2.15V, T5 ms, T1＝15us，t2＝8.5us，t3＝5.5us，t40.5 us. As can be seen from fig. 11, the first clock input signal CLK is inputted every time the first clock signal input terminal is inputted1When the voltage is high potential, the band gap reference module is in a working state and outputs a reference voltage VREFWhenever the first clock signal input terminal CLK1When the input first clock input signal is at a low potential, the band gap reference module is closed and is in a working state; when the second clock signal input terminal inputs the second clock input signal CLK2Or a third clock input signal CLK input at a third clock input terminal3When the level is high, the sampling and holding module outputs the reference voltage V output by the third output end of the band-gap reference moduleREFCollect the capacitance C3When the second clock signal input terminal inputs the second clock input signal CLK2And a third clock input signal CLK input from a third clock input terminal3When the voltage is low level, the sampling holding module holds the capacitor C3The voltage on is not changed, i.e. the voltage of the hold state is still the reference voltage VREFE.g. reference voltage V provided by a bandgap reference moduleREFAt 1.2V,. DELTA.V during the entire period T1＝1.9mV，ΔV1/VREFThe average power consumption is 67.5nW when the power consumption is 0.15 percent, the simulation result is consistent with the expected function, and the ultra-low power consumption can be realized. In the embodiment, the total power consumption P of the circuit in one period T is calculated by dividing into two parts, wherein the first part is that the duration is T1Power consumption P consumed in the sampling mode of (2)1The second part is a duration of (T-T)1) Power consumption P in hold mode2Power consumption P in hold mode2With respect to power consumption P in sampling mode1Can be ignoredSo the average power consumption P of the circuit can be expressed as
Figure BDA0002384861450000191
And is
Figure BDA0002384861450000192
Wherein
Figure BDA0002384861450000193
Is the average value of the total current of the circuit in the sampling mode.
In summary, the working principle of the ultra-low power consumption reference circuit provided by this embodiment is as follows: the working state of the band-gap reference module is controlled by a first clock input signal CLK1Control when the first clock input signal CLK1When the level is high, the band gap reference module works normally and outputs a reference voltage VREFAnd a first start-up voltage V at a key point A, BAA second starting voltage VBThe first self-starting module and the second self-starting module respectively apply a first starting voltage VAA second starting voltage VBCollect the capacitance C1Capacitor C2When the first clock inputs the signal CLK1When the level is low, the band gap reference module stops working, and the first self-starting module and the second self-starting module respectively keep the capacitor C1Capacitor C2First starting voltage V ofAA second starting voltage VBUnchanged, but the first clock input signal CLK of the next cycle1When the high level arrives, the first self-starting module and the second self-starting module respectively use the first starting voltage VAA second starting voltage VBThe signal is provided to the band-gap reference module to accelerate the band-gap reference module to enter a working state, and the working state of the sample-hold module is input by a second clock signal CLK2And a third clock input signal CLK3Control when the second clock is input with the signal CLK2Or a third clock input signal CLK3When the voltage is high level, the sampling and holding module refers to the reference voltage VREFCollect the capacitance C3When the second clock inputs signal CLK2And a third clock input signal CLK3Are all lowAt level, the sample-and-hold module holds the capacitor C3Upper reference voltage VREFAnd is not changed.
Therefore, the low-power-consumption reference circuit provided by the embodiment has the advantages that the sampling and holding module, the first self-starting module and the second self-starting module are additionally arranged on the periphery of the band gap reference module, so that the band gap reference module intermittently works, the power consumption of the reference circuit is greatly reduced, and meanwhile, the good stability of the output voltage is kept; the method for adding the sample-hold module, the first self-starting module and the second self-starting module to the periphery is simple in mode, suitable for various band-gap reference core circuits and wide in application range.
Example two
Referring to fig. 12, fig. 12 is a schematic flowchart of a sampling method based on an ultra-low power consumption reference circuit according to an embodiment of the present invention. The embodiment provides a sampling method based on an ultra-low power consumption reference circuit, which includes the ultra-low power consumption reference circuit described in the first embodiment, please refer to the first embodiment for the implementation principle and the technical effect of the ultra-low power consumption reference circuit, which is not described herein again, and specifically the sampling method includes the following steps:
step 1, controlling a first clock input signal to enable a band gap reference module to be in a working mode, outputting a first self-starting voltage, a second self-starting voltage and a reference voltage in the working mode, and controlling a second clock input signal and a third clock input signal to enable a sample-and-hold module to be in a sampling mode, so as to sample the reference voltage in the sampling mode and obtain an output signal;
step 2, controlling the first clock input signal to enable the band gap reference module to be in a non-working mode, and controlling the second clock input signal and the third clock input signal to enable the sampling and holding module to be in a holding mode so as to hold the output signal in the holding mode;
step 3, controlling a first clock input signal to enable the band gap reference module to be in a working mode again, enabling the band gap reference module to be in the working mode rapidly through a first self-starting voltage and a second self-starting voltage respectively by the first self-starting module and the second self-starting module, outputting a new first self-starting voltage, a new second self-starting voltage and a new reference voltage in the working mode, and controlling a second clock input signal and a third clock input signal to enable the sampling and holding module to be in a sampling mode so as to sample the new reference voltage in the sampling mode to obtain a new output signal;
step 4, controlling the first clock input signal to enable the band gap reference module to be in a non-working mode, and controlling the second clock input signal and the third clock input signal to enable the sampling and holding module to be in a holding mode, so that a new output signal is held in the holding mode;
and 5, repeatedly executing the step 3 and the step 4 within preset time.
Specifically, the reference voltage sampled in the conventional sampling method is influenced by the environment, and the like, and thus has the problems of poor robustness and unstable performance, but the sampling method provided by the embodiment is implemented based on the ultra-low power consumption reference circuit of the first embodiment, and the initial state is as step 1, and the first clock input signal CLK is controlled1The band gap reference module is in a working mode for high level, and generates a first starting voltage, a second starting voltage and a reference voltage which are needed by the first self-starting module, the second self-starting module and the sampling and holding module respectively, at the moment, the first self-starting module and the second self-starting module are also in the working mode, and the first starting voltage and the second starting voltage are sampled and stored to control a second clock input signal CLK2Or a third clock input signal CLK3The sampling and holding module is in a sampling mode when the voltage is at a high level, and performs sampling storage processing on the reference voltage to obtain an output signal; controlling a first clock input signal CLK1When the level is low, if the bandgap reference module is in the non-operating mode in step 2, the first self-starting module and the second self-starting module are also in the non-operating mode at this time, the first starting voltage and the second starting voltage are kept and stored, and the second clock input signal CLK is controlled2And a third clock input signal CLK3When the voltage is low, the sample-hold module is in hold mode and outputs signalsThe signals are kept and stored, so that the good stability of the sampled output signals is kept; and when the band gap reference module is changed from the non-working mode to the working mode again in step 3, the first self-starting module and the second self-starting module respectively provide a first starting voltage and a second starting voltage for the band gap reference module, so that the band gap reference module is accelerated to enter the working mode, and simultaneously a new first starting voltage, a new second starting voltage and a new reference voltage required by the first self-starting module, the second self-starting module and the sample and hold module are respectively generated again, the sample and hold module continues to execute the sampling process in step 1 in step 3, while the band gap reference module is in the non-working mode in step 4, the sample and hold module continues to execute the holding process in step 2 in step 4. Wherein, the steps 1 to 2 are initial sampling condition processing, the steps 3 to 4 are normal sampling processing, and the steps 3 to 4 are continuously repeated within a preset time (such as the period T in the first embodiment) in the normal sampling process, so as to realize the sampling processing of the signal in the present embodiment.
In summary, the sampling method provided in this embodiment is based on the ultra-low power consumption reference circuit of the first embodiment, so that ultra-low power consumption is achieved in sampling, and meanwhile, the ultra-low power consumption reference circuit provides a reference voltage, and the reference voltage has good stability, so that higher sampling precision is ensured.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (9)

1. An ultra-low power consumption reference circuit is characterized by comprising a band gap reference module, a first self-starting module, a second self-starting module and a sampling and holding module, wherein,
the band-gap reference module is used for generating a first self-starting voltage, a second self-starting voltage and a reference voltage according to a first clock input signal;
the first self-starting module is connected with the band-gap reference module and used for providing the first self-starting voltage for the band-gap reference module according to the first clock input signal;
the second self-starting module is connected with the band-gap reference module and used for providing the second self-starting voltage for the band-gap reference module according to the first clock input signal;
the sampling and holding module is connected with the band-gap reference module and is used for sampling and holding the reference voltage according to a second clock input signal and a third clock input signal to obtain an output signal;
wherein the first self-starting module comprises an inverter INV1Transistor M1Transistor M3And a capacitor C1Wherein, in the step (A),
the inverter INV1Of the transistor M3The grid of the inverter INV is connected with the first clock signal input end1And the transistor M1Gate of (1), the transistor M2Of the transistor M, the transistor M1Is connected with a first output terminal of the band-gap reference module, the transistor M1And the transistor M2Drain electrode of, the transistor M3Of said transistor M, said transistor M2Source electrode of, the transistor M3And the capacitor C1Is connected to the capacitor C1And the other end of the same is grounded.
2. The ultra-low power consumption reference circuit of claim 1, wherein the second self-starting module comprises an inverter INV2Transistor M4Transistor M6And a capacitor C2Wherein, in the step (A),
the inverter INV2Of the transistor M6The grid of the inverter INV is connected with the first clock signal input end2And the transistor M4OfElectrode, said transistor M5Of the transistor M, the transistor M4Is connected with a second output terminal of the bandgap reference module, the transistor M4And the transistor M5Drain electrode of, the transistor M6Of said transistor M, said transistor M5Source electrode of, the transistor M6And the capacitor C2Is connected to the capacitor C2And the other end of the same is grounded.
3. The ultra-low power reference circuit of claim 1, wherein the sample-and-hold module comprises a unity gain module, a first switch module, a second switch module, and a third switch module, wherein,
the first switch module is connected with the band-gap reference module and is used for carrying out first switch sampling and holding processing on the reference voltage according to the second clock input signal and the third clock input signal to obtain a first switch sampling and holding signal;
the second switch module is connected with the first switch module and is used for performing second switch sampling and holding processing on the first switch sampling and holding signal according to the second clock input signal and the third clock input signal to obtain a second switch sampling and holding signal;
the unit gain module is connected with the second switch module and the signal output end and is used for holding the second switch sample-hold signal;
the third switching module is connected to the unit gain module, and configured to perform third switching sample-and-hold processing on the second switching sample-and-hold signal according to the second clock input signal and the third clock input signal to obtain a third switching sample-and-hold signal;
the second switch module is further connected to the third switch module, and is further configured to perform fourth switch sample-and-hold processing on the third switch sample-and-hold signal according to the second clock input signal and the third clock input signal to obtain an output signal.
4. The ultra-low power reference circuit of claim 3, wherein the first switch module comprises an inverter INV3Inverter INV4Transistor M11Transistor M16Wherein, in the step (A),
the inverter INV3And a second clock signal input, said transistor M11Gate of (1), the transistor M13The inverter INV3And the transistor M12The inverter INV4And a third clock signal input, said transistor M14Gate of (1), the transistor M16The inverter INV4And the transistor M15Of the transistor M, the transistor M11Source electrode of, the transistor M11Drain electrode of, the transistor M12Source electrode of, the transistor M14Source electrode of, the transistor M14Drain electrode of, the transistor M15Is connected with a third output terminal of the band-gap reference module, the transistor M12Substrate of (1), said transistor M15The substrates of the transistors M are all connected with VDD12And the transistor M13Source electrode of, the transistor M13Drain electrode of, the transistor M16Source electrode of, the transistor M16Drain electrode of, the transistor M15The drain of the first switch module is connected with the second switch module and the third switch module.
5. The ultra-low power reference circuit of claim 4, wherein the second switch module comprises an inverter INV5Inverter INV6Transistor M21Transistor M26Wherein, in the step (A),
the inverter INV5And said second clock signal input terminal, said transistor M21Gate of (1), the transistor M23The inverter INV5And the transistor M22The inverter INV6With said third clock signal input terminal, said transistor M24Gate of (1), the transistor M26The inverter INV6And the transistor M25Of the transistor M, the transistor M21Source electrode of, the transistor M21Drain electrode of, the transistor M22Source electrode of, the transistor M24Source electrode of, the transistor M24Drain electrode of, the transistor M25Is connected with the first switch module and the third switch module, the transistor M22Substrate of (1), said transistor M25The substrate of (a) is connected with the third switch module and the unity gain module, the transistor M22And the transistor M23Source electrode of, the transistor M23Drain electrode of, the transistor M26Source electrode of, the transistor M26Drain electrode of, the transistor M25The drain electrode of the unit gain module is connected with the signal output end and the unit gain module.
6. The ultra-low power reference circuit of claim 5, wherein the third switching module comprises an inverter INV7Inverter INV8Transistor M31Transistor M36Wherein, in the step (A),
the inverter INV7And said second clock signal input terminal, said transistor M31Gate of (1), the transistor M33The inverter INV7And the transistor M32The inverter INV8With said third clock signal input terminal, said transistor M34Gate of (1), the transistor M36The inverter INV8And the transistor M35Of the transistor M, the transistor M31Source electrode of, the transistor M31Drain electrode of, the transistor M32Source electrode of, the transistor M34Source electrode of, the transistor M34Drain electrode of, the transistor M35Is connected to the second switch module and the unity gain module, the transistor M32Substrate of (1), said transistor M35The substrates of the transistors M are all connected with VDD32And the transistor M33Source electrode of, the transistor M33Drain electrode of, the transistor M36Source electrode of, the transistor M36Drain electrode of, the transistor M35Is connected with the first switch module and the second switch module.
7. The ultra-low power consumption reference circuit of claim 6, wherein the transistor M11Transistor M13Transistor M21Transistor M23Transistor M31Transistor M33Same size, the transistors M14Transistor M16Transistor M24Transistor M26Transistor M34Transistor M36Same size, the transistors M12Transistor M22Transistor M32Same size, the transistors M15Transistor M25Transistor M35Same size, the transistors M11Size of the transistor M12Half of the size of the transistor M14Size of the transistor M15Half of the size of the transistor M15Is smaller than the transistor M12。
8. The ultra-low power consumption reference circuit of claim 3, wherein the unity gain block comprises an Amplifier (AL), a capacitor (C)3Wherein, in the step (A),
the positive input end of the amplifier AL, the second switch module, the signal output end and the capacitor C3Is connected with the second switch module and the third switch module, the reverse input end of the amplifier AL is connected with the second switch module and the third switch module, the amplifierThe output end of the AL is connected with the second switch module and the third switch module, the power supply end of the amplifier AL is connected with VDD, and the capacitor C3The other end of the first and second electrodes is grounded.
9. A sampling method based on an ultra-low power consumption reference circuit, which is characterized by comprising the ultra-low power consumption reference circuit as claimed in any one of claims 1 to 8, and the sampling method comprises the following steps:
step 1, controlling a first clock input signal to enable a band gap reference module to be in a working mode, outputting a first self-starting voltage, a second self-starting voltage and a reference voltage in the working mode, and controlling a second clock input signal and a third clock input signal to enable a sample-and-hold module to be in a sampling mode, so as to sample the reference voltage in the sampling mode and obtain an output signal;
step 2, controlling the first clock input signal to enable the bandgap reference module to be in a non-working mode, and controlling the second clock input signal and the third clock input signal to enable the sample-and-hold module to be in a hold mode, so as to hold the output signal in the hold mode;
step 3, controlling the first clock input signal to enable the bandgap reference module to be in the working mode again, enabling the bandgap reference module to be in the working mode quickly by the first self-starting voltage and the second self-starting voltage through the first self-starting module and the second self-starting module respectively, outputting a new first self-starting voltage, a new second self-starting voltage and a new reference voltage in the working mode, and controlling the second clock input signal and the third clock input signal to enable the sample-and-hold module to be in the sampling mode, so as to sample the new reference voltage in the sampling mode to obtain a new output signal;
step 4, controlling the first clock input signal to enable the bandgap reference module to be in the non-operating mode, and controlling the second clock input signal and the third clock input signal to enable the sample-and-hold module to be in the hold mode, so as to hold the new output signal in the hold mode;
and 5, repeatedly executing the step 3 and the step 4 within preset time.
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