CN111198319B - Method and system for automatically measuring power-on time sequence of mainboard - Google Patents
Method and system for automatically measuring power-on time sequence of mainboard Download PDFInfo
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- CN111198319B CN111198319B CN201911415679.XA CN201911415679A CN111198319B CN 111198319 B CN111198319 B CN 111198319B CN 201911415679 A CN201911415679 A CN 201911415679A CN 111198319 B CN111198319 B CN 111198319B
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000008859 change Effects 0.000 claims abstract description 15
- 238000005259 measurement Methods 0.000 claims description 24
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 10
- 229910052799 carbon Inorganic materials 0.000 claims description 10
- 230000001960 triggered effect Effects 0.000 claims description 5
- 238000009434 installation Methods 0.000 claims description 3
- 238000011161 development Methods 0.000 abstract description 5
- 238000012827 research and development Methods 0.000 abstract description 4
- 239000012141 concentrate Substances 0.000 abstract description 3
- 238000011160 research Methods 0.000 abstract description 3
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- 230000008569 process Effects 0.000 description 4
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2839—Fault-finding or characterising using signal generators, power supplies or circuit analysers
- G01R31/2841—Signal generators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2844—Fault-finding or characterising using test interfaces, e.g. adapters, test boxes, switches, PIN drivers
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Abstract
The invention provides a method and a system for automatically measuring the power-on time sequence of a mainboard, wherein an automatic measuring program is burnt in a CPLD FW, an oscilloscope with the automatic measuring program is matched, after power is on, the measuring time of the oscilloscope is matched with the measuring time of the power-on and power-off of the CPLD FW so as to correctly obtain a waveform, the CPLD is provided with a counter, and a GPIO output end signal is changed through the change of the value of the counter, so that the power-on sequence can be quickly known in the hardware research and development stage, the time on the measuring signal is greatly reduced, and EE has more abundant time to concentrate on research, development and debugging.
Description
Technical Field
The invention relates to the technical field of power-on time sequence measurement, in particular to a method and a system for automatically measuring the power-on time sequence of a mainboard.
Background
At present, EE measurement power-on time sequence adopts a traditional mode, firstly, a position to be measured is found out on a schematic diagram and Boardfile, a single core with the length of about 5-7 centimeters is cut and welded on a measurement target, then, a carbon rod of an oscilloscope is connected, a trigger point is set on the oscilloscope, and finally, power on and power off are carried out, and a waveform is obtained.
However, this method EE requires much time for measurement of power-on timing, and the board may be carelessly damaged during the measurement process, resulting in short circuit to the ground, etc., and the board in the development stage EE is already used in an insufficient amount, and if the system debugging is to be assisted at the same time, the board usage is more stressful.
Disclosure of Invention
The invention aims to provide a method and a system for automatically measuring a power-on time sequence of a mainboard, and aims to solve the problems that in the prior art, a large amount of time is spent on measuring the power-on time sequence, the power-on sequence is quickly known in a hardware research and development stage, the time for measuring the signal time sequence is reduced, and the working efficiency is improved.
To achieve the above technical object, the present invention provides a method for automatically measuring a power-on sequence of a motherboard, the method comprising the following operations:
burning an automatic measurement program into the CPLD FW, and performing automatic triggering and storage by using an oscilloscope matched with an OS system, wherein a carbon rod of the oscilloscope is hooked on a pin head of the CPLD;
the system is powered on, an oscilloscope automatic measurement program is started, the oscilloscope measurement time is matched with the measurement time of the power-on and power-off of the CPLD FW, the CPLD counter has an initial value of 0, the counter is powered on after each power-off, 1 is added to the counter, two GPIO output signals connected to the pin head are changed according to the change of the counter value, the oscilloscope is triggered according to the GPIO output signals to obtain graphic signals and store the graphic signals, the CPLD is powered off, and the CPLD is powered on after the oscilloscope resets the trigger point.
Preferably, the counter is a scratch variable.
Preferably, the VR power-up sequence to be measured automatically needs to be after the CPLD is powered up.
The invention also provides an automatic measurement mainboard power-on time sequence system, which comprises:
the preposed installation module is used for burning the automatic measurement program into the CPLD FW, automatically triggering and storing the automatic measurement program by utilizing an oscilloscope matched with an OS system, and hooking a carbon rod of the oscilloscope on a pin head of the CPLD;
the time sequence measuring module is used for starting an oscilloscope automatic measuring program after the system is powered on, the oscilloscope measuring time is matched with the measuring time of the power-on and power-off of the CPLD FW, the CPLD counter has an initial value of 0, the power-on is converted into the power-on every time when the power-off is carried out, the counter is added with 1, two GPIO output signals connected to the pin heads are changed according to the change of the counter value, the oscilloscope is triggered according to the GPIO output signals to obtain graphic signals and store the graphic signals, the CPLD is powered off, and the CPLD is powered on after the oscilloscope resets the trigger point.
Preferably, the counter is a temporary storage variable.
Preferably, the VR power-up sequence to be measured automatically needs to be after the CPLD is powered up.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
compared with the prior art, the invention records the automatic measuring program in the CPLD FW, and matches the oscilloscope with the automatic measuring program, after the power is on, the measuring time of the oscilloscope is matched with the measuring time of the power on and power off of the CPLD FW to correctly obtain the waveform, the CPLD sets the counter, and the signal at the output end of the GPIO is changed through the change of the value of the counter, so that the power on sequence can be quickly obtained in the hardware research and development stage, the time on the measuring signal is greatly reduced, and the EE has more abundant time to concentrate on research, development and debugging.
Drawings
Fig. 1 is a schematic diagram of an automatic measurement method for power-on timing of a motherboard according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a CPLD workflow for automatically measuring a power-on sequence according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an oscilloscope working flow for automatically measuring a power-on timing sequence according to an embodiment of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
The following describes a method and a system for automatically measuring a power-on timing sequence of a motherboard in detail with reference to the accompanying drawings.
The invention discloses a method for automatically measuring the power-on time sequence of a mainboard, which comprises the following operations:
burning an automatic measurement program into the CPLD FW, and performing automatic triggering and storage by using an oscilloscope matched with an OS system, wherein a carbon rod of the oscilloscope is hooked on a pin head of the CPLD;
the system is powered on, an oscilloscope automatic measurement program is started, the oscilloscope measurement time is matched with the measurement time of DC on and DC off of CPLD FW, the CPLD counter initial value is 0, every time DC off is converted into DC on, the counter is added with 1, two GPIO values connected to the pin head are changed according to the change of the counter value, the oscilloscope triggers a graphic signal according to the GPIO value and then stores the graphic signal, the CPLD can be DC off, and the CPLD can be DC on after the oscilloscope resets the trigger point.
In the process of automatically measuring the power-on time sequence of the mainboard, the carbon rod of the oscilloscope only needs to be hooked on the pin near the CPLD all the time without adjustment. The GPIOs of the CPLD are connected to nearby pin headers as shown in fig. 1.
The design sequence of the system VR suggested by the embodiment of the invention is as follows: PSU Standard power- > P3V3_ AUX- > P5V _ AUX- > BMC AUX PWR VRs- > CPU or PCH AUX PWR VRs- > RSMRST _ N default- > PS _ ON to PSU- > System main PWRs ex P12V- > MEM PWR- > CPU PWR- > CPU _ PWROK- > CPU _ RESET _ N default. After the power supply P12V _ AUX is switched in during the development and design stage, the first VR must be P3V3_ AUX to supply power to the CPLD, then P5V _ AUX and the standby power required by BMC and CPU, if the VR before the CPLD power supply is designed, it cannot be automatically measured, so the VR power-on sequence which needs to be automatically measured needs to be measured after the CPLD is powered on, for example, the P5V _ AUX is designed before P3V3_ AUX, and PG occurs earlier than the CPLD. In addition, the signal to be measured must be accessed into CPLD GPIO.
In the automated measurement process, EE must explicitly inform CPLD FW engineer about the order of DC off to DC on for each group VR PG, and signal terminals such as RSMRST _ N, PSU _ PWROK, CPU0_ PWR _ BTN, CPU0_ SLP _ S3_ N, CPU _ PWROK and CPU _ RESET _ N are included in the middle, which platform design needs to be identified, which special timing measurement cannot be covered inevitably, and which additional manual measurement is necessary, but this type is usually not many.
The CPLD will use a temporary storage variable as a counter, every time DC off goes to DC on, the counter will increment 1, then change two GPIO values connected to the external pins according to the change of the counter, and change to the next group VR PG or other signals, for example, the initial value of the counter is 0, assign two fixed GPIOs A1 and B1 and pull out to 2-pin header for carbon rod measurement, the first group output is 0 according to the counter, the outputs P5V _ AUX PG and P2V5_ AUX PG, the counter is accumulated to 1, then DC off goes to DC on, the second group output is 1 according to the counter, the outputs P2V5_ AUX PG and P1V2_ AUX PG, the counter becomes 2, and so on, as shown in FIG. 2.
The oscilloscope automatic trigger and the storage program which are matched with the OS system are matched, the time sequence is matched with CPLD FW DC on and off, for example, before the start, the oscilloscope measurement automatic program is started, the rising edge of the first signal of the first group of the trigger is started, after the start, the automatic CPLD FW starts to be executed, after the oscilloscope triggers the graph and stores the graph, the CPLD is off, the oscilloscope resets the trigger point, and the CPLD is controlled to be on.
As shown in fig. 3, the system is powered on, P3V3_ AUX is ready, the CPLD starts running, the initial value of the counter is 0, when GPIO a1 outputs a signal, the oscilloscope has automatically captured the waveform and stored, the CPLD counter increments by 1, then DC off, after waiting for a period of time, DC on again, and the oscilloscope resets the trigger point.
The embodiment of the invention records the automatic measuring program in the CPLD FW, is matched with the oscilloscope of the automatic measuring program, after the CPLD FW is powered on, the measuring time of the oscilloscope is matched with the measuring time of the power-on and power-off of the CPLD FW to accurately obtain the waveform, the CPLD is provided with the counter, and the signal at the output end of the GPIO is changed through the change of the value of the counter, so that the power-on sequence can be quickly known in the hardware research and development stage, the time on the measuring signal is greatly reduced, and the EE has more abundant time to concentrate on research, development and debugging.
The embodiment of the invention also discloses an automatic measurement mainboard power-on time sequence system, which comprises:
the pre-installation module is used for burning the automatic measurement program into the CPLD FW, and performing automatic triggering and storage by utilizing an oscilloscope matched with an OS system, wherein a carbon rod of the oscilloscope is hooked on a pin head of the CPLD;
the time sequence measuring module is used for starting an oscilloscope automatic measuring program after the system is powered on, the oscilloscope measuring time is matched with the measuring time of the power-on and power-off of the CPLD FW, the CPLD counter has an initial value of 0, the power-on is converted into the power-on every time when the power-off is carried out, the counter is added with 1, two GPIO output signals connected to the pin heads are changed according to the change of the counter value, the oscilloscope is triggered according to the GPIO output signals to obtain graphic signals and store the graphic signals, the CPLD is powered off, and the CPLD is powered on after the oscilloscope resets the trigger point.
In the automated measurement process, EE must explicitly inform CPLD FW engineer about the order of DC off to DC on for each group VR PG, and signal terminals such as RSMRST _ N, PSU _ PWROK, CPU0_ PWR _ BTN, CPU0_ SLP _ S3_ N, CPU _ PWROK and CPU _ RESET _ N are included in the middle, which platform design needs to be identified, which special timing measurement cannot be covered inevitably, and which additional manual measurement is necessary, but this type is usually not many.
The CPLD will use a temporary storage variable as a counter, every time DC off goes to DC on, the counter will increment 1, then change two GPIO values connected to the external pins according to the change of the counter, and change to the next group VR PG or other signals, for example, the initial value of the counter is 0, assign two fixed GPIOs A1 and B1 and pull out to 2-pin header for carbon rod measurement, the first group output is 0 according to the counter, the outputs P5V _ AUX PG and P2V5_ AUX PG, the counter is accumulated to 1, then DC off goes to DC on, the second group output is 1 according to the counter, the outputs are P2V5_ AUX PG and P1V2_ AUX PG, the counter becomes 2, and so on.
The oscilloscope automatic trigger and the storage program which are matched with the OS system are matched, the time sequence is matched with CPLD FW DC on and off, for example, before the start, the oscilloscope measurement automatic program is started, the rising edge of the first signal of the first group of the trigger is started, after the start, the automatic CPLD FW starts to be executed, after the oscilloscope triggers the graph and stores the graph, the CPLD is off, the oscilloscope resets the trigger point, and the CPLD is controlled to be on.
The system is powered on, P3V3_ AUX is ready, the CPLD starts to run, the initial value of the counter is 0, when the GPIO A1 outputs signals, the oscilloscope automatically captures waveforms and stores the waveforms, the CPLD counter is increased by 1, then DC is off, DC is on after waiting for a period of time, and the oscilloscope resets the trigger point.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. A method for automatically measuring a power-on time sequence of a mainboard is characterized by comprising the following operations:
burning an automatic measurement program into the CPLD FW, and performing automatic triggering and storage by using an oscilloscope matched with an OS system, wherein a carbon rod of the oscilloscope is hooked on a pin head of the CPLD;
the system is powered on, an oscilloscope automatic measurement program is started, the oscilloscope measurement time is matched with the measurement time of the power-on and power-off of the CPLD FW, the CPLD counter has an initial value of 0, the counter is powered on after each power-off, 1 is added to the counter, two GPIO output signals connected to the pin head are changed according to the change of the counter value, the oscilloscope is triggered according to the GPIO output signals to obtain graphic signals and store the graphic signals, the CPLD is powered off, and the CPLD is powered on after the oscilloscope resets the trigger point.
2. The method as claimed in claim 1, wherein the counter is a temporary variable.
3. The method of claim 1, wherein the VR power-on sequence to be automatically measured is after the CPLD power-on.
4. An automatic measurement mainboard power-on timing sequence system, the system comprises:
the pre-installation module is used for burning the automatic measurement program into the CPLD FW, and performing automatic triggering and storage by utilizing an oscilloscope matched with an OS system, wherein a carbon rod of the oscilloscope is hooked on a pin head of the CPLD;
the time sequence measuring module is used for starting an oscilloscope automatic measuring program after the system is powered on, the oscilloscope measuring time is matched with the measuring time of the power-on and power-off of the CPLD FW, the CPLD counter has an initial value of 0, the power-on is converted into the power-on every time when the power-off is carried out, the counter is added with 1, two GPIO output signals connected to the pin heads are changed according to the change of the counter value, the oscilloscope is triggered according to the GPIO output signals to obtain graphic signals and store the graphic signals, the CPLD is powered off, and the CPLD is powered on after the oscilloscope resets the trigger point.
5. The system according to claim 4, wherein the counter is a temporary variable.
6. The system according to claim 4, wherein the VR power-on sequence to be automatically measured is subsequent to the CPLD power-on sequence.
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| CN201911415679.XA CN111198319B (en) | 2019-12-31 | 2019-12-31 | Method and system for automatically measuring power-on time sequence of mainboard |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108548955A (en) * | 2018-05-24 | 2018-09-18 | 郑州云海信息技术有限公司 | A kind of method and system using CPLD monitoring signal exceptions |
| CN108646173A (en) * | 2018-08-07 | 2018-10-12 | 郑州云海信息技术有限公司 | It is a kind of to solve the not dull method and system of VR timing sequence test PG signals |
| CN109726056A (en) * | 2018-10-10 | 2019-05-07 | 郑州云海信息技术有限公司 | It is a kind of to improve the not dull method and system of VR clock signal |
| CN109885437A (en) * | 2019-02-25 | 2019-06-14 | 西安易朴通讯技术有限公司 | Baseboard management controller BMC, terminal and power-up state diagnotic module, method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7725742B2 (en) * | 2006-08-15 | 2010-05-25 | Mitac International Corp. | Remote monitor module for power initialization of computer system |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108548955A (en) * | 2018-05-24 | 2018-09-18 | 郑州云海信息技术有限公司 | A kind of method and system using CPLD monitoring signal exceptions |
| CN108646173A (en) * | 2018-08-07 | 2018-10-12 | 郑州云海信息技术有限公司 | It is a kind of to solve the not dull method and system of VR timing sequence test PG signals |
| CN109726056A (en) * | 2018-10-10 | 2019-05-07 | 郑州云海信息技术有限公司 | It is a kind of to improve the not dull method and system of VR clock signal |
| CN109885437A (en) * | 2019-02-25 | 2019-06-14 | 西安易朴通讯技术有限公司 | Baseboard management controller BMC, terminal and power-up state diagnotic module, method |
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