CN211603369U - Server DC power-down fault positioning system - Google Patents
Server DC power-down fault positioning system Download PDFInfo
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- CN211603369U CN211603369U CN201921927700.XU CN201921927700U CN211603369U CN 211603369 U CN211603369 U CN 211603369U CN 201921927700 U CN201921927700 U CN 201921927700U CN 211603369 U CN211603369 U CN 211603369U
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Abstract
The utility model provides a server DC power-down fault positioning system, which comprises a VR chip, wherein the VR chip is connected with a CPLD chip; the CPLD chip is connected with the BMC; the CPLD chip is also connected with an oscilloscope and a PC client. The CPLD chip acquires a fault problem signal; for more accurate test, a receiving end of a VR-PWRGD signal of the CPLD chip is connected with an oscilloscope; the fault waveform can be captured through the oscilloscope, and meanwhile, the condition that the oscilloscope can not reproduce noise wave filtering is avoided. The system also comprises a DEMO board, wherein the DEMO board is connected with the CPLD chip and outputs a switch control signal to the CPLD chip. The DEMO board is used for performing startup and shutdown actions, reboot is immediately performed when the board card runs for the fault occurrence time, and time is saved due to quick reproduction and quick verification.
Description
Technical Field
The utility model relates to a server test technical field, concretely relates to server DC falls electric fault positioning system.
Background
With the progress of science and technology, informatization becomes the mainstream of the modern times, and the rapid development of the internet industry has higher and higher requirements on data storage and exchange, so that the development of the server industry is further promoted. The server plays an important role in data storage, exchange and transmission, and on the other hand, the development of the internet industry and the acceleration of the informatization process can be further promoted by the progress of the server technology.
Along with increasing to the server requirement, performance, consumption, the precision degree of each spare part have also had a higher requirement on the server, and the factor that need consider when corresponding the mainboard design will increase, and mainboard precision degree has certain improvement, and mainboard power supply line and signal line can be more complicated simultaneously, appear bug probability and can further improve like this in server operation process and frequent action in-process.
In the mainboard return board testing process, the DC power failure phenomenon of the mainboard in the DC Reboot process is found, the problem is not found quickly by adopting the traditional scheme for debug, meanwhile, the recurrence probability is very low, if the phenomenon is repeated, a good solution and a countermeasure can not be provided, and the project progress and the bug processing are greatly influenced. When a bug with low recurrence probability is encountered, the recurrence process is slow, and the time for fault location is long.
Disclosure of Invention
Can appear the very low DC of recurrence probability and fall the problem of electricity to mainboard test in-process, when facing the lower bug of recurrence probability, the recurrence process is slower, the longer problem of fault location required time the utility model provides a server DC falls electric fault positioning system.
The technical scheme of the utility model is that:
the utility model provides a server DC power down fault positioning system, which comprises a VR chip connected with a CPLD chip; the CPLD chip is connected with the BMC; the CPLD chip is also connected with an oscilloscope and a PC client.
Preferably, the VR-PWRGD signal output by the VR chip and the CPLD chip, the CPLD chip obtains the fault problem signal; for more accurate test, a receiving end of a VR-PWRGD signal of the CPLD chip is connected with an oscilloscope; the fault waveform can be captured through the oscilloscope, and meanwhile, the condition that clutter is filtered by the oscilloscope and cannot be reproduced is avoided; and the CPLD chip outputs a VR-EN signal to control the VR chip.
Preferably, the CPLC chip sends an interrupt to the BMC through interrupt; and the CPLC chip reads the BMC storage information through the 12C to obtain the specific information in the power failure process. After the downtime phenomenon occurs, the fault problem signal is acquired through the CPLD chip, the BMC reads the CPLD recorded information through the I2C and stores the CPLD recorded information through the BMC, and the specific information in the power failure process is acquired by reading the BMC storage information in the power failure process, so that the specific time of the downtime process can be acquired.
Preferably, the CPLC chip is connected with the PC client through a Signal TAP; the CPLC chip is connected with an oscilloscope through a Signal TAP. The CPLD chip acquires the waveform during downtime, and can compare the waveform with the waveform captured by the oscilloscope as comparison verification.
Preferably, the system also comprises a DEMO board, wherein the DEMO board is connected with the CPLD chip and outputs a switch control signal to the CPLD chip. The DEMO board is used for performing startup and shutdown actions, reboot is immediately performed when the board card runs for the fault occurrence time, and time is saved due to quick reproduction and quick verification.
According to the technical scheme, the utility model has the advantages of it is following: the CPLD interacts with the BMC to record fault information; the CPLD transmits fault signals, so that the influence of the filtering of the oscilloscope on the fault reproduction is avoided; and rapidly positioning fault signals and fault time, and simultaneously recording all fault dynamics. And the method has the advantages of quick reproduction, quick verification and time saving. Multiple waveform monitoring may be performed.
Furthermore, the utility model relates to a principle is reliable, and simple structure has very extensive application prospect.
Therefore, compared with the prior art, the utility model has the outstanding substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is the utility model relates to a server DC falls electric fault location system and connects the block diagram.
Detailed Description
In order to make the technical solutions in the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.
Example one
As shown in fig. 1, the technical solution of the present invention provides a server DC power down fault location system, which includes a VR chip, wherein the VR chip is connected with a CPLD chip; the CPLD chip is connected with the BMC; the CPLD chip is also connected with an oscilloscope and a PC client. The VR-PWRGD signal output by the VR chip and the CPLD chip acquire a fault problem signal; for more accurate test, a receiving end of a VR-PWRGD signal of the CPLD chip is connected with an oscilloscope; the fault waveform can be captured through the oscilloscope, and meanwhile, the condition that clutter is filtered by the oscilloscope and cannot be reproduced is avoided; and the CPLD chip outputs a VR-EN signal to control the VR chip.
The oscilloscope probe has certain filtering function, and can perform certain filtering function on the signal received by the CPLD chip when the oscilloscope probe is placed at a receiving end. Therefore, the fault signal is derived from the other Pin of the CPLD chip by utilizing the transparent transmission function of the CPLD chip, and the oscilloscope is used again to capture the signal. The CPLC chip sends out an interrupt to the BMC through the interrupt; the CPLC chip reads the BMC storage information through I2C to obtain the specific information in the power-down process. After the downtime phenomenon occurs, the fault problem signal is acquired through the CPLD chip, the BMC reads the CPLD recorded information through the I2C and stores the CPLD recorded information through the BMC, and the specific information in the power failure process is acquired by reading the BMC storage information in the power failure process, so that the specific time of the downtime process can be acquired.
The CPLC chip is connected with the PC client through a Signal TAP; the CPLC chip is connected with an oscilloscope through a Signal TAP. The CPLD chip acquires the waveform during downtime, and can compare the waveform with the waveform captured by the oscilloscope as comparison verification. The fault can still be reproduced after a plurality of reboots.
If the fault reason is not caused by line noise, but the VR chip controls power failure, a storage mechanism can be introduced into the VR chip, the err occurrence reason and time are recorded, and meanwhile, a VR manufacturer communicates with the VR chip to confirm the problem reason, so that the problem can be solved more quickly.
When the fault is caused by line noise, the line routing can be analyzed, whether noise sources such as a clock, a crystal oscillator and a hook exist or not is observed, whether noise is introduced due to the reason such as overlong lines or not is observed, the CPLD chip is provided with a filtering mechanism, and part of low-speed signals can be guided into the filtering mechanism to avoid noise interference.
Example two
The difference between the present embodiment and the first embodiment is as follows:
because the time required by restarting each time in the test process is longer, in order to save time, the system also comprises a DEMO board which is connected with the CPLD chip and outputs a switch control signal to the CPLD chip. The DEMO board is used for performing startup and shutdown actions, reboot is immediately performed when the board card runs for the fault occurrence time, and time is saved due to quick reproduction and quick verification.
Although the present invention has been described in detail by referring to the drawings in conjunction with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and substance of the present invention, and these modifications or substitutions are intended to be within the scope of the present invention/any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. A DC power failure fault positioning system of a server is characterized by comprising a VR chip, wherein the VR chip is connected with a CPLD chip; the CPLD chip is connected with the BMC; the CPLD chip is also connected with an oscilloscope and a PC client.
2. The system according to claim 1, wherein the VR chip outputs a VR-PWRGD signal and the CPLD chip, and the CPLD chip obtains a fault problem signal; the receiving end of the VR-PWRGD signal of the CPLD chip is connected with an oscilloscope;
and the CPLD chip outputs a VR-EN signal to control the VR chip.
3. The system according to claim 2, wherein the CPLC chip sends an interrupt to the BMC through interrupt;
the CPLC chip reads the BMC storage information through I2C to obtain the specific information in the power-down process.
4. The system according to claim 3, wherein the CPLC chip is connected with the PC client through a Signal TAP; the CPLC chip is connected with an oscilloscope through a Signal TAP.
5. The server DC power-down fault location system according to claim 4, further comprising a DEMO board, wherein the DEMO board is connected to the CPLD chip and outputs a switch control signal to the CPLD chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921927700.XU CN211603369U (en) | 2019-11-09 | 2019-11-09 | Server DC power-down fault positioning system |
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| CN201921927700.XU CN211603369U (en) | 2019-11-09 | 2019-11-09 | Server DC power-down fault positioning system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112463479A (en) * | 2020-11-19 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Automatic testing method and system for VR abnormal power failure detection positioning function |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112463479A (en) * | 2020-11-19 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Automatic testing method and system for VR abnormal power failure detection positioning function |
| CN112463479B (en) * | 2020-11-19 | 2023-01-06 | 苏州浪潮智能科技有限公司 | Automatic testing method and system for VR abnormal power failure detection positioning function |
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