CN111009575A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN111009575A
CN111009575A CN201811494037.9A CN201811494037A CN111009575A CN 111009575 A CN111009575 A CN 111009575A CN 201811494037 A CN201811494037 A CN 201811494037A CN 111009575 A CN111009575 A CN 111009575A
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gate
disposed
semiconductor device
type region
trench
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周洛龙
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Hyundai Motor Co
Kia Corp
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Hyundai Motor Co
Kia Motors Corp
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  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开了半导体器件及其制造方法。根据本发明的示例性实施方式的半导体器件包括：n‑型外延层，布置在衬底的第一表面上；p型区，布置在n‑型外延层上；n+型区，布置在p型区上；栅极，布置在n‑型外延层上；氧化膜，布置在栅极上；源电极，布置在氧化膜和n+型区上；以及漏电极，布置在衬底的第二表面上。栅极包括PN结部分。

Description

半导体器件及其制造方法
相关申请的交叉引证
本申请要求于2018年10月5日提交给韩国知识产权局的韩国专利申请第10-2018-0118905号的优先权，该申请通过引证结合于本文中。
技术领域
本发明涉及半导体器件及其制造方法。
背景技术
功率半导体器件尤其需要低导通电阻或低饱和电压,以便在导电状态下产生非常大的电流并且减小功率损耗。进一步地，功率半导体器件主要需要具有一种特性，即，高击穿电压特性，功率半导体器件通过该特性可在关断状态下或者在开关关断时抵抗施加到功率半导体器件的两端的PN结的反向高电压。
功率半导体器件中的金属氧化物半导体场效应晶体管(MOSFET)是在数字电路和模拟电路中最常用的晶体管。
同时，为了减小导通电阻并增加电流密度，研究了去除其中的平面栅极MOSFET的JFET区的沟槽栅极MOSFET。
在沟槽栅极MOSFET的情况下，在形成沟槽之后，栅极绝缘层形成在沟槽的横向表面和底表面上。在这种情况下，电场集中至布置在沟槽的拐角处的栅极绝缘层，使得栅极绝缘层可能在半导体器件的运行期间断裂。
在该背景技术部分中公开的上述信息仅用于增强对本发明的背景的理解，并且因此，上述信息可包含并不构成在该国已被本领域普通技术人员已知的现有技术的信息。
发明内容
完成的本发明致力于弛豫集中至沟槽栅极金属氧化物半导体场效应晶体管(MOSFET)中的栅极绝缘层的电场。本发明的示例性实施方式提供了半导体器件。n-型外延层布置在衬底的第一表面上。p型区布置在n-型外延层上。n+型区布置在p型区上。栅极布置在n-型外延层上。氧化膜布置在栅极上。源电极布置在氧化膜和n+型区上。漏电极布置在衬底的第二表面上。栅极包括PN结部分。
栅极可包括第一栅极、以及布置在第一栅极上的第二栅极，第一栅极可包括n型多晶硅，并且第二栅极可包括p型多晶硅。
第一栅极可与第二栅极接触，并且PN结部分可以布置在其中第一栅极与第二栅极接触的表面中。
第一栅极的横向表面的边界可以与第二栅极的横向表面的边界相同。
第二栅极可以覆盖第一栅极的横向表面。
半导体器件可以进一步包括：沟槽，布置在n-型层中；以及栅极绝缘层，布置在沟槽内，其中，第一栅极可以与布置在沟槽的下表面中的栅极绝缘层接触。
第一栅极的上表面的延伸线可以布置为低于p型区的下表面。
第一栅极可以布置为从沟槽的横向表面延伸至下表面。
第一栅极可以与布置在沟槽的下表面和横向表面中的栅极绝缘层接触。
半导体器件可以进一步包括布置在p型区上并且与沟槽的横向表面隔开的p+型区。
该衬底可以是n+型碳化硅衬底。
本发明的另一个示例性实施方式提供了制造半导体器件的方法，该方法包括：在衬底的第一表面上顺序地形成n-型外延层、p型区和n+型区；通过蚀刻n-型外延层、p型区和n+型区形成沟槽；在沟槽内形成栅极绝缘层；在栅极绝缘层上形成栅极；在栅极上形成氧化膜；形成布置在氧化膜和n+型区上的源电极；并且形成布置在衬底的第二表面上的漏电极，其中，栅极包括PN结部分。
形成栅极可包括：在栅极绝缘层上形成栅极材料层；通过蚀刻栅极材料层形成第一栅极；并且在第一栅极上形成第二栅极。
根据本发明的示例性实施方式，布置在沟槽内的栅极包括PN结部分，以便可以弛豫(relax)集中至栅极绝缘层的电场。
因此，可以提高半导体器件的击穿电压。
进一步地，根据集中至栅极绝缘层的电场的弛豫，可以改善栅极绝缘层的耐久性。
附图说明
图1是示意性地示出了根据本发明的示例性实施方式的半导体器件的横截面的实例的示图。
图2是示意性地示出了图1的半导体器件的关断状态的示图。
图3是示意性地示出了图1的半导体器件的导通状态的示图。
图4至图8是示意性地示出了制造图1的半导体器件的方法的实例的示图。
图9是示意性地示出了根据本发明的另一示例性实施方式的半导体器件的横截面的实例的示图。
图10是示意性地示出了制造图9的半导体器件的方法的实例的示图。
图11是示意性地示出了根据本发明的另一示例性实施方式的半导体器件的横截面的实例的示图。
图12是示意性地示出了根据本发明的另一示例性实施方式的半导体器件的横截面的实例的示图。
具体实施方式
在以下详细说明中，仅简单地通过说明的方式示出和描述了本发明的某些示例性实施方式。如本领域技术人员将认识到的，全部在不背离本发明的精神或范围的情况下，可以以各种不同的方式修改所描述的实施方式。
附图和描述在本质上被认为是示例性的而不是限制性的，并且贯穿说明书，相同参考数字表示相同元件。
此外，为了理解和便于描述，任意示出了附图中示出的每种配置的尺寸和厚度，但是本发明并不限于此。在附图中，为了清楚起见，放大了层、膜、面板、区等的厚度。在附图中，为了理解和便于描述，放大了一些层和区的厚度。
进一步地，应当理解的是，当诸如层、膜、区或者衬底等元件被称为位于另一元件“上”时，其可以直接位于该另一元件上，或者还可以存在中间元件。相反，当元件被称为“直接位于”另一元件“上”时，不存在中间元件。进一步地，在用作参考的部分“上”或“以上”意味着放置在用作参考的部分上或以下，但是不必意味着基于与重力方向相反的方向放置在“上”或“以上”。
此外，除非明确描述与此相反，否则词语“包括”及诸如“包含”或“含有”等变形将被理解为暗示包括所指定的元件但不排除任何其他元件。
进一步地，贯穿本说明书，“在平面上”意味着期中目标部分从顶侧看的情况，并且“横截面图”意味着期中通过垂直切割目标部分获得的目标部分的横截面从侧面看的情况。
图1是示意性地示出了根据本发明的示例性实施方式的半导体器件的横截面的实例的示图。
参考图1，根据本发明的示例性实施方式的半导体器件包括衬底100、n-型层200、p型区300、沟槽350、n+型区400、栅极600、p+型区700、源电极900和漏电极950。
衬底100可以是n+型碳化硅衬底。
n-型层200布置在衬底100的第一表面上，并且p型区300布置在n-型层200上。n+型区400和p+型区700布置在p型区300上。在本文中，p+型区700的厚度可以大于n+型区400的厚度。
沟槽350穿过p型区300和n+型区，并且布置在n-型层200中。因此，p型区300和n+型区布置在沟槽350的横向表面上。p+型区700与沟槽350的横向表面隔开，并且n+型区布置在p+型区700和沟槽350的横向表面之间。
栅极绝缘层500布置在沟槽350内。栅极绝缘层500可包括二氧化硅(SiO2)。
栅极600布置在栅极绝缘层500上。沟槽350可以填充有栅极600，并且栅极600的一部分可以突出至沟槽350的外部。
栅极600包括第一栅极610和第二栅极620。第一栅极610与布置在沟槽350的下表面中的栅极绝缘层500接触，并且第二栅极620布置在第一栅极610上并且与第一栅极610接触。第二栅极620的一部分可以突出至沟槽350的外部。在这种情况下，第一栅极610的上表面的延伸线可以布置为低于p型区300的下表面，以便不影响由p型区300、栅极绝缘层500和第二栅极620决定的阈值电压。
第一栅极610包括n型多晶硅，并且第二栅极620包括p型多晶硅。因此，栅极600包括PN结部分J。PN结部分J布置在沟槽350内，并且形成在第一栅极610与第二栅极620接触的表面中。
氧化膜800布置在栅极600上。氧化膜800覆盖突出栅极600的横向表面。即，氧化膜800布置在第二栅极620上并且覆盖第二栅极620的横向表面。氧化膜800可包括二氧化硅(SiO2)。
源电极900布置在n+型区400、p+型区700和氧化膜800上，并且漏电极950布置在衬底100的第二表面上。在本文中，衬底100的第二表面表示与衬底100的第一表面相对的表面。源电极900和漏电极950可包括欧姆金属。
如上所述，沟槽350内的栅极600包括PN结部分J，以便在半导体器件的关断状态下电场分布至栅极绝缘层500和栅极600的PN结部分J。因此，施加到栅极绝缘层500的电场弛豫，使得可以提高半导体器件的击穿电压。进一步地，根据施加到栅极绝缘层500的电场的弛豫，可以改善栅极绝缘层500的耐久性。
然后，将参考图2和图3描述图1的半导体器件的运行。
图2和图3是示意性地示出了图1的半导体器件的运行的示图。
图2是示意性地示出了图1的半导体器件的关断状态的示图。图3是示意性地示出了图1的半导体器件的导通状态的示图。
在以下描述的条件下构成半导体器件的关断状态。
VGS<VTH，VDS≥0V
在以下描述的条件下构成半导体器件的导通状态。
VGS≥VTH，VDS>0V
在本文中，VTH是MOSFET的阈值电压，并且VGS是VG-VS，并且VDS是VD-VS。VG是施加到栅极的电压，VD是施加到漏电极的电压，并且VS是施加到源电极的电压。
参考图2，在半导体器件的关断中，形成耗尽层50以便几乎覆盖n-型层200以阻断电流路径。耗尽层50围绕沟槽350的下表面和拐角。在半导体器件的关断状态下，通过施加到漏电极950的电压在栅极600和p型区300中生成电场，并且存在于栅极600中的PN结部分J分布电场，以便低电场被施加到栅极绝缘层500。
如上所述，施加到栅极绝缘层500的电场弛豫，使得可以改善半导体器件的击穿电压。进一步地，根据以比击穿电压更低的电压施加到栅极绝缘层500的电场的弛豫，可以改善栅极绝缘层500的耐久性。
参考图3，在半导体器件的导通状态下，耗尽层50形成在布置在p型区300下方的n-型层200中。耗尽层50没有形成在邻近于沟槽350的横向表面的n-型层200中，并且沟道形成在邻近于沟槽350的横向表面的p型区300中，以便形成电流路径。即，在半导体器件的导通状态下，从源电极900发射的电子(e-)经过n+型区400、p型区300和n-型层200移动至漏电极950。
然后，将参考表1描述根据本示例性实施方式的半导体器件的特征与普遍的半导体器件的特征之间的比较。
表1表示根据本示例性实施方式的半导体器件和普遍的半导体器件的模拟结果。
比较例1是普遍的沟槽栅极MOSFET器件，其中，栅极不包括PN结部分。实例1是根据图1的半导体器件。
在表1中，在几乎相同的电流密度上比较根据实例1的半导体器件和根据比较例1的半导体器件的击穿电压。
(表1)
Figure BDA0001896400670000091
参考表1，根据比较例1的半导体器件的击穿电压表示为858V，并且根据实例1的半导体器件的击穿电压表示为1230V。即，可以看出，与根据比较例1的半导体器件的击穿电压相比，根据实例1的半导体器件的击穿电压增加43.4％。
然后，将参考图4至图8以及图1描述制造图1的半导体器件的方法。
图4至图8是示意性地示出了制造图1的半导体器件的方法的实例的示图。
参考图4，制备衬底100，并且n-型层200形成在衬底100的第一表面上。n-型层200可以通过外延生长形成在衬底100的第一表面上。在本文中，衬底100可以是n+型碳化硅衬底。
参考图5，p型区300形成在n-型层200上，并且n+型区400形成在p型区300上。p型区300可以通过将诸如硼(B)、铝(Al)、镓(Ga)和铟(In)等p离子注入至n-型层200而形成，并且n+型区400可以通过将诸如氮(N)、磷(P)、砷(As)和锑(Sb)等n离子注入至p型区300而形成。
然而，本发明不限于此，并且p型区300通过外延生长形成在n-型层200上，并且n+型区400还可以通过外延生长形成在p型区300上。
参考图6，通过蚀刻n+型区400、p型区300和n-型层200形成沟槽350。沟槽350穿过p型区300和n+型区并且形成在n-型层200中。
接下来，栅极绝缘层500形成在沟槽350内，并且第一栅极材料层610a形成在栅极绝缘层500上。沟槽350填充有第一栅极材料层610a，并且第一栅极材料层610a可包括n型多晶硅。
参考图7，通过蚀刻第一栅极材料层610a的一部分形成第一栅极610。第一栅极610形成在布置在沟槽350的下表面中的栅极绝缘层500上。在这种情况下，第一栅电极610的上表面的延伸线可以布置为低于p型区300的下表面。
参考图8，通过在第一栅极610上形成第二栅极620而形成栅极600。第二栅极620与第一栅极610接触，并且包括p型多晶硅。因此，栅极600包括PN结部分J。PN结部分J布置在沟槽350内，并且形成在第一栅极610与第二栅极620接触的表面中。沟槽350可以填充有栅极600，并且栅极600的一部分可以突出至沟槽350的外部。
接下来，诸如硼(B)、铝(Al)、镓(Ga)和铟(In)等p离子被注入n+型区400和p型区300以形成p+型区700。p+型区700与沟槽350的横向表面隔开。包含在p+型区700中的p离子的浓度高于包含在p型区300中的p离子的浓度。
接下来，氧化膜形成在栅极600上。氧化膜800可以覆盖突出栅极600的横向表面。
参考图1，源电极900形成在n+型区400、p+型区700和氧化膜800上，并且漏电极950形成在衬底100的第二表面上。
然后，将参考图9至图11描述根据本发明的另一示例性实施方式的半导体器件。
图9是示意性地示出了根据本发明的另一示例性实施方式的半导体器件的横截面的实例的示图。
参考图9，半导体器件仅在栅极600的结构上与图1的半导体器件不同，剩余结构与图1的半导体器件的那些结构相同。因此，将省略相同结构的描述。
栅极绝缘层500布置在沟槽350内，并且栅极600布置在栅极绝缘层500上。沟槽350可以填充有栅极600，并且栅极600的一部分可以突出至沟槽350的外部。
栅极600包括第一栅极610和第二栅极620。第一栅极610布置为从沟槽350的横向表面延伸至下表面，并且第二栅极620布置在第一栅极610上且与第一栅极610接触。第二栅极620的一部分可以突出至沟槽350的外部。在这种情况下，第一栅极610与布置在沟槽350的下表面和横向表面中的栅极绝缘层500接触。进一步地，第一栅极610的一部分以及第二栅极620可以突出至沟槽350的外部。
第一栅极610包括n型多晶硅，并且第二栅极620包括p型多晶硅。因此，栅极600包括PN结部分J。PN结部分J布置在沟槽350内，并且形成在第一栅极610与第二栅极620接触的表面中。
然后，将参考表2描述根据本示例性实施方式的半导体器件的特征与普遍的半导体器件的特征之间的比较。
表2表示根据本示例性实施方式的半导体器件和普遍的半导体器件的模拟结果。
比较例1是普遍的沟槽栅极MOSFET器件，其中，栅极不包括PN结部分J。实例2是根据图9的半导体器件。
在表2中，在几乎相同的电流密度上比较根据实例2的半导体器件和根据比较例1的半导体器件的击穿电压。
(表2)
Figure BDA0001896400670000121
参考表2，根据比较例1的半导体器件的击穿电压表示为858V，并且根据实例2的半导体器件的击穿电压表示为1098V。即，可以看出，与根据比较例1的半导体器件的击穿电压相比，根据实例2的半导体器件的击穿电压增加28.0％。
然后，将参考图10、图9和图6描述制造图9的半导体器件的方法。
图10是示意性地示出了制造图9的半导体器件的方法的实例的示图。
制造图9的半导体器件的方法仅在形成栅极600的方法上与制造图1的半导体器件的方法不同，但是剩余方法与制造图1的半导体器件的方法的剩余方法相同。因此，将省略相同方法的描述。
如图6所示，通过蚀刻n+型区400、p型区300和n-型层200形成沟槽350，栅极绝缘层500形成在沟槽350内，然后第一栅极材料层610a形成在栅极绝缘层500上。沟槽350填充有第一栅极材料层610a，并且第一栅极材料层610a可包括n型多晶硅。
参考图10，通过蚀刻第一栅极材料层610a的一部分形成第一栅极610。第一栅极610布置为从沟槽350的横向表面延伸至下表面。在这种情况下，第一栅极610与布置在第一栅极610的下表面和横向表面中的栅极绝缘层500接触。
然后，如图9所示，第二栅极620形成在第一栅极610上，并且制造剩余组成元件的方法与制造根据图1的半导体器件的方法相同。
图11是示意性地示出了根据本发明的另一示例性实施方式的半导体器件的横截面的实例的示图。
根据本示例性实施方式的半导体器件包括衬底100、n-型层200、p型区300、n+型区400、栅极600、p+型区700、源电极900和漏电极950。衬底100可以是n+型碳化硅衬底。
n-型层200布置在衬底100的第一表面上，并且p型区300布置在n-型层200上。n+型区400和p+型区700布置在p型区300上。在本文中，p+型区700的厚度可以大于n+型区400的厚度。
栅极绝缘层500布置在n-型层200、p型区300和n+型区400上，并且栅极600布置在栅极绝缘层500上。
栅极600包括第一栅极610和第二栅极620。第一栅极610的下表面与栅极绝缘层500接触，并且第二栅极620布置在第一栅极610上并且与第一栅极610接触。第一栅极610的横向表面的边界可以与第二栅极620的横向表面的边界相同。
第一栅极610包括n型多晶硅，并且第二栅极620包括p型多晶硅。因此，栅极600包括PN结部分J。PN结部分J形成在第一栅极610与第二栅极620接触的表面中。
氧化膜800布置在栅极600上。氧化膜800覆盖栅极600的横向表面。即，氧化膜800布置在第二栅极620上并且覆盖第一栅极610和第二栅极620的横向表面。氧化膜800可包括二氧化硅(SiO2)。
源电极900布置在n+型区400、p+型区700和氧化膜800上，并且漏电极950布置在衬底100的第二表面上。在本文中，衬底100的第二表面表示与衬底100的第一表面相对的表面。源电极900和漏电极950可包括欧姆金属。
如上所述，栅极600包括PN结部分J，以便在半导体器件的关断状态下电场分布至栅极绝缘层500和栅极600的PN结部分J。因此，施加到栅极绝缘层500的电场弛豫，使得可以改善半导体器件的击穿电压。进一步地，根据施加到栅极绝缘层500的电场的弛豫，可以改善栅极绝缘层500的耐久性。
图12是示意性地示出了根据本发明的另一示例性实施方式的半导体器件的横截面的实例的示图。
参考图12，半导体器件仅在栅极600的结构上与图11的半导体器件不同，但是剩余结构与图11的半导体器件的那些结构相同。因此，将省略相同结构的描述。
栅极绝缘层500布置在n-型层200、p型区300和n+型区400上，并且栅极600布置在栅极绝缘层500上。
栅极600包括第一栅极610和第二栅极620。第一栅极610的下表面与栅极绝缘层500接触，并且第二栅极620布置在第一栅极610上并且与第一栅极610接触。进一步地，第二栅极620覆盖第一栅极610的横向表面，并且与栅极绝缘层500接触。
氧化膜800布置在栅极600上。氧化膜800覆盖栅极600的横向表面。即，氧化膜800布置在第二栅极620上并且覆盖第二栅极620的横向表面。氧化膜800可包括二氧化硅(SiO2)。
尽管已经结合目前被视为实际的示例性实施方式描述了本发明，但是应理解的是，本发明并不局限于所公开的实施方式，而是相反，本发明旨在覆盖所附权利要求的精神和范围内包括的各种修改和等同布置。

Claims (20)

1.一种半导体器件，包括：
n-型外延层，布置在衬底的第一表面上；
p型区，布置在所述n-型外延层上；
n+型区，布置在所述p型区上；
栅极，布置在所述n-型外延层上，其中，所述栅极包括PN结部分；
氧化膜，布置在所述栅极上；
源电极，布置在所述氧化膜和所述n+型区上；以及
漏电极，布置在所述衬底的第二表面上。
2.根据权利要求1所述的半导体器件，其中：
所述栅极包括第一栅极以及布置在所述第一栅极上的第二栅极；
所述第一栅极包括n型多晶硅；并且
所述第二栅极包括p型多晶硅。
3.根据权利要求2所述的半导体器件，其中，所述第一栅极与所述第二栅极接触，所述PN结部分布置在所述第一栅极和所述第二栅极之间的界面处。
4.根据权利要求3所述的半导体器件，其中，所述第一栅极的横向表面的边界与所述第二栅极的横向表面的边界相同。
5.根据权利要求3所述的半导体器件，其中，所述第二栅极覆盖所述第一栅极的横向表面。
6.根据权利要求3所述的半导体器件，进一步包括：
沟槽，布置在所述n-型层中；以及
栅极绝缘层，布置在所述沟槽内，
其中，所述第一栅极与布置在所述沟槽的下表面中的所述栅极绝缘层接触。
7.根据权利要求6所述的半导体器件，其中，所述第一栅极的上表面的延伸线布置为低于所述p型区的下表面。
8.根据权利要求6所述的半导体器件，其中，所述第一栅极从所述沟槽的横向表面延伸至下表面。
9.根据权利要求8所述的半导体器件，其中，所述第一栅极与布置在所述沟槽的所述下表面和所述横向表面中的所述栅极绝缘层接触。
10.根据权利要求1所述的半导体器件，进一步包括：
沟槽，布置在所述n-型层中；以及
p+型区，布置在所述p型区上并且所述p+型区与所述沟槽的横向表面隔开。
11.根据权利要求1所述的半导体器件，其中，所述衬底是n+型碳化硅衬底。
12.一种制造半导体器件的方法，所述方法包括：
在衬底的第一表面上顺序地形成n-型外延层、p型区和n+型区；
通过蚀刻所述n-型外延层、所述p型区和所述n+型区形成沟槽；
在所述沟槽内形成栅极绝缘层；
在所述栅极绝缘层上方形成栅极，其中，所述栅极包括PN结部分；
在所述栅极上方形成氧化膜；
在所述氧化膜和所述n+型区上形成源电极；并且
形成布置在所述衬底的第二表面上的漏电极。
13.根据权利要求12所述的方法，其中，形成所述栅极包括：
在所述栅极绝缘层上形成栅极材料层；
通过蚀刻所述栅极材料层形成第一栅极，所述第一栅极包括n型多晶硅；并且
在所述第一栅极上形成第二栅极，所述第二栅极包括p型多晶硅。
14.根据权利要求13所述的方法，其中，所述第一栅极与所述第二栅极接触，所述PN结部分布置在所述第一栅极和所述第二栅极之间的界面处。
15.根据权利要求14所述的方法，其中，所述第一栅极与布置在所述沟槽的下表面中的所述栅极绝缘层接触。
16.根据权利要求15所述的方法，其中，所述第一栅极的上表面的延伸线布置为低于所述p型区的下表面。
17.根据权利要求14所述的方法，其中，所述第一栅极从所述沟槽的横向表面延伸至下表面。
18.根据权利要求17所述的方法，其中，所述第一栅极与布置在所述沟槽的所述下表面和所述横向表面中的所述栅极绝缘层接触。
19.根据权利要求12所述的方法，进一步包括：形成布置在所述p型区上并且与所述沟槽的横向表面隔开的p+型区。
20.根据权利要求12所述的方法，其中，所述衬底是n+型碳化硅衬底。
CN201811494037.9A 2018-10-05 2018-12-07 半导体器件及其制造方法 Pending CN111009575A (zh)

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