CN1110094C - 用于消除电子组件应力的方法和装置 - Google Patents
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Abstract
一种制造方法和所制电子组件便于在组件内消除热应力。制造方法包括提供众多集成电路芯片,后者在其大体上平的主面上具有槽。芯片叠装起来并用一种膨胀材料和一种可流动粘合剂互相间粘接起来,以形成一块电子组件。粘接如此进行,以限制组件内个别IC芯片在垂直于它们的平的面的方向内移动,在组件热膨胀时,膨胀材料和个别芯片以不同速率膨胀,然而膨胀材料流动入槽,因而消除热应力。
Description
本申请是于1995年6月19日申请的申请号为95107369.9的发明专利申请“用于消除电子组件应力的方法和装置”的分案申请。
本发明一般涉及到便于在给定空间内容纳最佳数量电路元件的高密度电子封装。更具体地说,本发明涉及到在包括例如用粘合剂粘接在一起的多块集成电路芯片的叠装阵列的电子组件中消除热应力的问题。
自集成电路技术发展以来,计算机和计算机存储设备用半导体材料晶片所组成的集成电路(IC)芯片所制成。在制成晶片后,将晶片切成小芯片,即将电路互相隔开。接着将芯片粘接到不同类型的载体上,用线互相连接并加以封装。这种“二维”芯片封装无法在给定空间内容纳最佳数量的电路,并且当芯片间传送信号时,会引入不希望有的信号延迟、电容和电感。最近出现的三维芯片阵列是重要的封装方法。典型的多块芯片电子组件包括将多IC芯片粘接固定在一起的单块结构(一个“叠层”)。
一个要讨论的问题是叠层材料的热膨胀。不同材料具有不同相应的热膨胀率。例如,在电子组件中当IC芯片和粘接层由不同材料组成并且温度升高时,每件材料以不同速率膨胀。不幸的是,由于电阻损耗,电子组件在运行时会热起来。因此当组件温度升高时,芯片和粘接层(用于将芯片粘接在一起)以不同速率膨胀,从而在组件内引起应力。
当组件膨胀受到约束时,将进一步产生组件应力。例如,如电子组件的侧面点焊连接到安装衬底上,则焊点将在垂直于组成组件的芯片的主平面的方向内限制组件膨胀(以后这称之为“Z方向”)。这个限制的原因是由于例如每个IC芯片粘接到安装衬底上,因而它无法在Z方向移动,因此不能移动的衬底就限制了热膨胀粘合剂的力的作用,由于一般屈服点是高的,所以“被压缩的”粘合剂保持它的粘接点,并在组件上产生物理应力,后者能导致焊点的损坏和失效。由温度变化造成的电子组件的膨胀和收缩会导致焊点破裂,这是工业中常见的现象,本发明直接用于解决这些问题。
本发明的一个方面提供了一种电子组件,包括:众多集成电路IC芯片,所述众多IC芯片的每一块IC芯片具有一个平的工作主面和一个平的非工作主面,所述众多IC芯片的第一IC芯片的平的非工作主面具有众多槽,所述众多IC芯片叠装成一块电子组件,其中所述平的工作主面都朝着一个共同方向;一种膨胀材料,所述膨胀材料位于所述众多IC芯片的第二IC芯片的平的工作主面和所述众多IC芯片的第一IC芯片的所述平的非工作主面之间并在机械上将所述两个面粘接在一起,所述第二IC芯片具有第一热膨胀率和所述膨胀材料具有第二热膨胀率,所述第二热膨胀率不同于第一热膨胀率;以及其中所述第一IC芯片的所述平的非工作主面中的所述众多槽提供众多空间,供所述膨胀材料膨胀进入,以便消除由于所述膨胀材料和所述第二集成电路芯片之间不同热膨胀的所述差别而引起的应力。
作为扩充,电子组件的槽的形状可设计为允许冷却剂流经它们。此外,电子组件还可以包括第三IC芯片。放置在第三IC芯片和第二IC芯片间的膨胀材料将第三IC芯片的大体上平的工作主面和第二IC芯片的大体上平的非工作主面在机械上粘结在一起。第二IC芯片的大体上平的非工作主面具有众多槽。
本发明的另一方面提供了一种电子组件,包括:众多叠装的集成电路IC芯片,所述众多IC芯片的每一块IC芯片具有第一平的主面和第二平的主面,以及一种先进热化合物,所述先进热化合物位于所述众多IC芯片的第一IC芯片的第一平的主面与所述众多IC芯片的第二IC芯片的第二平的主面之间并在机械上和所述两个面粘接在一起,所述先进热化合物导热并在电气上绝缘,其中所述第一IC芯片的所述第一平的主面具有空穴,所述先进热化合物充入所述空穴。
本发明的再一方面提供了一种用于形成电子组件的方法,包括以下步骤:(a)提供众多叠装的集成电路IC芯片,所述众多叠装IC芯片的每一块IC芯片具有第一平的主面和第二平的主面;以及(b)使用一种先进热化合物将所述众多IC芯片的第一IC芯片的第一平的主面与所述众多IC芯片的第二IC芯片的第二平的面在机械上粘接在一起,所述先进热化合物导热并在电气上绝缘,其中所述第一IC芯片的所述平的主面在其中具有空穴,所述粘接步骤(b)包括将所述空穴充以所述先进热化合物。
有利的是本发明的技术便于用来消除电子组件中的热应力。此外,该技术可用于控制“Z方向”中的组件膨胀,组件的芯片中的空穴(用于消除热应力)可使冷却剂便于流动,因而可以便于对组件进行增强冷却。
在本说明书的末尾部分具体地指出有关本发明的项目内容和明确地提出要求。参照下面的详细描述和附图,可以很好地理解本发明及其目的和优点。
图1是本发明的在平的主(非工作)面中具有槽的集成电路(IC)芯片的透视图;
图2是本发明的由众多的如图1的IC芯片所组成的电子组件的透视图;
图3是图2的电子组件的芯片间粘接处的放大的部分图;
图4是图3的电子组件在将侧面粘接到安装衬底后的透视图;
图5是在出现组件的热膨胀和膨胀层的膨胀后图4的电子组件的芯片间粘接处的放大的部分图;
图6是根据本发明的IC芯片的另一实施例的透视图,该IC芯片在平的主(非工作)面上具有槽,后者并不沿伸至芯片边缘;
图7是本发明的由众多例如图6的IC芯片组成的电子组件的透视图;
图8是本发明的具有在“Z方向”限制芯片移动的带的电子组件的透视图;
图9是本发明的电子组件的透视图,该电子组件的相对侧面上放置有两层弹性限制层;
图10是本发明的使用先进热化合物和粘合层的芯片间粘接处的剖面图;
图11是用于显示本发明中制造电子组件的方法的流程图;以及
图12是用于显示本发明中在芯片间使用先进热化合物制造电子组件的方法的流程图。
此处显示一些用于将由集成电路(IC)芯片叠装成的电子组件中的应力加以消除的最佳实施例。图1是一块IC芯片11的部分剖面图,它将被装入一个具有众多叠层集成电路芯片的电子组件中(也即众多芯片叠装成一块电子组件)。芯片可提供任何功能件,例如与电子组件有关的功能件。虽然芯片可包括任何用已知技术在半导体芯片上实现的功能件,但典型的可实现的功能件可包括例如存储器、接口、处理器(例如微处理器)及/或控制功能件。
如图1所示,IC芯片11用新型槽式结构组成。芯片的第一大体上平的主面具有在其中形成的众多槽,这些槽在芯片的非工作面上形成,并延伸进入IC芯片的衬底,可选方案是,可在芯片的绝缘层、或非工作面上淀积的其他层(或甚至于在工作面上类似地形成的保护层)内形成槽。在芯片背面非工作面形成的槽不会影响到大体上平的工作主面13。此处所用和一般技术中所用一样,芯片的“工作”面是用于在其上形成IC元件电路(例如半导体)的面,而IC芯片的“非工作”面则是没有任何如半导体那样的有源结构的面。
众多包括“带槽的”背面的IC芯片11叠装成一块电子组件21(图2)。叠装时使每块芯片的带槽的非工作主面粘结到相邻芯片的工作主面,从而使相邻芯片的非工作面和工作面互相面对面。末端集成电路芯片的非工作主面则与端盖17粘接在一起。
如图3所示,膨胀材料层23和粘合层24在机械上将芯片互相粘接在一起,当芯片最初粘接在一起时,芯片间放置的这些层并不填入槽内15。另外,膨胀材料层的厚度如此选择,以便在膨胀材料膨胀时,槽能容纳膨胀部分,膨胀材料可以包括市场上现成的具有低杨氏模量的高温膨胀材料,例如Dow Corning公司制造的High Temperature Silicone.粘合材料可以包括任何一种市场上现成的高温可流动粘合材料,例如National Starch ChemicalCompany,Bridgewater,NJ所生产的Thermid。
本发明一个实施例的下一个过程步骤是将电子组件粘接到安装衬底上。如图4所示,电子组件的侧面通过焊点27粘接到安装衬底29上。焊点和电子组件和安装衬底上的触点(都没有显示)都粘接在在一起。对应于组件的每一块芯片的金属成分,可用任何常用技术形成触点,例如形成“T连点”。因此每一块IC芯片都单独地粘接到组件上。安装衬底上的触点也可用众所周知的技术形成,例如标准衬底金属化。
将IC芯片粘接到安装衬底上,即将芯片牢固定位。因此在“Z方向”内(垂直于芯片的平的主面的方向)的芯片移动将受到限制。当组件运行而温度因而升高时,芯片和膨胀材料将开始膨胀。然而每一部分按照每一种材料相应的热膨胀率以不同速率膨胀。当膨胀材料膨胀时,它将产生将芯片相互推开的力(在“Z方向”内)。类似地,当芯片在“Z方向”膨胀时,芯片间用于放置膨胀材料的空间将变小。这将挤压膨胀材料,从而在“Z方向”产生附加力。然而由于芯片是粘死在安装衬底上,因此芯片无法移动来吸收相应的力。故而槽15提供一种手段,用于消除产生的应力(图5)。
当应力于“Z方向”内作用时,膨胀材料23受到挤压,并相应地膨胀到众多槽15内,如面23′所示。这种流动消除了挤压力,减轻了组件的总应力。在一个实施例中槽是如此设计,在纵的方向延伸跨越每个芯片的非工作面,然而也可用其他方案。事实上,根据本发明的技术,可用很多不同类型空穴来消除应力,例如众多凹穴和不同几何形状(例如图6所示,下面将讨论)。
作为本发明的一个扩充性能实施例,槽的尺寸可选用得便于冷却组件。以前曾用电子组件周围的液体流动或气体流动来冷却组件(例如,在94年5月3日授权的美国专利5,309,318的“热增强型半导体芯片封装”,及其中所引用内容)。本发明中,槽中允许液体或气体(一种“冷却剂”)流经组件,从而进一步增强组件的冷却,用于容纳冷却剂流通的槽的典型尺寸是125-250微米深和500-1000微米宽,当然冷却剂特性不同,尺寸也会变动。使用这类槽后,热量即从组件的每一块芯片内部传走,而不必经过芯片边缘传送再散去。
应注意并不是所有本发明的实施例允许冷却剂流经组件。例如,图6的芯片11的槽16并不延伸到芯片的边缘,因此当用这类芯片组成组件时(图7),组件侧面并不存在允许冷却剂流经组件的开口。
此处描述的消除应力的技术并不局限于只应用于包括叠层芯片的电子组件。该技术可应用于一个半导体结构(例如一块电子组件、一块芯片或一块衬底)安装在另一个半导体结构上的任何一种情况。例如,一块单片集成电路芯片可粘接到一块安装衬底上。由于衬底、IC芯片和膨胀材料的热膨胀率不同而引起的应力可因膨胀层膨胀进入位于芯片(或衬底)面内的槽中而减轻。可用不同封装技术将芯片紧固在衬底上(这将限制“Z方向”内膨胀,并增强粘合剂的流动)。
一种用于由IC芯片叠装成的电子组件的这类技术示于图8。粘合层41将带层43粘附到电子组件21′的面上。该带层用于控制电子组件在Z方向的热膨胀。槽15和膨胀层23(图5)一起用于减轻电子组件中由于带43对热膨胀施加阻力而引起的应力。硅和陶瓷是带材料的例子。
图9中是另一限制技术,在电子组件的两个相对的平行的侧面上淀积了限制膨胀层45和47,这类层的一侧是其典型膨胀系数处于3-10PPM/℃范围内的聚酰亚胺膜,该膜粘附于电子组件的侧面,可用众所周知的技术加以淀积,例如自旋溅射、蒸发和滚延,在电子组件21和焊点27间的限制层47用于在焊点附近控制膨胀,以减轻会导致破裂的应力。限制层47包括有穿孔(未示出),它们是用标准工业技术在绝缘层上蚀刻而成,用于在焊点27及电子组件上的电接触层(未示出)之间建立电气连接。
还有一种用于限制电子组件膨胀以减轻焊点应力的技术是将粘接到衬底的芯片加以密封。
在另外一个本发明实施例中,如图10所示,槽15和芯片间的空间可充有一种先进的热化合物(“ATC”)51。ATC是一种导热而在电气上绝缘的材料,它改善整个电子组件内的热量分布,从而减少总的温升(例如可参看授权1992年3月24日的美国专利5,098,609“稳定的高固体性高热传导性膏剂”,及其中所引用材料)。它也可减轻由于IC芯片在不同地点消耗不同功率而引起的局部热膨胀,图10的槽15增加了ATC和芯片之间的接触面积,因而增强了IC芯片间的热流动,然而,也可在不改变本实施例的工作原理的情况下忽略不用任何槽,一般认为IC芯片11上的所有绝缘层都可用ATC组成,从而在电子组件内部最大程度地分散热量,粘合层24可位于两块IC芯片11之间的任何地点,例如,如图所示位于一块IC芯片的一个主面上。
作为简要归纳,图11的流程图显示了一种用于形成本发明的电子组件的方法,提供的IC芯片具有背面(非工作面)槽31。其次,芯片粘接在一起形成一块电子组件33。具体说来,使用可流动粘合剂和膨胀材料层将每块芯片的其中有槽的非工作主面和相邻芯片的工作主面粘接起来(相邻芯片的大体上平的主面相对而平行地放置)。当组件构成后,它用焊点连接到安装衬底上,这提供了机械紧固35,从而在芯片、粘合剂和包括组件的膨胀材料层进行热膨胀时,使膨胀层膨胀入槽。还可如上面叙述那样,将附加限制层加到电子组件的面上。
在使用先进热化合物的本发明又一个实施例中,图12的流程图显示了一种用于形成这类电子组件的方法,所提供的众多IC芯片具有带有槽的主面61。如前面所述,在特定实施例中可忽略不用任何槽。芯片相互间用先进热化合物粘结在一起,从而形成一块电子组件63。具体说,如图10所示,每一片带有槽的芯片的非工作主面通过ATC和带槽面上的薄的可流动的粘合层与相邻芯片的工作主面粘结在一起。由于使用ATC得到电子组件的良好热分布,进而在本质上改善了热膨胀,因此不必要使用紧固技术使材料膨胀,然而为了外部电气连接,该组件可通过焊点连接到衬底上。
此处所描述的本发明的技术涉及到电子组件内部和有关连的焊点连接上热应力问题。下面是本发明提供优点的例子。
1.限制电子组件内部所产生的应力,但仍保证IC层之间的良好粘接。
2.在“Z方向”限制组件膨胀。
3.在带有膨胀槽的IC芯片上使用低杨氏模量的膨胀层,从而减轻焊点连接的应力。
4.通过减少电子组件的温度膨胀范围来减轻焊点的应力。一个方法是迫使冷却剂流经电子组件内的槽,从而冷却组件。另一个方法是使用一种先进热化合物,以便在整个电子组件内增强热量的均匀分布。
虽然本发明根据一定实施例加以详细描述,但技术熟练的人仍可做出许多更动和修改,相应地,所附权利要求书用来包括所有不背离本发明的真实实质和范围的更动和修改。
Claims (12)
1.一种电子组件,包括:
众多集成电路IC芯片,所述众多IC芯片的每一块IC芯片具有一个平的工作主面和一个平的非工作主面,所述众多IC芯片的第一IC芯片的平的非工作主面具有众多槽,所述众多IC芯片叠装成一块电子组件,其中所述平的工作主面都朝着一个共同方向;
一种膨胀材料,所述膨胀材料位于所述众多IC芯片的第二IC芯片的平的工作主面和所述众多IC芯片的第一IC芯片的所述平的非工作主面之间并在机械上将所述两个面粘接在一起,所述第二IC芯片具有第一热膨胀率和所述膨胀材料具有第二热膨胀率,所述第二热膨胀率不同于第一热膨胀率;以及
其中所述第一IC芯片的所述平的非工作主面中的所述众多槽提供众多空间,供所述膨胀材料膨胀进入,以便消除由于所述膨胀材料和所述第二集成电路芯片之间不同热膨胀的所述差别而引起的应力。
2.权利要求1的电子组件,其特征在于:进一步包括一个机械限制装置,用于阻止电子组件在垂直于所述众多IC芯片的每片IC芯片的平的主面的方向内膨胀。
3.权利要求1的电子组件,其特征在于:所述第一IC芯片中的所述众多槽的尺寸可供冷却剂流通。
4.权利要求1的电子组件,其特征在于:进一步包括一种膨胀材料,所述膨胀材料位于所述众多IC芯片的第二IC芯片的平的非工作主面与所述众多IC芯片的第三IC芯片的平的工作主面之间并在机械上将所述两个面粘结在一起,第二IC芯片的所述平的非工作主面在其中具有众多的槽。
5.权利要求1的电子组件,其特征在于:进一步包括可流动粘合剂,所述粘合剂位于所述膨胀材料和所述第二IC芯片的所述平的工作主面之间并在机械上将所述两者粘接在一起。
6.权利要求1的电子组件,其特征在于:进一步包括可流动粘合剂,所述粘合剂位于所述膨胀材料与所述第一IC芯片的所述平的非工作主面之间并在机械上将所述两者粘接在一起。
7.一种电子组件,包括:
众多叠装的集成电路IC芯片,所述众多IC芯片的每一块IC芯片具有第一平的主面和第二平的主面,以及
一种先进热化合物,所述先进热化合物位于所述众多IC芯片的第一IC芯片的第一平的主面与所述众多IC芯片的第二IC芯片的第二平的主面之间并在机械上和所述两个面粘接在一起,所述先进热化合物导热并在电气上绝缘,
其中所述第一IC芯片的所述第一平的主面具有空穴,所述先进热化合物充入所述空穴。
8.权利要求7的电子组件,其特征在于:所述先进热化合物位于所述众多IC芯片的每一片IC芯片的第一平的主面与所述众多IC芯片的相邻IC芯片的第二平的主面之间并在机械上和所述两个面粘接在一起。
9.权利要求7的电子组件,其特征在于:所述空穴包括众多槽。
10.一种用于形成电子组件的方法,包括以下步骤:
(a)提供众多叠装的集成电路IC芯片,所述众多叠装IC芯片的每一块IC芯片具有第一平的主面和第二平的主面;以及
(b)使用一种先进热化合物将所述众多IC芯片的第一IC芯片的第一平的主面与所述众多IC芯片的第二IC芯片的第二平的面在机械上粘接在一起,所述先进热化合物导热并在电气上绝缘,
其中所述第一IC芯片的所述平的主面在其中具有空穴,所述粘接步骤(b)包括将所述空穴充以所述先进热化合物。
11.权利要求10的方法,其特征在于:所述粘接步骤(b)包括使用可流动粘合剂将所述先进热化合物与所述第一IC芯片的所述第一平的主面粘接在一起。
12.权利要求10的方法,其特征在于:所述空穴包括众多槽,以及所述粘接步骤(b)包括将所述槽充以所述先进热化合物。
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EP0348972A2 (en) * | 1988-07-01 | 1990-01-03 | Sharp Kabushiki Kaisha | A semiconductor device and a process for manufacturing thereof |
US5195020A (en) * | 1987-05-25 | 1993-03-16 | Fujitsu Limited | Cooling system used with an electronic circuit device for cooling circuit components included therein having a thermally conductive compound layer and method for forming the layer |
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US4451973A (en) * | 1981-04-28 | 1984-06-05 | Matsushita Electronics Corporation | Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor |
US4918511A (en) * | 1985-02-01 | 1990-04-17 | Advanced Micro Devices, Inc. | Thermal expansion compensated metal lead frame for integrated circuit package |
US4778950A (en) * | 1985-07-22 | 1988-10-18 | Digital Equipment Corporation | Anisotropic elastomeric interconnecting system |
US4706166A (en) * | 1986-04-25 | 1987-11-10 | Irvine Sensors Corporation | High-density electronic modules--process and product |
US4983533A (en) * | 1987-10-28 | 1991-01-08 | Irvine Sensors Corporation | High-density electronic modules - process and product |
US4952999A (en) * | 1988-04-26 | 1990-08-28 | National Semiconductor Corporation | Method and apparatus for reducing die stress |
US5098609A (en) * | 1989-11-03 | 1992-03-24 | The Research Foundation Of State Univ. Of N.Y. | Stable high solids, high thermal conductivity pastes |
JPH0779144B2 (ja) * | 1992-04-21 | 1995-08-23 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 耐熱性半導体チップ・パッケージ |
US5422435A (en) * | 1992-05-22 | 1995-06-06 | National Semiconductor Corporation | Stacked multi-chip modules and method of manufacturing |
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1994
- 1994-09-26 US US08/311,815 patent/US5506753A/en not_active Expired - Fee Related
-
1995
- 1995-06-16 MY MYPI95001641A patent/MY113073A/en unknown
- 1995-06-19 CN CN95107369A patent/CN1041579C/zh not_active Expired - Fee Related
- 1995-08-08 EP EP95480112A patent/EP0706219A1/en not_active Withdrawn
- 1995-09-14 JP JP7236351A patent/JP2818390B2/ja not_active Expired - Fee Related
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1998
- 1998-04-17 CN CN98106665A patent/CN1110094C/zh not_active Expired - Fee Related
Patent Citations (3)
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US4525921A (en) * | 1981-07-13 | 1985-07-02 | Irvine Sensors Corporation | High-density electronic processing package-structure and fabrication |
US5195020A (en) * | 1987-05-25 | 1993-03-16 | Fujitsu Limited | Cooling system used with an electronic circuit device for cooling circuit components included therein having a thermally conductive compound layer and method for forming the layer |
EP0348972A2 (en) * | 1988-07-01 | 1990-01-03 | Sharp Kabushiki Kaisha | A semiconductor device and a process for manufacturing thereof |
Also Published As
Publication number | Publication date |
---|---|
US5506753A (en) | 1996-04-09 |
CN1206227A (zh) | 1999-01-27 |
EP0706219A1 (en) | 1996-04-10 |
MY113073A (en) | 2001-11-30 |
JP2818390B2 (ja) | 1998-10-30 |
CN1041579C (zh) | 1999-01-06 |
CN1119788A (zh) | 1996-04-03 |
JPH08111502A (ja) | 1996-04-30 |
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