CN110995180A - Ultra-wideband microwave millimeter wave differential power amplifier - Google Patents
Ultra-wideband microwave millimeter wave differential power amplifier Download PDFInfo
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Abstract
The invention discloses an ultra-wideband microwave and millimeter wave differential power amplifier, which comprises an input end, an output end, an input matching network connected with the input end, an output matching network connected with the output end, and N power amplifying circuits connected in parallel between the input matching network and the output matching network, wherein N is the number of the power amplifying circuits in the power amplifier, and N is more than or equal to 1; each path of power amplifying circuit comprises Q differential power transistors, wherein Q is the stage number of the power amplifying circuit and is more than or equal to 1; two adjacent differential power transistors on the same path are connected through an interstage matching network; each differential power transistor comprises at least one pair of power transistors in a differential operation mode and a gain enhancement network. The invention enhances the anti-interference performance of the device, realizes the impedance matching of the large signal in the ultra-wide band, greatly improves the large signal working bandwidth of the amplifier and has high efficiency.
Description
Technical Field
The invention relates to a power amplifier, in particular to an ultra-wideband power amplifier.
Background
In recent years, with the gradual depletion of radio frequency spectrum and microwave low frequency spectrum resources, microwave and millimeter wave resources are more and more valued by workers related to military, civil, commercial and special fields.
The power amplifier is a key period in a microwave millimeter wave system, and mainly plays a role in enlarging and improving the output power of the system, the high output power can ensure that a system link has stronger anti-interference capability, better signal quality and farther system working radius, and the monolithic integration millimeter wave power amplifier based on the semiconductor process has the remarkable characteristics of high stability, miniaturization, low cost, low power consumption and the like, and plays a great role in the fields of communication, radar, special sensing application and the like.
With the continuous development of application requirements, modern microwave and millimeter wave systems put higher demands on power amplifiers, including:
1. and the output power is high, so that the working radius of the system and the anti-interference performance of a link are improved.
2. Wide operating band to satisfy the radio frequency bandwidth required by high data rate transmission.
3. High power added efficiency to meet the low power consumption requirement of the system.
Disclosure of Invention
The purpose of the invention is as follows: in order to solve the defects in the prior art, the invention provides an ultra-wideband microwave and millimeter wave differential power amplifier.
The technical scheme is as follows: in order to solve the technical problem, the invention provides an ultra-wideband microwave and millimeter wave differential power amplifier, which comprises an input end, an output end, an input matching network connected with the input end, an output matching network connected with the output end, and N power amplifying circuits connected in parallel between the input matching network and the output matching network, wherein N is the number of the power amplifying circuits in the power amplifier, and N is more than or equal to 1;
each path of power amplifying circuit comprises Q differential power transistors, wherein Q is the stage number of the power amplifying circuit and is more than or equal to 1; two adjacent differential power transistors on the same path are connected through an interstage matching network;
each differential power transistor comprises at least one pair of power transistors in a differential operation mode and a gain enhancement network.
Preferably, the input matching network, the interstage matching network and the output matching network are impedance matching networks providing input, interstage and output impedances required by the differential power transistor in an ultra-wideband microwave millimeter wave frequency range, respectively.
Preferably, the power transistor is a field effect transistor or a bipolar transistor.
Preferably, the gain enhancement network comprises a cross-interconnected capacitive feedback network inserted between differential input and output terminals of a pair of differential transistors.
As another preferred scheme, the gain enhancement network comprises a feedback transmission line and a blocking capacitor which are respectively connected to the input end and the output end of the same transistor in a pair of differential transistors.
As a further preferred scheme, the output matching network comprises M pairs of coupling transmission lines symmetrically arranged, wherein M is more than or equal to 1; the two coupling transmission lines in each pair are a left coupling transmission line and a right coupling transmission line; when M is 1, the output matching network comprises only 1 pair of mirror-symmetrically arranged coupled transmission lines:
the isolated ends of the two coupled transmission lines in the pair are connected through a second output matching capacitor C _ k 2; the isolated end of the left coupled transmission line of the pair is connected with the port OUTk +, and the isolated end of the right coupled transmission line of the pair is connected with the port OUTk-;
the straight-through ends of the two coupling transmission lines in the pair are connected and then connected with a port Ak through a first output microstrip transmission line TL _ Ak;
the coupling ends of the two coupling transmission lines in the pair are connected;
the input ends of the two coupled transmission lines in the pair are connected through a first output matching capacitor C _ k 1; the input of the left coupled transmission line of the pair is connected to port INk +, and the input of the right coupled transmission line of the pair is connected to port INk-;
when M is 2, the output matching network comprises 2 pairs of symmetrically arranged coupled transmission lines:
the input ends of the two coupled transmission lines in the left pair are connected through a third matching capacitor C _ K3; the input ends of the two coupling transmission lines in the right pair are connected through a fourth matching capacitor C _ K4; the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with a port INK1+, the input end of the right coupling transmission line in the left pair of coupling transmission lines is connected with a port INK1-, the input end of the left coupling transmission line in the right pair of coupling transmission lines is connected with a port INK2+, and the input end of the right coupling transmission line in the right pair of coupling transmission lines is connected with a port INK 2-;
the coupling ends of the two coupling transmission lines in the left pair are connected; the coupling ends of the two coupling transmission lines in the right pair are connected;
the straight-through ends of the two coupling transmission lines in the left pair are connected and then connected with a port AK through a second output microstrip transmission line TL _ AK; the straight-through ends of the two coupled transmission lines in the right pair are connected and then connected with a port BK through a third microstrip transmission line TL _ BK;
the isolation end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the isolation end of the right coupling transmission line in the right pair of coupling transmission lines through a third output matching capacitor C _ K5; the isolation end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the port OUTK +, and the isolation end of the right coupling transmission line in the right pair of coupling transmission lines is connected with the port OUTK-;
the isolated end of the right coupled transmission line in the left pair of coupled transmission lines is connected with the isolated end of the left coupled transmission line in the right pair of coupled transmission lines.
As a further preferred scheme, each differential power transistor at least comprises a pair of power transistors in a differential operation mode: a first power transistor M1 and a second power transistor M2;
the gain enhancement network comprises a first neutralization capacitor C1 and a second neutralization capacitor C2;
wherein the emitter of the first power transistor M1 is connected to ground, the collector is connected to port JOUT +, and the base is connected to port JIN +; wherein the emitter of the second power transistor M2 is connected to ground, the collector is connected to port JOUT-, and the base is connected to port JIN-;
the collector of the second power transistor M2 is connected to the base of the first power transistor M1 through a first neutralization capacitor C1; the collector of the first power transistor M1 is connected to the base of the second power transistor M2 through a second neutralization capacitor C2.
As a further preferred scheme, each differential power transistor at least comprises a pair of power transistors in a differential operation mode: a third power transistor M3 and a fourth power transistor M4;
the gain enhancement network comprises a third dc blocking capacitor C3, a fourth dc blocking capacitor C4, a third feedback transmission line TL3 and a fourth feedback transmission line TL 4;
wherein the emitter of the third power transistor M3 is grounded, the collector is connected to the port JOUT +, and the base is connected to the port JIN +; wherein the emitter of the fourth power transistor M4 is connected to ground, the collector is connected to port JOUT-, and the base is connected to port JIN-;
the collector of the third power transistor M3 is connected with the base of the third power transistor M3 through a third feedback transmission line TL3 and a third dc blocking capacitor C3 which are connected in series; the collector of the fourth power transistor M4 is connected to the base of the fourth power transistor M4 through a fourth feedback transmission line TL4 and a fourth dc blocking capacitor C4 connected in series.
Preferably, the input matching network, the interstage matching network and the output matching network all comprise a plurality of pairs of coupling transmission lines which are arranged in mirror symmetry, and microstrip transmission lines and matching capacitors which are matched with the coupling transmission lines;
the electrical parameters of all the coupled transmission lines in the same matching network are equal and the electrical length is less than 90 degrees;
the matching capacitor is a transistor parasitic capacitor or an MIM capacitor or an MOM capacitor;
wherein the microstrip transmission line is a DC bias network.
Preferably, the input matching network comprises N pairs of coupling transmission lines which are symmetrically arranged, wherein N is more than or equal to 1; the two coupling transmission lines in each pair are a left coupling transmission line and a right coupling transmission line;
when N is 1, the input matching network comprises only 1 pair of mirror-symmetrically arranged coupled transmission lines:
the isolated ends of the two coupled transmission lines in the pair are connected through a second matching capacitor; the isolated end of the left coupled transmission line of the pair is connected with the port OUTi +, and the isolated end of the right coupled transmission line of the pair is connected with the port OUTi-;
the straight-through ends of the two coupled transmission lines in the pair are connected;
the coupling ends of the two coupling transmission lines in the pair are connected, and then the ports Ai are connected through the first microstrip transmission lines TL _ Ai;
the input ends of the two coupling transmission lines in the pair are connected through a first matching capacitor; the input end of the left coupling transmission line in the pair is connected with the port INi +, and the input end of the right coupling transmission line in the pair is connected with the port INi-;
when N is 2, the input matching network includes 2 pairs of coupled transmission lines symmetrically arranged:
the isolated ends of the two coupled transmission lines in the left pair are connected through a fourth matching capacitor C _ I4; the isolated ends of the two coupled transmission lines in the right pair are connected through a fifth matching capacitor C _ I5; the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with the port OUTI1+, and the isolated end of the right coupled transmission line in the left pair of coupled transmission lines is connected with the port OUTI 1-; the isolated end of the left coupled transmission line in the right pair of coupled transmission lines is connected with the port OUTI2+, and the isolated end of the right coupled transmission line in the right pair of coupled transmission lines is connected with the port OUTI 2-;
the straight-through ends of the two coupling transmission lines in the left pair are connected; the straight-through ends of the two coupling transmission lines in the right pair are connected;
the coupling ends of the two coupling transmission lines in the left pair are connected and then connected with a port AI1 through a second microstrip transmission line TL _ AI 1; the coupling ends of the two coupling transmission lines in the right pair are connected and then connected with a port AI2 through a third microstrip transmission line TL _ AI 2;
the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the input end of the right coupling transmission line in the right pair of coupling transmission lines through a third matching capacitor C _ I3; the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the port INI +, and the input end of the right coupling transmission line in the right pair of coupling transmission lines is connected with the port INI-;
the input end of the right coupling transmission line in the left pair of coupling transmission lines is connected with the input end of the left coupling transmission line in the right pair of coupling transmission lines.
Preferably, the interstage matching network comprises L pairs of coupling transmission lines which are symmetrically arranged in a mirror mode, and L is larger than or equal to 1; the two coupling transmission lines in each pair are a left coupling transmission line and a right coupling transmission line;
when L is 1, the interstage matching network comprises only 1 pair of mirror-symmetrically arranged coupled transmission lines:
the isolated ends of the two coupled transmission lines in the pair are connected through a second interstage matching capacitor C _ j 2; the isolated end of the left coupled transmission line of the pair is connected with the port OUTj +, and the isolated end of the right coupled transmission line of each pair is connected with the port OUTj-;
the straight-through ends of the two coupling transmission lines in the pair are connected and then connected with a port Bj through a second interstage microstrip transmission line TL _ Bj;
the coupling ends of the two coupling transmission lines in the pair are connected and then connected with a port Aj through a first interstage microstrip transmission line TL _ Aj;
the input ends of the two coupled transmission lines in the pair are connected through a first interstage matching capacitor C _ j 1; the input of the left coupled transmission line of the pair is connected to port INj +, and the input of the right coupled transmission line of the pair is connected to port INj-;
when L is 2, the interstage matching network comprises 2 pairs of coupled transmission lines arranged symmetrically:
the isolated ends of the two coupled transmission lines in the left pair are connected through a fifth interstage matching capacitor C _ J5;
the isolated ends of the two coupled transmission lines in the right pair are connected through a sixth interstage matching capacitor C _ J6;
the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with the port OUTJ1+, and the isolated end of the right coupled transmission line in the left pair of coupled transmission lines is connected with the port OUTJ 1-; the isolated end of the left coupled transmission line in the right pair of coupled transmission lines is connected with the port OUTJ2+, and the isolated end of the right coupled transmission line in the right pair of coupled transmission lines is connected with the port OUTJ 2-;
the straight-through ends of two coupling transmission lines in the left pair are connected and then connected with a port BJ1 through a fifth interstage microstrip transmission line TL _ BJ 1; the straight-through ends of the two coupling transmission lines in the right pair are connected and then connected with a port BJ2 through a sixth interstage microstrip transmission line TL _ BJ 2;
the coupling ends of the two coupling transmission lines in the left pair are connected and then connected with a port AJ1 through a third interstage microstrip transmission line TL _ AJ 1; the coupling ends of the two coupling transmission lines in the right pair are connected and then connected with a port AJ2 through a fourth interstage microstrip transmission line TL _ AJ 2;
the input ends of the two coupled transmission lines in the left pair are connected through a third interstage matching capacitor C _ J3;
the input ends of the two coupling transmission lines in the right pair are connected through a fourth interstage matching capacitor C _ J4;
the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the port INJ1+, and the input end of the right coupling transmission line in the left pair of coupling transmission lines is connected with the port INJ 1-; the input of the left coupled transmission line of the right pair of coupled transmission lines is connected to port INJ2+, and the input of the right coupled transmission line of the right pair of coupled transmission lines is connected to port INJ 2-.
Has the advantages that: compared with the prior art, the ultra-wideband microwave millimeter wave differential power amplifier provided by the invention has the following advantages:
1. differential mode of operation provides greater output power relative to single-ended mode;
2. the differential working mode utilizes the characteristic that two paths of signals are opposite in phase, so that the feedback capacitor in the transistor can be compensated through an external passive network, and the power gain of the transistor is further improved;
3. the differential mode of operation provides a virtual ground on the central symmetry line of the circuit, thereby simplifying the complexity of the feed network and improving the immunity of the amplifier to external spurious signals.
4. The input and output matching network can provide a good electrostatic protection function for the input and output ends, and the anti-interference performance of the device is enhanced.
5. Furthermore, the microstrip coupling transmission line is utilized to realize a low-loss and miniaturized output impedance matching network, and the input impedance of the microstrip coupling transmission line tracks the optimal impedance value obtained by the load traction of the differential power transistor in the ultra-wide frequency band, so that the impedance matching of a large signal is realized in the ultra-wide frequency band, the large signal working bandwidth of the amplifier is greatly improved, and the microstrip coupling transmission line has the advantage of high efficiency.
Drawings
Fig. 1 is a schematic block diagram of a circuit structure of an ultra-wideband microwave and millimeter wave differential power amplifier provided by the invention;
fig. 2 is a schematic block diagram of a single-stage and two-stage differential power amplifier according to an embodiment;
fig. 3 is a schematic block diagram of a two-way two-stage differential power amplifier according to an embodiment;
FIG. 4 is a schematic diagram of the circuit structure of a differential power transistor in one embodiment;
FIG. 5 is a schematic diagram of a circuit configuration of a differential power transistor in another embodiment thereof;
fig. 6 is a schematic circuit diagram of an input matching network in a single-channel differential power amplifier according to an embodiment;
fig. 7 is a schematic circuit diagram of an inter-stage matching network in a single-channel differential power amplifier according to an embodiment;
fig. 8 is a schematic circuit diagram of an output matching network in a single-channel differential power amplifier according to an embodiment;
fig. 9 is a schematic circuit diagram of an input matching network in a two-way differential power amplifier according to an embodiment;
fig. 10 is a schematic circuit diagram of an inter-stage matching network in a two-way differential power amplifier according to an embodiment;
fig. 11 is a schematic circuit diagram of an output matching network in a two-way differential power amplifier according to an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following examples and drawings, but the present invention is not limited to the following examples.
The invention provides an ultra-wideband microwave and millimeter wave differential power amplifier, which comprises an input end, an output end, an input matching network connected with the input end, an output matching network connected with the output end and an N-path power amplifying circuit connected between the input matching network and the output matching network in parallel, as shown in figure 1. Wherein N is the number of the power amplifying circuits in the power amplifier, and N is more than or equal to 1.
Each path of power amplifying circuit comprises Q differential power transistors, wherein Q is the stage number of the power amplifying circuit and is more than or equal to 1; two adjacent differential power transistors located on the same path are connected through an inter-stage matching network.
Wherein each differential power transistor comprises at least one pair of power transistors in a differential operating mode and a gain enhancement network.
Fig. 2 shows a schematic structural diagram of a single-path two-stage ultra-wideband microwave and millimeter wave differential power amplifier provided in an embodiment, where N is 1 and Q is 2, and the single-path two-stage ultra-wideband microwave and millimeter wave differential power amplifier includes an input matching network connected to an input end, an output matching network connected to an output end, and a 1-path power amplifying circuit including a differential power transistor 1, a differential power transistor 2, and an inter-stage matching network. The structural connection of this embodiment is as follows: the input end of the input matching network is connected with a power signal source through the input end of the differential power amplifier, the output end of the input matching network is connected with the input end of the first-stage differential power transistor 1, the output end of the first-stage differential power transistor 1 is connected with the input end of the first-stage inter-stage matching network, the output end of the first-stage inter-stage matching network is connected with the input end of the second-stage differential power transistor 2, the output end of the second-stage differential power transistor 2 is connected with the input end of the output matching network, and finally the output end of the output matching network is connected with a load through. The input matching network and the interstage matching network may be in a common transmission line connection structure or a packaging structure, and may also be the input matching network and the interstage matching network described in the chinese patent application text with publication numbers CN110277965A, application dates of 2018, 3 and 15, and publication dates of 2019, 9 and 24, and the structures of the matching units in the prior art described in fig. 1 and 2.
Another embodiment of the present invention provides a schematic structural diagram of two-stage ultra-wideband microwave and millimeter wave differential power amplifiers with N being 2 and Q being 2, as shown in fig. 3, which includes an input matching network connected to an input end, an output matching network connected to an output end, and 2 power amplification circuits, where each power amplification circuit includes a differential power transistor 1, a differential power transistor 2, and an inter-stage matching network. In the structural connection relationship of this embodiment, the circuit structure of each power amplifier circuit is the same as that of the power amplifier circuit in the previous embodiment, and details are not repeated here. The input matching network and the interstage matching network may be in a common transmission line connection structure or a packaging structure, and may also be the input matching network and the interstage matching network described in the chinese patent application text with publication numbers CN110277965A, application dates of 2018, 3 and 15, and publication dates of 2019, 9 and 24, and the structures of the matching units in the prior art described in fig. 1 and 2.
The input matching network, the interstage matching network and the output matching network are impedance matching networks which respectively provide input impedance, interstage impedance and output impedance needed by the differential power transistor in the ultra-wideband microwave millimeter wave frequency range. In each input matching network, interstage matching network and output matching network, the impedance transformation of broadband is realized by controlling the characteristic impedance of odd mode and even mode of coupling transmission line in the network and making the electrical length of the impedance transformation less than quarter wavelength.
Wherein the power transistor adopts a field effect transistor or a bipolar transistor.
In some embodiments, the gain enhancement network comprises a cross-interconnected capacitive feedback network interposed between differential input and output terminals of a pair of differential transistors. Specifically, in this embodiment, as shown in fig. 4, each of the differential power transistors at least includes a pair of power transistors in a differential operation mode: a first power transistor M1 and a second power transistor M2; the gain enhancement network comprises a first neutralization capacitor C1 and a second neutralization capacitor C2; the emitter of the first power transistor M1 is grounded, the collector is connected to the output port JOUT +, and the base is connected to the input port JIN +; wherein the emitter of the second power transistor M2 is grounded, the collector is connected to the output port JOUT-, and the base is connected to the input port JIN-; the collector of the second power transistor M2 is connected to the base of the first power transistor M1 through a first neutralization capacitor C1; the collector of the first power transistor M1 is connected to the base of the second power transistor M2 through a second neutralization capacitor C2. Namely: one end of the first neutralization capacitor C1 is connected with the base of the first power transistor M1, and the other end is connected with the collector of the second power transistor M2; the second neutralization capacitor C2 has one end connected to the base of the second power transistor M2 and the other end connected to the collector of the first power transistor M1. The working principle of the gain enhancement network is that the first and second neutralization capacitors are equivalent to inductance by means of cross interconnection by utilizing a pair of inverted signals provided by a differential working mode. The equivalent inductor resonates with the base-collector capacitance inside the power transistor, thereby eliminating the negative feedback loop of the transistor, thereby enhancing the power gain of the differential power transistor.
In some embodiments, the gain enhancement network includes a feedback transmission line and a blocking capacitor respectively connected to the input and output terminals of the same transistor in the differential pair of transistors. Specifically, in this embodiment, as shown in fig. 5, each of the differential power transistors at least includes a pair of power transistors in a differential operation mode: a third power transistor M3 and a fourth power transistor M4; the gain enhancement network includes a third dc blocking capacitor C3, a fourth dc blocking capacitor C4, a third feedback transmission line TL3, and a fourth feedback transmission line TL 4. The emitter of the third power transistor M3 is grounded, the collector is connected to the output port JOUT +, and the base is connected to the input port JIN +; wherein the emitter of the fourth power transistor M4 is grounded, the collector is connected to the output port JOUT-, and the base is connected to the input port JIN-; the collector of the third power transistor M3 is connected with the base of the third power transistor M3 through a third feedback transmission line TL3 and a third dc blocking capacitor C3 which are connected in series; the collector of the fourth power transistor M4 is connected to the base of the fourth power transistor M4 through a fourth feedback transmission line TL4 and a fourth dc blocking capacitor C4 connected in series. Namely: one end of the third dc blocking capacitor C3 is connected to the base of the third power transistor M3, the other end is connected to one end of the third feedback transmission line TL3, and the other end of the third feedback transmission line TL3 is connected to the collector of the third power transistor M3; one end of the fourth dc blocking capacitor C4 is connected to the base of the fourth power transistor M4, the other end is connected to one end of a fourth feedback transmission line TL4, and the other end of the fourth feedback transmission line TL4 is connected to the collector of the fourth power transistor M4. This structure has a greater degree of freedom in design than the structure shown in the previous embodiment (fig. 4), and can further improve the gain of the transistor in the target operating frequency range. The network not only can realize the performance of the structure shown in the previous embodiment (fig. 4), but also can provide a proper positive feedback loop for the differential power transistor, so that the gain is further improved on the premise of ensuring the stability of the differential power transistor.
The input matching network, the interstage matching network and the output matching network respectively comprise a plurality of pairs of coupling transmission lines which are arranged in mirror symmetry, and microstrip transmission lines and matching capacitors which are matched with the coupling transmission lines.
In the invention, the output matching network comprises M pairs of coupling transmission lines which are symmetrically arranged in a mirror manner, wherein M is more than or equal to 1; the two coupled transmission lines in each pair are a left coupled transmission line and a right coupled transmission line.
In the invention, the input matching network comprises N pairs of coupling transmission lines which are symmetrically arranged in a mirror manner, wherein N is more than or equal to 1; the two coupled transmission lines in each pair are a left coupled transmission line and a right coupled transmission line.
In the invention, the interstage matching network comprises L pairs of coupling transmission lines which are symmetrically arranged by mirrors, wherein L is more than or equal to 1; the two coupled transmission lines in each pair are a left coupled transmission line and a right coupled transmission line.
When M ═ N ═ L ═ 1, and Q ═ 2, the structure of the single-path two-stage ultra-wideband microwave and millimeter wave differential power amplifier provided in this embodiment is schematically shown in fig. 2. Specifically in this embodiment:
in this case, M is 1, the output matching network includes only 1 pair of coupling transmission lines symmetrically arranged as shown in fig. 8, specifically: the isolated ends of the two coupled transmission lines in the pair are connected through a second output matching capacitor C _ k 2; the isolated end of the left coupling transmission line of the pair is connected with the output port OUTk +, and the isolated end of the right coupling transmission line of the pair is connected with the output port OUTk-; the straight-through ends of the two coupling transmission lines in the pair are connected and then connected with a port Ak through a first output microstrip transmission line TL _ Ak; the coupling ends of the two coupling transmission lines in the pair are connected; the input ends of the two coupled transmission lines in the pair are connected through a first output matching capacitor C _ k 1; the input of the left coupled transmission line of the pair is connected to input port INk +, and the input of the right coupled transmission line of the pair is connected to input port INk-.
At this time, N is 1, the input matching network includes only 1 pair of coupling transmission lines symmetrically arranged as shown in fig. 6, specifically: the isolated ends of the two coupled transmission lines in the pair are connected through a second matching capacitor; the isolated end of the left coupling transmission line of the pair is connected with the output port OUTi +, and the isolated end of the right coupling transmission line of the pair is connected with the output port OUTi-; the straight-through ends of the two coupled transmission lines in the pair are connected; the coupling ends of the two coupling transmission lines in the pair are connected, and then the ports Ai are connected through the first microstrip transmission lines TL _ Ai; the input ends of the two coupling transmission lines in the pair are connected through a first matching capacitor; the input end of the left coupled transmission line of the pair is connected to the input port INi +, and the input end of the right coupled transmission line of the pair is connected to the input port INi-.
In this case, L is 1, the inter-stage matching network includes only 1 pair of coupled transmission lines symmetrically arranged as shown in fig. 7, specifically: the isolated ends of the two coupled transmission lines in the pair are connected through a second interstage matching capacitor C _ j 2; the isolated end of the left coupled transmission line of the pair is connected with the port OUTj +, and the isolated end of the right coupled transmission line of each pair is connected with the port OUTj-; the straight-through ends of the two coupling transmission lines in the pair are connected and then connected with an output port Bj through a second interstage microstrip transmission line TL _ Bj; the coupling ends of the two coupling transmission lines in the pair are connected and then connected with an output port Aj through a first interstage microstrip transmission line TL _ Aj; the input ends of the two coupled transmission lines in the pair are connected through a first interstage matching capacitor C _ j 1; the input of the left coupled transmission line of the pair is connected to input port INj +, and the input of the right coupled transmission line of the pair is connected to input port INj-.
When M is equal to N is equal to L is equal to 2, and Q is equal to 2, the two-way two-stage uwb microwave and millimeter wave differential power amplifier provided in this embodiment has a schematic structure as shown in fig. 3. Specifically in this embodiment:
at this time, M is 2, and the output matching network includes 2 pairs of coupling transmission lines symmetrically arranged as shown in fig. 11, specifically:
the input ends of the two coupled transmission lines in the left pair are connected through a third matching capacitor C _ K3; the input ends of the two coupling transmission lines in the right pair are connected through a fourth matching capacitor C _ K4; the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the input port INK1+, the input end of the right coupling transmission line in the left pair of coupling transmission lines is connected with the input port INK1-, the input end of the left coupling transmission line in the right pair of coupling transmission lines is connected with the input port INK2+, and the input end of the right coupling transmission line in the right pair of coupling transmission lines is connected with the input port INK 2-;
the coupling ends of the two coupling transmission lines in the left pair are connected; the coupling ends of the two coupling transmission lines in the right pair are connected;
the straight-through ends of the two coupling transmission lines in the left pair are connected and then connected with a port AK through a second output microstrip transmission line TL _ AK; the straight-through ends of the two coupled transmission lines in the right pair are connected and then connected with a port BK through a third microstrip transmission line TL _ BK;
the isolation end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the isolation end of the right coupling transmission line in the right pair of coupling transmission lines through a third output matching capacitor C _ K5; the isolation end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the output port OUTK +, and the isolation end of the right coupling transmission line in the right pair of coupling transmission lines is connected with the output port OUTK-;
the isolated end of the right coupled transmission line in the left pair of coupled transmission lines is connected with the isolated end of the left coupled transmission line in the right pair of coupled transmission lines.
At this time, N is 2, and the input matching network includes 2 pairs of coupling transmission lines symmetrically arranged as shown in fig. 9, specifically:
the isolated ends of the two coupled transmission lines in the left pair are connected through a fourth matching capacitor C _ I4; the isolated ends of the two coupled transmission lines in the right pair are connected through a fifth matching capacitor C _ I5; the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with the output port OUTI1+, and the isolated end of the right coupled transmission line in the left pair of coupled transmission lines is connected with the output port OUTI 1-; the isolated end of the left coupled transmission line of the right pair of coupled transmission lines is connected to output port OUTI2+, and the isolated end of the right coupled transmission line of the right pair of coupled transmission lines is connected to output port OUTI 2-.
The method specifically comprises the following steps: the isolation end of the left coupling transmission line and the isolation end of the right coupling transmission line in the left pair of coupling transmission lines are connected through a fourth matching capacitor C _ I4; the isolated end of the left coupling transmission line and the isolated end of the right coupling transmission line in the right pair of coupling transmission lines are connected through a fifth matching capacitor C _ I5.
The straight-through ends of the two coupling transmission lines in the left pair are connected; the straight-through ends of the two coupling transmission lines in the right pair are connected; namely specifically: the straight-through end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the straight-through end of the right coupling transmission line; the straight-through end of the left coupling transmission line in the pair of coupling transmission lines on the right side is connected with the straight-through end of the right coupling transmission line.
The coupling ends of the two coupling transmission lines in the left pair are connected and then connected with a port AI1 through a second microstrip transmission line TL _ AI 1; the coupling ends of the two coupling transmission lines in the right pair are connected and then connected with a port AI2 through a third microstrip transmission line TL _ AI 2; namely: the coupling end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the coupling end of the right coupling transmission line and then is connected with a port AI1 through a second microstrip transmission line TL _ AI 1; the coupling end of the left coupling transmission line and the coupling end of the right coupling transmission line in the pair of coupling transmission lines on the right side are connected and then connected with a port AI2 through a third microstrip transmission line TL _ AI 2;
the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the input end of the right coupling transmission line in the right pair of coupling transmission lines through a third matching capacitor C _ I3; the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the input port INI +, and the input end of the right coupling transmission line in the right pair of coupling transmission lines is connected with the input port INI-;
the input end of the right coupling transmission line in the left pair of coupling transmission lines is connected with the input end of the left coupling transmission line in the right pair of coupling transmission lines.
In this case, L is 2, and the inter-stage matching network includes 2 pairs of coupled transmission lines symmetrically arranged as shown in fig. 10, specifically:
the isolated ends of the two coupled transmission lines in the left pair are connected through a fifth interstage matching capacitor C _ J5;
the isolated ends of the two coupled transmission lines in the right pair are connected through a sixth interstage matching capacitor C _ J6;
the isolated end of the left coupled transmission line of the left pair of coupled transmission lines is connected to the output port OUTJ1+,
the isolated end of the right coupling transmission line in the left pair of coupling transmission lines is connected with the output port OUTJ 1-;
the isolated end of the left coupled transmission line of the right pair of coupled transmission lines is connected to the output port OUTJ2+,
the isolated end of the right coupling transmission line in the right pair of coupling transmission lines is connected with the output port OUTJ 2-;
the straight-through ends of two coupling transmission lines in the left pair are connected and then connected with a port BJ1 through a fifth interstage microstrip transmission line TL _ BJ 1; the straight-through ends of the two coupling transmission lines in the right pair are connected and then connected with a port BJ2 through a sixth interstage microstrip transmission line TL _ BJ 2;
the coupling ends of the two coupling transmission lines in the left pair are connected and then connected with a port AJ1 through a third interstage microstrip transmission line TL _ AJ 1; the coupling ends of the two coupling transmission lines in the right pair are connected and then connected with a port AJ2 through a fourth interstage microstrip transmission line TL _ AJ 2;
the input ends of the two coupled transmission lines in the left pair are connected through a third interstage matching capacitor C _ J3;
the input ends of the two coupling transmission lines in the right pair are connected through a fourth interstage matching capacitor C _ J4;
the input end of the left coupled transmission line in the left pair of coupled transmission lines is connected with the input port INJ1+, and the input end of the right coupled transmission line in the left pair of coupled transmission lines is connected with the input port INJ 1-; the input of the left coupled transmission line of the right pair of coupled transmission lines is connected to input port INJ2+, and the input of the right coupled transmission line of the right pair of coupled transmission lines is connected to input port INJ 2-.
In this embodiment, the coupled transmission lines in the same matching network have equal electrical parameters and an electrical length of less than 90 degrees. The matching capacitor is a transistor parasitic capacitor or an MIM capacitor or an MOM capacitor. Wherein the microstrip transmission line is a DC bias network. Namely: the electrical parameters of all the coupled transmission lines in the same input matching network are equal and the electrical length is less than 90 degrees; the electrical parameters of all coupling transmission lines in the same interstage matching network are equal, and the electrical length of the coupling transmission lines is less than 90 degrees; the coupled transmission lines in the same output matching network have equal electrical parameters and an electrical length less than 90 degrees.
The above is only a preferred embodiment of the present invention, it should be noted that the above embodiment does not limit the present invention, and various changes and modifications made by workers within the scope of the technical idea of the present invention fall within the protection scope of the present invention.
Claims (10)
1. An ultra wide band microwave millimeter wave differential power amplifier is characterized in that: the power amplifier comprises an input end, an output end, an input matching network connected with the input end, an output matching network connected with the output end, and N power amplifying circuits connected in parallel between the input matching network and the output matching network, wherein N is the number of paths of the power amplifying circuits in the power amplifier, and N is more than or equal to 1;
each path of power amplifying circuit comprises Q differential power transistors, wherein Q is the stage number of the power amplifying circuit and is more than or equal to 1; two adjacent differential power transistors on the same path are connected through an interstage matching network;
each differential power transistor comprises at least one pair of power transistors in a differential operation mode and a gain enhancement network.
2. The ultra-wideband microwave millimeter wave differential power amplifier of claim 1, characterized in that: the input matching network, the interstage matching network and the output matching network are impedance matching networks which respectively provide input impedance, interstage impedance and output impedance needed by the differential power transistor in the ultra-wideband microwave millimeter wave frequency range.
3. The ultra-wideband microwave millimeter wave differential power amplifier of claim 1, characterized in that: the power transistor is a field effect transistor or a bipolar transistor.
4. The ultra-wideband microwave millimeter wave differential power amplifier of claim 1, characterized in that: the gain enhancement network comprises a cross-interconnected capacitive feedback network inserted at the differential input and output terminals of a pair of differential transistors; or
The gain enhancement network comprises a feedback transmission line and a blocking capacitor which are respectively connected with the input end and the output end of the same transistor in a pair of differential transistors.
5. The ultra-wideband microwave millimeter wave differential power amplifier of claim 1, characterized in that: the output matching network comprises M pairs of coupling transmission lines which are symmetrically arranged, wherein M is more than or equal to 1; the two coupling transmission lines in each pair are a left coupling transmission line and a right coupling transmission line;
when M is 1, the output matching network comprises only 1 pair of mirror-symmetrically arranged coupled transmission lines:
the isolated ends of the two coupled transmission lines in the pair are connected through a second output matching capacitor C _ k 2; the isolated end of the left coupled transmission line of the pair is connected with the port OUTk +, and the isolated end of the right coupled transmission line of the pair is connected with the port OUTk-;
the straight-through ends of the two coupling transmission lines in the pair are connected and then connected with a port Ak through a first output microstrip transmission line TL _ Ak;
the coupling ends of the two coupling transmission lines in the pair are connected;
the input ends of the two coupled transmission lines in the pair are connected through a first output matching capacitor C _ k 1; the input of the left coupled transmission line of the pair is connected to port INk +, and the input of the right coupled transmission line of the pair is connected to port INk-;
when M is 2, the output matching network comprises 2 pairs of symmetrically arranged coupled transmission lines:
the input ends of the two coupled transmission lines in the left pair are connected through a third matching capacitor C _ K3; the input ends of the two coupling transmission lines in the right pair are connected through a fourth matching capacitor C _ K4; the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with a port INK1+, the input end of the right coupling transmission line in the left pair of coupling transmission lines is connected with a port INK1-, the input end of the left coupling transmission line in the right pair of coupling transmission lines is connected with a port INK2+, and the input end of the right coupling transmission line in the right pair of coupling transmission lines is connected with a port INK 2-;
the coupling ends of the two coupling transmission lines in the left pair are connected; the coupling ends of the two coupling transmission lines in the right pair are connected;
the straight-through ends of the two coupling transmission lines in the left pair are connected and then connected with a port AK through a second output microstrip transmission line TL _ AK; the straight-through ends of the two coupled transmission lines in the right pair are connected and then connected with a port BK through a third microstrip transmission line TL _ BK;
the isolation end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the isolation end of the right coupling transmission line in the right pair of coupling transmission lines through a third output matching capacitor C _ K5; the isolation end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the port OUTK +, and the isolation end of the right coupling transmission line in the right pair of coupling transmission lines is connected with the port OUTK-;
the isolated end of the right coupled transmission line in the left pair of coupled transmission lines is connected with the isolated end of the left coupled transmission line in the right pair of coupled transmission lines.
6. The ultra-wideband microwave millimeter wave differential power amplifier of claim 1, characterized in that:
each differential power transistor at least comprises a pair of power transistors in a differential working mode: a first power transistor M1 and a second power transistor M2;
the gain enhancement network comprises a first neutralization capacitor C1 and a second neutralization capacitor C2;
wherein the emitter of the first power transistor M1 is connected to ground, the collector is connected to port JOUT +, and the base is connected to port JIN +; wherein the emitter of the second power transistor M2 is connected to ground, the collector is connected to port JOUT-, and the base is connected to port JIN-;
the collector of the second power transistor M2 is connected to the base of the first power transistor M1 through a first neutralization capacitor C1; the collector of the first power transistor M1 is connected to the base of the second power transistor M2 through a second neutralization capacitor C2.
7. The ultra-wideband microwave millimeter wave differential power amplifier of claim 1, characterized in that:
each differential power transistor at least comprises a pair of power transistors in a differential working mode: a third power transistor M3 and a fourth power transistor M4;
the gain enhancement network comprises a third dc blocking capacitor C3, a fourth dc blocking capacitor C4, a third feedback transmission line TL3 and a fourth feedback transmission line TL 4;
wherein the emitter of the third power transistor M3 is grounded, the collector is connected to the port JOUT +, and the base is connected to the port JIN +; wherein the emitter of the fourth power transistor M4 is connected to ground, the collector is connected to port JOUT-, and the base is connected to port JIN-;
the collector of the third power transistor M3 is connected with the base of the third power transistor M3 through a third feedback transmission line TL3 and a third dc blocking capacitor C3 which are connected in series; the collector of the fourth power transistor M4 is connected to the base of the fourth power transistor M4 through a fourth feedback transmission line TL4 and a fourth dc blocking capacitor C4 connected in series.
8. The ultra-wideband microwave millimeter wave differential power amplifier of claim 1, characterized in that: the input matching network, the interstage matching network and the output matching network respectively comprise a plurality of pairs of coupling transmission lines which are arranged in mirror symmetry, and microstrip transmission lines and matching capacitors which are matched with the coupling transmission lines;
the electrical parameters of all the coupled transmission lines in the same matching network are equal and the electrical length is less than 90 degrees;
the matching capacitor is a transistor parasitic capacitor or an MIM capacitor or an MOM capacitor;
wherein the microstrip transmission line is a DC bias network.
9. The ultra-wideband microwave millimeter wave differential power amplifier of claim 1, characterized in that:
the input matching network comprises N pairs of coupling transmission lines which are symmetrically arranged, wherein N is more than or equal to 1; the two coupling transmission lines in each pair are a left coupling transmission line and a right coupling transmission line;
when N is 1, the input matching network comprises only 1 pair of mirror-symmetrically arranged coupled transmission lines:
the isolated ends of the two coupled transmission lines in the pair are connected through a second matching capacitor; the isolated end of the left coupled transmission line of the pair is connected with the port OUTi +, and the isolated end of the right coupled transmission line of the pair is connected with the port OUTi-;
the straight-through ends of the two coupled transmission lines in the pair are connected;
the coupling ends of the two coupling transmission lines in the pair are connected, and then the ports Ai are connected through the first microstrip transmission lines TL _ Ai;
the input ends of the two coupling transmission lines in the pair are connected through a first matching capacitor; the input end of the left coupling transmission line in the pair is connected with the port INi +, and the input end of the right coupling transmission line in the pair is connected with the port INi-;
when N is 2, the input matching network includes 2 pairs of coupled transmission lines symmetrically arranged:
the isolated ends of the two coupled transmission lines in the left pair are connected through a fourth matching capacitor C _ I4; the isolated ends of the two coupled transmission lines in the right pair are connected through a fifth matching capacitor C _ I5; the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with the port OUTI1+, and the isolated end of the right coupled transmission line in the left pair of coupled transmission lines is connected with the port OUTI 1-; the isolated end of the left coupled transmission line in the right pair of coupled transmission lines is connected with the port OUTI2+, and the isolated end of the right coupled transmission line in the right pair of coupled transmission lines is connected with the port OUTI 2-;
the straight-through ends of the two coupling transmission lines in the left pair are connected; the straight-through ends of the two coupling transmission lines in the right pair are connected;
the coupling ends of the two coupling transmission lines in the left pair are connected and then connected with a port AI1 through a second microstrip transmission line TL _ AI 1; the coupling ends of the two coupling transmission lines in the right pair are connected and then connected with a port AI2 through a third microstrip transmission line TL _ AI 2;
the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the input end of the right coupling transmission line in the right pair of coupling transmission lines through a third matching capacitor C _ I3; the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the port INI +, and the input end of the right coupling transmission line in the right pair of coupling transmission lines is connected with the port INI-;
the input end of the right coupling transmission line in the left pair of coupling transmission lines is connected with the input end of the left coupling transmission line in the right pair of coupling transmission lines.
10. The ultra-wideband microwave millimeter wave differential power amplifier of claim 1, characterized in that: the interstage matching network comprises L pairs of coupling transmission lines which are symmetrically arranged in a mirror mode, wherein L is more than or equal to 1; the two coupling transmission lines in each pair are a left coupling transmission line and a right coupling transmission line;
when L is 1, the interstage matching network comprises only 1 pair of mirror-symmetrically arranged coupled transmission lines:
the isolated ends of the two coupled transmission lines in the pair are connected through a second interstage matching capacitor C _ j 2; the isolated end of the left coupled transmission line of the pair is connected with the port OUTj +, and the isolated end of the right coupled transmission line of each pair is connected with the port OUTj-;
the straight-through ends of the two coupling transmission lines in the pair are connected and then connected with a port Bj through a second interstage microstrip transmission line TL _ Bj;
the coupling ends of the two coupling transmission lines in the pair are connected and then connected with a port Aj through a first interstage microstrip transmission line TL _ Aj;
the input ends of the two coupled transmission lines in the pair are connected through a first interstage matching capacitor C _ j 1; the input of the left coupled transmission line of the pair is connected to port INj +, and the input of the right coupled transmission line of the pair is connected to port INj-;
when L is 2, the interstage matching network comprises 2 pairs of coupled transmission lines arranged symmetrically:
the isolated ends of the two coupled transmission lines in the left pair are connected through a fifth interstage matching capacitor C _ J5;
the isolated ends of the two coupled transmission lines in the right pair are connected through a sixth interstage matching capacitor C _ J6;
the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with the port OUTJ1+, and the isolated end of the right coupled transmission line in the left pair of coupled transmission lines is connected with the port OUTJ 1-; the isolated end of the left coupled transmission line in the right pair of coupled transmission lines is connected with the port OUTJ2+, and the isolated end of the right coupled transmission line in the right pair of coupled transmission lines is connected with the port OUTJ 2-;
the straight-through ends of two coupling transmission lines in the left pair are connected and then connected with a port BJ1 through a fifth interstage microstrip transmission line TL _ BJ 1; the straight-through ends of the two coupling transmission lines in the right pair are connected and then connected with a port BJ2 through a sixth interstage microstrip transmission line TL _ BJ 2;
the coupling ends of the two coupling transmission lines in the left pair are connected and then connected with a port AJ1 through a third interstage microstrip transmission line TL _ AJ 1; the coupling ends of the two coupling transmission lines in the right pair are connected and then connected with a port AJ2 through a fourth interstage microstrip transmission line TL _ AJ 2;
the input ends of the two coupled transmission lines in the left pair are connected through a third interstage matching capacitor C _ J3;
the input ends of the two coupling transmission lines in the right pair are connected through a fourth interstage matching capacitor C _ J4;
the input end of the left coupling transmission line in the left pair of coupling transmission lines is connected with the port INJ1+, and the input end of the right coupling transmission line in the left pair of coupling transmission lines is connected with the port INJ 1-; the input of the left coupled transmission line of the right pair of coupled transmission lines is connected to port INJ2+, and the input of the right coupled transmission line of the right pair of coupled transmission lines is connected to port INJ 2-.
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| CN201911406199.7A CN110995180A (en) | 2019-12-31 | 2019-12-31 | Ultra-wideband microwave millimeter wave differential power amplifier |
| PCT/CN2020/116263 WO2021135408A1 (en) | 2019-12-31 | 2020-09-18 | Ultra-wideband microwave and millimeter wave differential power amplifier |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112068635A (en) * | 2020-08-13 | 2020-12-11 | 成都天锐星通科技有限公司 | Global bias scheme and embedded current mirror amplifying circuit technology suitable for multi-channel phased array |
| WO2021135408A1 (en) * | 2019-12-31 | 2021-07-08 | 南京米乐为微电子科技有限公司 | Ultra-wideband microwave and millimeter wave differential power amplifier |
| WO2021135407A1 (en) * | 2019-12-31 | 2021-07-08 | 南京米乐为微电子科技有限公司 | Output matching network for differential power amplifier |
| CN113556092A (en) * | 2021-09-16 | 2021-10-26 | 深圳飞骧科技股份有限公司 | Radio frequency power amplifier based on transformer matching network |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116317978B (en) * | 2023-05-22 | 2023-07-21 | 广东工业大学 | Dual-mode power amplifier, power amplifying method and related equipment thereof |
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| KR101128486B1 (en) * | 2010-11-23 | 2012-03-27 | 포항공과대학교 산학협력단 | Power amplifier apparatus |
| CN107404294A (en) * | 2017-08-23 | 2017-11-28 | 广州慧智微电子有限公司 | A kind of output matching network circuit and amplifying circuit with directional coupler |
| CN107707209A (en) * | 2017-09-18 | 2018-02-16 | 曾传德 | High-gain broadband millimeter wave difference amplifier |
| CN110995180A (en) * | 2019-12-31 | 2020-04-10 | 南京米乐为微电子科技有限公司 | Ultra-wideband microwave millimeter wave differential power amplifier |
| CN210839488U (en) * | 2019-12-31 | 2020-06-23 | 南京米乐为微电子科技有限公司 | Ultra-wideband microwave millimeter wave differential power amplifier |
-
2019
- 2019-12-31 CN CN201911406199.7A patent/CN110995180A/en active Pending
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021135408A1 (en) * | 2019-12-31 | 2021-07-08 | 南京米乐为微电子科技有限公司 | Ultra-wideband microwave and millimeter wave differential power amplifier |
| WO2021135407A1 (en) * | 2019-12-31 | 2021-07-08 | 南京米乐为微电子科技有限公司 | Output matching network for differential power amplifier |
| CN112068635A (en) * | 2020-08-13 | 2020-12-11 | 成都天锐星通科技有限公司 | Global bias scheme and embedded current mirror amplifying circuit technology suitable for multi-channel phased array |
| CN112068635B (en) * | 2020-08-13 | 2021-08-27 | 成都天锐星通科技有限公司 | Multi-channel phased array |
| CN113556092A (en) * | 2021-09-16 | 2021-10-26 | 深圳飞骧科技股份有限公司 | Radio frequency power amplifier based on transformer matching network |
| CN113556092B (en) * | 2021-09-16 | 2021-12-31 | 深圳飞骧科技股份有限公司 | Radio frequency power amplifier based on transformer matching network |
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