CN111010090A

CN111010090A - Broadband active frequency doubler

Info

Publication number: CN111010090A
Application number: CN201911380832.XA
Authority: CN
Inventors: 刘尧; 潘晓枫; 胡远圣
Original assignee: Clp Guoji Nanfang Group Co ltd
Current assignee: Clp Guoji Nanfang Group Co ltd
Priority date: 2019-12-27
Filing date: 2019-12-27
Publication date: 2020-04-14
Anticipated expiration: 2039-12-27
Also published as: CN111010090B

Abstract

The invention discloses a broadband active frequency doubler. The frequency doubler comprises an active balun, a PUSH-PUSH frequency doubler unit and a broadband amplifying circuit; the active balun receives a single-ended signal, converts the single-ended signal into a double-ended differential signal and outputs the double-ended differential signal, and the two output signals are respectively connected to the PUSH-PUSH frequency doubling unit; two paths of frequency doubling signals generated by the PUSH-PUSH frequency doubling unit are output from a drain electrode, fundamental wave and odd harmonic signals are offset in opposite phases, and meanwhile, second harmonic signals are superposed in the same phase; the broadband amplifying circuit receives the output signal of the PUSH-PUSH frequency doubling unit and amplifies the output signal through the three-stage broadband amplifying circuit to finish the power output of the frequency doubling signal. The invention has the advantages of wide working bandwidth range, strong fundamental wave and third harmonic suppression capability, low power consumption, high output power, small circuit area and low process difficulty requirement.

Description

Broadband active frequency doubler

Technical Field

The invention belongs to the radio frequency microwave integrated circuit technology of microelectronics and solid electronics, in particular to a broadband active frequency doubler.

Background

Frequency multipliers are widely used in transmitters, frequency synthesizers and other information transmission and processing systems. The frequency multiplier is used in the transmitter to multiply the lower oscillation frequency generated by the crystal oscillator to the required carrier frequency, or multiply the low carrier frequency and small frequency deviation frequency modulation waves generated by the indirect frequency modulator to the high carrier frequency and large frequency deviation frequency modulation waves. In a frequency synthesizer, a frequency multiplier is used to generate stable oscillation signals of many frequencies from a stable oscillation frequency.

With the development of wireless communication technology, frequency multipliers are widely used in applications such as communication, radar, and frequency synthesis. The frequency multiplier can obtain a signal with high frequency and low phase noise from a low-frequency and high-performance oscillator. Compared with the mode that the oscillator directly generates the high-frequency signal, the mode that the low-frequency oscillator and the frequency multiplier are cascaded to obtain the high-frequency signal has lower phase noise, and the performance of the whole communication system is directly influenced by the quality of the design of the frequency multiplier.

Most of the traditional frequency multipliers are designed by adopting a single tube or a passive balun, and the design generally cannot give consideration to the aspects of efficiency, loss, bandwidth, output power, chip area, cost and the like.

Disclosure of Invention

The invention aims to provide a broadband active frequency doubler which has low power consumption, wide working bandwidth range, strong fundamental wave and third harmonic suppression capability, high output power, small circuit area and low process difficulty requirement.

The technical solution for realizing the purpose of the invention is as follows: a broadband active frequency doubler comprises an active balun, a PUSH-PUSH frequency doubler unit and a broadband amplifying circuit;

the active balun receives a single-ended signal, converts the single-ended signal into a double-ended differential signal and outputs the double-ended differential signal, and the two output signals are respectively connected to the PUSH-PUSH frequency doubling unit;

two paths of frequency doubling signals generated by the PUSH-PUSH frequency doubling unit are output from a drain electrode and synthesized to cancel fundamental wave and odd harmonic signals, and simultaneously, second harmonics are superposed in phase;

the broadband amplifying circuit receives the output signal of the PUSH-PUSH frequency doubling unit and amplifies the output signal through the three-stage broadband amplifying circuit to finish the power output of the frequency doubling signal.

Further, the single-ended signal is transmitted to the active balun through an input matching network.

As a specific example, the input matching network includes a first capacitor, a first inductor, a second inductor, and a first resistor; the input matching network is characterized in that a first capacitor and a second inductor are connected in series between the input end and the output end of the input matching network, the common end of the first capacitor and the second inductor is grounded through the first inductor, and the output end of the input matching network is grounded through a first resistor.

As a specific example, the active balun includes a first transistor, a second resistor, a third inductor, a fourth inductor, a third transistor, a fourth transistor, a first series capacitor, a second series capacitor, a first series resistor, a second series resistor, a fifth inductor, a third resistor, a second capacitor, a third capacitor, a fourth capacitor, a sixth inductor, and a seventh inductor;

the output end of the input matching network is connected with the grid electrode of a first transistor in the active balun, the first transistor is connected with the source electrode of a second transistor, the common end of the input matching network is connected with a second resistor and a third inductor in series and is grounded, and the grid electrode of the second transistor is grounded through a fourth inductor; the grid electrode of the third transistor is connected in series with the first series capacitor and the first series resistor to the source electrode of the third transistor; the common end of the first series capacitor and the first series resistor is connected to the drain electrode of the first transistor; the grid electrode of the fourth transistor is connected in series with a second series capacitor and a second series resistor to the source electrode of the fourth transistor, and the common end of the second series capacitor and the second series resistor is connected to the drain electrode of the second transistor; the drain electrodes of the third transistor and the fourth transistor are connected, the common end of the third transistor and the fourth transistor is sequentially connected with a fifth inductor, a third resistor and a second capacitor in series and grounded, and the common end of the fifth inductor and the third resistor is connected with a negative power-up port; the source electrode of the third transistor is respectively connected in series with a fourth capacitor and a seventh inductor to serve as a first differential output port of the active balun, and the source electrode of the fourth transistor is respectively connected in series with the third capacitor and a sixth inductor to serve as a second differential output port of the active balun.

As a specific example, an RC trimming network is arranged at a signal receiving end of the active balun, and the RC trimming network includes an RC trimming capacitor and an RC trimming resistor; the grid electrode of the first transistor in the active balun is connected with one end of an RC fine tuning capacitor in an RC fine tuning network, the other end of the RC fine tuning capacitor is connected with one end of an RC fine tuning resistor, and the other end of the RC fine tuning resistor is connected with the common end of the second resistor and the common end of the third inductor.

As a specific example, the PUSH-PUSH frequency doubling unit includes a fifth transistor, a sixth transistor, a first large resistor, and a second large resistor;

the first differential output port of the active balun is connected to the gate of the sixth transistor, and the second differential output port of the active balun is connected to the gate of the fifth transistor; the grid electrode of the sixth transistor is connected with the positive power-up port through the first large resistor, and the grid electrode of the fifth transistor is connected with the negative power-up port through the second large resistor, so that grid electrode bias is realized; the sources of the fifth transistor and the sixth transistor are both grounded, and the drains are connected to the output end of the PUSH-PUSH frequency doubling unit.

As a specific example, the broadband amplification circuit includes a seventh transistor, an eighth transistor, a ninth transistor, fifth to eighth capacitors, and eighth to eleventh inductors;

one end of a fifth capacitor in the broadband amplifying circuit is connected with the common end of the drain electrodes of the fifth transistor and the sixth transistor, the common end is connected with a positive power-up port through an eighth inductor, and meanwhile one ends of a ninth inductor, a tenth inductor and an eleventh inductor are respectively connected with the positive power-up port; the other end of the fifth capacitor is connected with the grid electrode of the seventh transistor, the source electrode of the seventh transistor is grounded, the drain electrode of the seventh transistor is connected with the other end of the ninth inductor and one end of the sixth capacitor, and the other end of the sixth capacitor is connected with the grid electrode of the eighth transistor; the source electrode of the eighth transistor is grounded, the drain electrode of the eighth transistor is connected with the other end of the tenth inductor and one end of the seventh capacitor, and the other end of the seventh capacitor is connected with the grid electrode of the ninth transistor; and the source electrode of the ninth transistor is grounded, the drain electrode of the ninth transistor is connected with the other end of the eleventh inductor and one end of the eighth capacitor, and the other end of the eighth capacitor is a signal output end.

Furthermore, the active balun realizes input matching through a power consumption circuit, the drains of the transistors are directly biased through resistors to increase the bandwidth, the sources of the two differential tube pairs are directly connected through a microstrip, resistors are connected in series between the microstrips to sense the ground, and the working performance and the bandwidth are adjusted through selecting the inductance value of the resistors.

Furthermore, the grids of a fifth transistor and a sixth transistor of the PUSH-PUSH frequency doubling unit are connected with a positive power-up port through a first large resistor and a second large resistor to be powered up to realize direct current bias, and the frequency doubling efficiency of the circuit is adjusted by selecting grid bias voltage; the drains of the fifth transistor and the sixth transistor are electrified through a choke inductor to realize direct current bias; the sources of the fifth transistor and the sixth transistor are grounded, the drains are connected, second harmonic signals at the frequency doubling output end are superposed in phase, and fundamental waves and odd harmonics are offset in opposite phase.

Further, the RC trimming network adjusts the balance of the active balun output signals by adjusting the values of the RC trimming capacitor and the RC trimming resistor; the broadband amplifying circuit is of a three-level common source amplifying structure, and the working performance and the bandwidth of the broadband amplifying circuit are adjusted by selecting element values.

Compared with the prior art, the invention has the following remarkable advantages: (1) the active balun output end adopts an active load to reduce the output impedance of the active balun output end, so that the voltage swing of the grid of the driving frequency multiplier is increased, and the power consumption is reduced; (2) the input amplitude and the phase of the active balun input end are improved by adopting an RC feedback network, so that the balance degree is improved; (3) the working bandwidth range is wide, the fundamental wave and third harmonic suppression capability is strong, the output power is large, the circuit topological structure is simple, and the process difficulty is low.

Drawings

Fig. 1 is a block diagram of a wideband active frequency doubler according to the present invention.

Fig. 2 is a circuit configuration diagram of the present invention.

FIG. 3 is a circuit layout of a 20-44 GHz broadband active frequency multiplier in the embodiment of the present invention.

Fig. 4 is a graph of fundamental output power when the input signal power is 2, 3, 4, and 5dBm in this order in the embodiment of the present invention.

Fig. 5 is a second harmonic output power curve diagram in the case of the input signal power of 2, 3, 4, 5dBm in sequence in the embodiment of the present invention.

Fig. 6 is a third harmonic output power curve diagram in the case of the input signal power of 2, 3, 4, and 5dBm in sequence in the embodiment of the present invention.

Fig. 7 is a graph comparing the output power of the fundamental, second harmonic and third harmonic at an input signal power of 5dBm in an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and specific examples.

With reference to fig. 1 and fig. 2, the present invention provides a wideband active frequency doubler, which includes an active balun, a PUSH-PUSH frequency doubler unit and a wideband amplifier circuit;

As a specific example, the input matching network includes a first capacitor C1, a first inductor L1, a second inductor L2, and a first resistor R1; a first capacitor C1 and a second inductor L2 are connected in series between the input end and the output end of the input matching network, the common end of the first capacitor C1 and the second inductor L2 is grounded through a first inductor L1, and the output end of the input matching network is grounded through a first resistor R1.

As a specific example, the active balun includes a first transistor AF1, a second transistor AF2, a second resistor R2, a third inductor L3, a fourth inductor L4, a third transistor AF3, a fourth transistor AF4, a first series capacitor Cf1, a second series capacitor Cf2, a first series resistor Rf1, a second series resistor Rf2, a fifth inductor L5, a third resistor R3, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a sixth inductor L6, and a seventh inductor L7;

the output end of the input matching network is connected with the grid of a first transistor AF1 in the active balun, the sources of the first transistor AF1 and a second transistor AF2 are connected, the common end is connected in series with a second resistor R2 and a third inductor L3 and is grounded, and the grid of the second transistor AF2 is grounded through a fourth inductor L4; the third transistor AF3 is used as an active load of the first transistor AF1, the fourth transistor AF4 is used as an active load of the second transistor AF2, and the gate of the third transistor AF3 is connected in series with the first series capacitor Cf1, the first series resistor Rf1 and the source of the third transistor AF 3; the common terminal of the first series capacitor Cf1 and the first series resistor Rf1 is connected to the drain of the first transistor AF 1; the gate of the fourth transistor AF4 is connected in series with the second series capacitor Cf2 and the second series resistor Rf2 to the source of the fourth transistor AF4, and the common end of the second series capacitor Cf2 and the second series resistor Rf2 is connected to the drain of the second transistor AF 2; the drains of the third transistor AF3 and the fourth transistor AF4 are connected, the common end is connected in series with a fifth inductor L5, a third resistor R3 and a second capacitor C2 in sequence and is grounded, and the common ends of the fifth inductor L5 and the third resistor R3 are connected with a positive power-up port VD; the source of the third transistor AF3 is connected in series with the fourth capacitor C4 and the seventh inductor L7 respectively as the first differential output port of the active balun, and the source of the fourth transistor AF4 is connected in series with the third capacitor C3 and the sixth inductor L6 respectively as the second differential output port of the active balun.

As a specific example, an RC trimming network is arranged at a signal receiving end of the active balun, and the RC trimming network includes an RC trimming capacitor Cs and an RC trimming resistor Rs; the grid electrode of the first transistor AF1 in the active balun is connected with one end of an RC trimming capacitor Cs in the RC trimming network, the other end of the RC trimming capacitor Cs is connected with one end of an RC trimming resistor Rs, and the other end of the RC trimming resistor Rs is connected with the common end of the second resistor R2 and the third inductor L3.

As a specific example, the PUSH-PUSH frequency doubling unit includes a fifth transistor AF5, a sixth transistor AF6, a first large resistor RG1, and a second large resistor RG 2;

the first differential output port of the active balun is connected to the gate of the sixth transistor AF6, and the second differential output port of the active balun is connected to the gate of the fifth transistor AF 5; the grid electrode of the sixth transistor AF6 is connected with the negative power-up port VG through a first large resistor RG1, the grid electrode of the fifth transistor AF5 is connected with the negative power-up port VG through a second large resistor RG2, and grid electrode biasing is achieved; the sources of the fifth transistor AF5 and the sixth transistor AF6 are both grounded, and the drains are connected to the output end of the PUSH-PUSH frequency doubling unit.

As a specific example, the broadband amplification circuit includes a seventh transistor AF7, an eighth transistor AF8, a ninth transistor AF9, fifth to eighth capacitors C5 to C8, and eighth to eleventh inductors L8 to L11;

one end of a fifth capacitor C5 in the broadband amplifying circuit is connected to the common drain terminal of the fifth transistor AF5 and the sixth transistor AF6, the common drain terminal is connected to the positive power-up port VD through an eighth inductor L8, and meanwhile, one ends of a ninth inductor L9, a tenth inductor L10 and an eleventh inductor L11 are respectively connected to the positive power-up port VD; the other end of the fifth capacitor C5 is connected to the gate of the seventh transistor AF7, the source of the seventh transistor AF7 is grounded, the drain is connected to the other end of the ninth inductor L9 and one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is connected to the gate of the eighth transistor AF 8; the source of the eighth transistor AF8 is grounded, the drain is connected to the other end of the tenth inductor L10 and one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is connected to the gate of the ninth transistor AF 9; the source of the ninth transistor AF9 is grounded, the drain is connected to the other end of the eleventh inductor L11 and one end of the eighth capacitor C8, and the other end of the eighth capacitor C8 is a signal output terminal.

Furthermore, the gates of the fifth transistor AF5 and the sixth transistor AF6 of the PUSH-PUSH frequency doubling unit are connected with the negative power-up port VG through the first large resistor RG1 and the second large resistor RG2 to be powered up to realize direct current bias, and the frequency doubling efficiency of the circuit is adjusted through the selection of the gate bias voltage; the drains of the fifth transistor AF5 and the sixth transistor AF6 are electrified through a choke inductor to realize direct current bias; the sources of the fifth transistor AF5 and the sixth transistor AF6 are grounded, the drains are connected, second harmonic signals at the frequency doubling output end are superposed in phase, and fundamental waves and odd harmonics are offset in opposite phases.

Further, the RC trimming network adjusts the balance of the active balun output signal by adjusting the values of an RC trimming capacitor Cs and an RC trimming resistor Rs; the broadband amplifying circuit is of a three-level common source amplifying structure, and the working performance and the bandwidth of the broadband amplifying circuit are adjusted by selecting element values.

Example 1

The embodiment discloses a 20-44 GHz broadband active frequency multiplier. The circuit structure block diagram is shown in fig. 1, and the whole circuit comprises an active balun, a PUSH-PUSH frequency doubling unit circuit and a broadband amplifying circuit.

As shown in fig. 2, the active balun effects conversion of a signal from single-ended to double-ended. The input matching circuit realizes the lossy bandpass matching through the first capacitor C1, the first inductor L1, the second inductor L2 and the first resistor R1 to obtain wider bandwidth. The sources of the first transistor AF1 and the second transistor AF2 are connected, and the second resistor R2 and the third inductor L3 are connected in series to the ground in the middle, so that the self-bias and active balun differential performance of the differential tube is improved. An Rs-Cs feedback network is connected in series between the gate of the first transistor AF1 and the common terminal of the second resistor R2 and the third inductor L3 to improve the amplitude and phase of the output differential signal and improve the balance. The gate of the second transistor AF2 is grounded through a small inductor. The output end of the active balun is connected in series with a pair of balanced transistors, namely a third transistor AF3 and a fourth transistor AF4, which serve as active loads. The drains of the third transistor AF3 and the fourth transistor AF4 are connected, and an LRC structure consisting of a fifth inductor L5, a third resistor R3 and a second capacitor C2 is connected in series to ground to achieve matching. A Rf-Cf feedback network is connected in series between the gate and source of the third transistor AF3 and the fourth transistor AF4 to extend the bandwidth. The drains of the first transistor AF1 and the second transistor AF2 are both connected to the common terminal of Rf and Cf respectively, and the frequency-doubled signal passes through the sources of the third transistor AF3 and the fourth transistor AF4 and is output by being connected in series with the third capacitor C3, the sixth inductor L6, the fourth capacitor C4 and the seventh inductor L6 respectively. The introduction of the active load obtains smaller output impedance, so that serious interstage mismatching can be generated when the active load is cascaded with the PUSH-PUSH frequency doubling unit, if a signal reflected back from the frequency doubling unit is superposed with an input signal in phase, the grid voltages of the fifth transistor AF5 and the sixth transistor AF6 at a connection point can be obviously improved, the voltage swing of the grid of the frequency doubling tube can be improved under the condition of not increasing the input power, and the frequency doubling efficiency is improved.

The frequency multiplication unit circuit adopts a PUSH-PUSH structure and is composed of a differential pair tube fifth transistor AF5 and a differential pair tube sixth transistor AF6, the phases of grid input signals of the two tubes are kept opposite through active balun and interstage matching, fundamental waves and odd harmonics at the output ends of the two tubes are mutually offset, and second harmonics are superposed and output in phase, so that high fundamental wave and odd harmonic suppression is realized.

In order to amplify the second harmonic signal output from the frequency doubling unit, a three-level cascade common source amplification structure is designed, and the structure has the characteristics of wide band, high gain, strong mismatch resistance and the like, and also has the output power.

The circuit layout of the 20-44 GHz broadband active frequency multiplier is shown in FIG. 3, and the layout mainly comprises GaAsPHEMT transistors, microstrip lines, resistors, capacitors, ground holes, power-up ports and radio frequency ports. The single-ended signal enters from a signal input port 1, is converted into a differential signal through an active balun 2 and is output, then is injected into a Push-Push frequency multiplication unit 3, and the two paths of signals enter a first-stage amplifier 4, a second-stage amplifier 5 and a third-stage amplifier 6 in sequence after frequency multiplication synthesis and are finally output from a signal output port 7. Two power-on ports 8 and 9 exist in the layout, and +5V voltage and-1V voltage are applied during testing respectively.

Fig. 4 to 7 are actually measured curves of the 20 to 44GHz broadband active frequency multiplier of the present invention, fig. 4 is a fundamental output power curve when the input signal power is sequentially 2, 3, 4, and 5dBm, fig. 5 and 6 are second harmonic and third harmonic output power curves in the same case, respectively, and fig. 7 is a comparison graph of fundamental, second harmonic, and third harmonic output power when the input signal power is 5 dBm. As can be seen from the figure, in the designed frequency band range, the second harmonic output power is high and relatively stable, can reach more than 18dBm, the in-band flatness is good, and the fundamental wave and the third harmonic suppression condition in the frequency band are good, the fundamental wave output power is basically below-5 dBm, and the third harmonic output power is basically below 0 dBm.

Claims

1. A broadband active frequency doubler is characterized by comprising an active balun, a PUSH-PUSH frequency doubler unit and a broadband amplifying circuit;

two paths of frequency doubling signals generated by the PUSH-PUSH frequency doubling unit are output from a drain electrode, fundamental wave and odd harmonic signals are offset in opposite phases, and meanwhile, second harmonic signals are superposed in the same phase;

2. The wideband active frequency doubler according to claim 1, wherein the single-ended signal is transmitted to the active balun through an input matching network.

3. The wideband active frequency doubler according to claim 2, wherein the input matching network comprises a first capacitor (C1), a first inductor (L1), a second inductor (L2), and a first resistor (R1); a first capacitor (C1) and a second inductor (L2) are connected in series between the input end and the output end of the input matching network, the common end of the first capacitor (C1) and the second inductor (L2) is grounded through a first inductor (L1), and the output end of the input matching network is grounded through a first resistor (R1).

4. The wideband active frequency doubler according to claim 1, 2 or 3, wherein the active balun comprises a first transistor (AF1), a second transistor (AF2), a second resistor (R2), a third inductor (L3), a fourth inductor (L4), a third transistor (AF3), a fourth transistor (AF4), a first series capacitor (Cf1), a second series capacitor (Cf2), a first series resistor (Rf1), a second series resistor (Rf2), a fifth inductor (L5), a third resistor (R3), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a sixth inductor (L6) and a seventh inductor (L7);

the output end of the input matching network is connected with the grid of a first transistor (AF1) in the active balun, the sources of the first transistor (AF1) and a second transistor (AF2) are connected, the common end is connected with a second resistor (R2) and a third inductor (L3) in series and is grounded, and the grid of the second transistor (AF2) is grounded through a fourth inductor (L4); the third transistor (AF3) is used as an active load of the first transistor (AF1), the fourth transistor (AF4) is used as an active load of the second transistor (AF2), and the gate of the third transistor (AF3) is connected in series with the first series capacitor (Cf1), the first series resistor (Rf1) and the source of the third transistor (AF 3); the common end of the first series capacitor (Cf1) and the first series resistor (Rf1) is connected to the drain of the first transistor (AF 1); the gate of the fourth transistor (AF4) is connected in series with the second series capacitor (Cf2) and the second series resistor (Rf2) to the source of the fourth transistor (AF4), and the common end of the second series capacitor (Cf2) and the second series resistor (Rf2) is connected to the drain of the second transistor (AF 2); the drain electrodes of the third transistor (AF3) and the fourth transistor (AF4) are connected, the common end of the third transistor (AF3) and the fourth transistor (AF4) is sequentially connected with a fifth inductor (L5), a third resistor (R3) and a second capacitor (C2) in series to be grounded, and the common end of the fifth inductor (L5) and the third resistor (R3) is connected with a positive power-up port (VD); the source of the third transistor (AF3) is respectively connected in series with the fourth capacitor (C4) and the seventh inductor (L7) to serve as a first differential output port of the active balun, and the source of the fourth transistor (AF4) is respectively connected in series with the third capacitor (C3) and the sixth inductor (L6) to serve as a second differential output port of the active balun.

5. The wideband active frequency doubler according to claim 4, wherein the signal input terminal of the active balun is provided with an RC trimming network, and the RC trimming network comprises an RC trimming capacitor (Cs) and an RC trimming resistor (Rs); the grid electrode of the first transistor (AF1) in the active balun is connected with one end of an RC trimming capacitor (Cs) in the RC trimming network, the other end of the RC trimming capacitor (Cs) is connected with one end of an RC trimming resistor (Rs), and the other end of the RC trimming resistor (Rs) is connected with the common end of the second resistor (R2) and the third inductor (L3).

6. The wideband active frequency doubler according to claim 4 or 5, wherein the PUSH-PUSH frequency doubling unit comprises a fifth transistor (AF5), a sixth transistor (AF6), a first big resistor (RG1), a second big resistor (RG 2);

the first differential output port of the active balun is connected to the gate of the sixth transistor (AF6), and the second differential output port of the active balun is connected to the gate of the fifth transistor (AF 5); the grid electrode of the sixth transistor (AF6) is connected with the negative power-on port (VG) through a first large resistor (RG1), and the grid electrode of the fifth transistor (AF5) is connected with the negative power-on port (VG) through a second large resistor (RG2), so that grid bias is realized; the sources of the fifth transistor (AF5) and the sixth transistor (AF6) are both grounded, and the drains are connected with the output end of the PUSH-PUSH frequency doubling unit.

7. The broadband active frequency doubler according to claim 6, wherein the broadband amplifying circuit comprises a seventh transistor (AF7), an eighth transistor (AF8), a ninth transistor (AF9), fifth to eighth capacitors (C5-C8), eighth to eleventh inductors (L8-L11);

one end of a fifth capacitor (C5) in the broadband amplifying circuit is connected with the common end of the drains of a fifth transistor (AF5) and a sixth transistor (AF6), the common end is connected with a positive power-up port (VD) through an eighth inductor (L8), and meanwhile one ends of a ninth inductor (L9), a tenth inductor (L10) and an eleventh inductor (L11) are respectively connected with the positive power-up port (VD); the other end of the fifth capacitor (C5) is connected with the gate of the seventh transistor (AF7), the source of the seventh transistor (AF7) is grounded, the drain of the seventh transistor is connected with the other end of the ninth inductor (L9) and one end of the sixth capacitor (C6), and the other end of the sixth capacitor (C6) is connected with the gate of the eighth transistor (AF 8); the source of the eighth transistor (AF8) is grounded, the drain of the eighth transistor is connected with the other end of the tenth inductor (L10) and one end of the seventh capacitor (C7), and the other end of the seventh capacitor (C7) is connected with the gate of the ninth transistor (AF 9); the source of the ninth transistor (AF9) is grounded, the drain is connected to the other end of the eleventh inductor (L11) and one end of the eighth capacitor (C8), and the other end of the eighth capacitor (C8) is a signal output terminal.

8. The wideband active frequency doubler according to claim 7, wherein the active balun implements input matching by a power consuming circuit, the drains of the transistors are biased directly by resistors to increase the bandwidth, the sources of the two differential transistor pairs are connected directly by microstrips, the resistors are connected in series between the microstrips to sense the ground, and the operating performance and bandwidth are adjusted by selecting the value of the resistor.

9. The wideband active frequency doubler according to claim 7, wherein the gates of the fifth transistor (AF5) and the sixth transistor (AF6) of the PUSH-PUSH frequency doubling unit are connected to the negative power-up port (VG) through the first large resistor (RG1) and the second large resistor (RG2) to realize DC bias, and the frequency doubling efficiency of the circuit is adjusted by selecting the gate bias voltage; the drains of the fifth transistor (AF5) and the sixth transistor (AF6) are electrified through a choke inductor to realize direct current bias; the sources of the fifth transistor (AF5) and the sixth transistor (AF6) are grounded, the drains are connected, second harmonic signals at the frequency doubling output end are superposed in phase, and fundamental waves and odd harmonics are cancelled in opposite phases.

10. The wideband active frequency doubler according to claim 7, wherein the RC trimming network adjusts the balance of the active balun output signal by adjusting the values of an RC trimming capacitor (Cs) and an RC trimming resistor (Rs); the broadband amplifying circuit is of a three-level common source amplifying structure, and the working performance and the bandwidth of the broadband amplifying circuit are adjusted by selecting element values.