WO2021135408A1 - Ultra-wideband microwave and millimeter wave differential power amplifier - Google Patents

Ultra-wideband microwave and millimeter wave differential power amplifier Download PDF

Info

Publication number
WO2021135408A1
WO2021135408A1 PCT/CN2020/116263 CN2020116263W WO2021135408A1 WO 2021135408 A1 WO2021135408 A1 WO 2021135408A1 CN 2020116263 W CN2020116263 W CN 2020116263W WO 2021135408 A1 WO2021135408 A1 WO 2021135408A1
Authority
WO
WIPO (PCT)
Prior art keywords
pair
coupled transmission
transmission lines
transmission line
port
Prior art date
Application number
PCT/CN2020/116263
Other languages
French (fr)
Chinese (zh)
Inventor
蒋一帆
夏冬
盖川
Original Assignee
南京米乐为微电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南京米乐为微电子科技有限公司 filed Critical 南京米乐为微电子科技有限公司
Publication of WO2021135408A1 publication Critical patent/WO2021135408A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Definitions

  • the invention relates to a power amplifier, in particular to an ultra-wideband power amplifier.
  • microwave and millimeter wave resources have received more and more attention from military, civilian, commercial and related personnel in special fields.
  • the power amplifier is the key period in the microwave and millimeter wave system. It mainly plays a role in increasing the output power of the system. High output power can ensure that the system link has stronger anti-interference ability, better signal quality and farther.
  • the working radius of the system, and the monolithic integrated millimeter-wave power amplifier based on semiconductor technology has outstanding characteristics such as high stability, miniaturization, low cost, and low power consumption. It plays a huge role in the fields of communications, radar and special sensing applications.
  • the present invention provides an ultra-wideband microwave and millimeter wave differential power amplifier.
  • the present invention provides an ultra-wideband microwave and millimeter wave differential power amplifier, which includes an input terminal, an output terminal, an input matching network connected to the input terminal, an output matching network connected to the output terminal, And N power amplifier circuits connected in parallel between the input matching network and the output matching network, where N is the number of power amplifier circuits in the power amplifier, N ⁇ 1;
  • Each power amplifier circuit includes Q differential power transistors, Q is the number of stages of the power amplifier circuit, Q ⁇ 1; two adjacent differential power transistors on the same road are connected by an inter-stage matching network;
  • Each of the differential power transistors includes at least a pair of power transistors in a differential working mode and a gain enhancement network.
  • the input matching network, the inter-stage matching network and the output matching network are respectively an impedance matching network that provides the input, inter-stage and output impedance required by the differential power transistor in the ultra-wideband microwave millimeter wave frequency range.
  • the power transistor is a field effect tube or a bipolar transistor.
  • the gain enhancement network includes a cross-connected capacitive feedback network inserted at the differential input and output ends of a pair of differential transistors.
  • the gain enhancement network includes a feedback transmission line and a DC blocking capacitor respectively connected to the input and output ends of the same transistor in a pair of differential transistors.
  • the output matching network only includes a pair of coupling transmission lines arranged in mirror symmetry:
  • the isolated ends of the two coupled transmission lines in the pair are connected through the second output matching capacitor C_k2; the isolated end of the left coupled transmission line in the pair is connected to the port OUTk+, and the isolated end of the right coupled transmission line in the pair is connected to the port OUTk- ;
  • the through ends of the two coupled transmission lines in the pair are connected to the port Ak through the first output microstrip transmission line TL_Ak;
  • the input ends of the two coupled transmission lines in the pair are connected through the first output matching capacitor C_k1; the input end of the left coupled transmission line in the pair is connected to the port INk+, and the input end of the right coupled transmission line in the pair is connected to the port INk- ;
  • the output matching network includes 2 pairs of coupled transmission lines arranged in mirror symmetry:
  • the input ends of the two coupled transmission lines in the pair on the left are connected through the third matching capacitor C_K3; the input ends of the two coupled transmission lines in the pair on the right are connected through the fourth matching capacitor C_K4;
  • the input end of the left coupling transmission line is connected to the port INK1+, the input end of the right coupling transmission line of the left pair of coupling transmission lines is connected to the port INK1-, and the input end of the left coupling transmission line of the right pair of coupling transmission lines is connected to the port INK2+,
  • the input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the port INK2-;
  • the coupling ends of the two coupled transmission lines in the pair on the left are connected; the coupling ends of the two coupled transmission lines in the pair on the right are connected;
  • the through ends of the two coupled transmission lines in the left pair are connected through the second output microstrip transmission line TL_AK to connect to port AK; the through ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_BK Port BK;
  • the isolated end of the left coupled transmission line in the left pair of coupled transmission lines and the isolated end of the right coupled transmission line in the right pair of coupled transmission lines are connected by the third output matching capacitor C_K5; the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with The port OUTK+ is connected, and the isolated end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the port OUTK-;
  • the isolated end of the right coupled transmission line in the pair of coupled transmission lines on the left is connected to the isolated end of the left coupled transmission line in the pair of coupled transmission lines on the right.
  • each of the differential power transistors includes at least a pair of power transistors in a differential operation mode: a first power transistor M1 and a second power transistor M2;
  • the gain enhancement network includes a first neutralization capacitor C1 and a second neutralization capacitor C2;
  • the emitter of the first power transistor M1 is grounded, the collector is connected to the port JOUT+, and the base is connected to the port JIN+;
  • the emitter of the second power transistor M2 is grounded, the collector is connected to the port JOUT-, and the base is connected to the port JIN- connection;
  • the collector of the second power transistor M2 is connected to the base of the first power transistor M1 through the first neutralization capacitor C1; the collector of the first power transistor M1 is connected to the base of the second power transistor M2 through the second neutralization capacitor C2 connection.
  • each of the differential power transistors includes at least a pair of power transistors in a differential operation mode: a third power transistor M3 and a fourth power transistor M4;
  • the gain enhancement network includes a third DC blocking capacitor C3, a fourth DC blocking capacitor C4, a third feedback transmission line TL3, and a fourth feedback transmission line TL4;
  • the emitter of the third power transistor M3 is grounded, the collector is connected to the port JOUT+, and the base is connected to the port JIN+;
  • the emitter of the fourth power transistor M4 is grounded, the collector is connected to the port JOUT-, and the base is connected to the port JIN- connection;
  • the collector of the third power transistor M3 is connected to the base of the third power transistor M3 through the series-connected third feedback transmission line TL3 and the third DC blocking capacitor C3; the collector of the fourth power transistor M4 is connected through the series-connected fourth feedback transmission line TL4 , The fourth DC blocking capacitor C4 is connected to the base of the fourth power transistor M4.
  • the input matching network, the inter-stage matching network, and the output matching network each include several pairs of coupled transmission lines arranged in mirror symmetry, and a microstrip transmission line and matching capacitors adapted to it;
  • the electrical parameters of the coupled transmission lines in the same matching network are equal and their electrical length is less than 90 degrees;
  • the matching capacitance is the parasitic capacitance of the transistor or MIM capacitance or MOM capacitance
  • the microstrip transmission line is a DC bias network.
  • the input matching network includes N pairs of coupled transmission lines arranged in mirror symmetry, N ⁇ 1; the two coupled transmission lines in each pair are a left coupled transmission line and a right coupled transmission line;
  • the input matching network only includes a pair of coupled transmission lines arranged in mirror symmetry:
  • the isolated ends of the two coupled transmission lines in the pair are connected by a second matching capacitor; the isolated end of the left coupled transmission line in the pair is connected to the port OUTi+, and the isolated end of the right coupled transmission line in the pair is connected to the port OUTi-;
  • the input ends of the two coupled transmission lines in the pair are connected by a first matching capacitor; the input end of the left coupled transmission line in the pair is connected to the port INi+, and the input end of the right coupled transmission line in the pair is connected to the port INi-;
  • the input matching network includes 2 pairs of coupled transmission lines arranged in mirror symmetry:
  • the isolated ends of the two coupled transmission lines in the left pair are connected by the fourth matching capacitor C_I4; the isolated ends of the two coupled transmission lines in the right pair are connected by the fifth matching capacitor C_I5; the middle of the left pair of coupled transmission lines
  • the isolated end of the left-coupled transmission line is connected to the port OUTI1+, the isolated end of the right-coupled transmission line of the left pair of coupled transmission lines is connected to the port OUTI1-; the isolated end of the left-coupled transmission line of the right pair of coupled transmission lines is connected to the port OUTI2+ connection, the isolated end of the right coupling transmission line of the pair of coupling transmission lines on the right is connected to the port OUTI2-;
  • the through ends of the two coupled transmission lines in the pair on the left are connected; the through ends of the two coupled transmission lines in the pair on the right are connected;
  • the coupling ends of the two coupled transmission lines in the left pair are connected through the second microstrip transmission line TL_AI1 to connect to port AI1; the coupling ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_AI2 to connect to the port AI2;
  • the input end of the left coupled transmission line in the left pair of coupled transmission lines and the input end of the right coupled transmission line in the right pair of coupled transmission lines are connected by a third matching capacitor C_I3; the input end and port of the left coupled transmission line in the left pair of coupled transmission lines INI+ connection, the input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the port INI-;
  • the input end of the right coupling transmission line in the pair of coupling transmission lines on the left is connected to the input end of the left coupling transmission line in the pair of coupling transmission lines on the right.
  • the inter-stage matching network includes L pairs of coupled transmission lines arranged in mirror symmetry, L ⁇ 1; the two coupled transmission lines in each pair are left coupled transmission lines and right coupled transmission lines;
  • the inter-stage matching network only includes 1 pair of coupled transmission lines arranged in mirror symmetry:
  • the isolated ends of the two coupled transmission lines in the pair are connected through the second inter-stage matching capacitor C_j2; the isolated end of the left coupled transmission line in the pair is connected to port OUTj+, and the isolated end of the right coupled transmission line in each pair is connected to port OUTj -connection;
  • the through ends of the two coupled transmission lines in the pair are connected to the port Bj through the second inter-level microstrip transmission line TL_Bj;
  • the coupling ends of the two coupled transmission lines in the pair are connected to the port Aj through the first inter-level microstrip transmission line TL_Aj;
  • the input ends of the two coupled transmission lines in the pair are connected through the first interstage matching capacitor C_j1; the input end of the left coupled transmission line in the pair is connected to the port INj+, and the input end of the right coupled transmission line in the pair is connected to the port INj- connection;
  • the inter-stage matching network includes 2 pairs of coupled transmission lines arranged in mirror symmetry:
  • the isolation ends of the two coupled transmission lines in the left pair are connected through the fifth inter-stage matching capacitor C_J5;
  • the isolation ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage matching capacitor C_J6;
  • the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected to port OUTJ1+, the isolated end of the right coupled transmission line of the left pair of coupled transmission lines is connected to port OUTJ1-; the left coupled transmission line of the right pair of coupled transmission lines The isolated end of the right is connected to the port OUTJ2+, and the isolated end of the right coupled transmission line of the pair of coupled transmission lines on the right is connected to the port OUTJ2-;
  • the through ends of the two coupled transmission lines in the pair on the left are connected through the fifth inter-stage microstrip transmission line TL_BJ1 to connect to port BJ1; the through ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage microstrip Transmission line TL_BJ2 connects to port BJ2;
  • the coupling ends of the two coupled transmission lines in the pair on the left are connected through the third inter-level microstrip transmission line TL_AJ1 to connect to port AJ1; the coupling ends of the two coupled transmission lines in the right pair are connected through the fourth inter-level microstrip Transmission line TL_AJ2 connects to port AJ2;
  • the input ends of the two coupled transmission lines in the left pair are connected through the third inter-stage matching capacitor C_J3;
  • the input ends of the two coupled transmission lines in the right pair are connected through the fourth inter-stage matching capacitor C_J4;
  • the input end of the left coupled transmission line in the left pair of coupled transmission lines is connected to port INJ1+, the input end of the right coupled transmission line in the left pair of coupled transmission lines is connected to port INJ1-; the left coupled transmission line in the right pair of coupled transmission lines The input end of the right is connected to the port INJ2+, and the input end of the right coupling transmission line of the pair of coupling transmission lines on the right is connected to the port INJ2-.
  • the ultra-wideband microwave and millimeter wave differential power amplifier provided by the present invention has the following advantages:
  • the differential working mode provides greater output power compared to the single-ended mode
  • the differential working mode takes advantage of the features of the opposite phases of the two channels, which enables the internal feedback capacitance of the transistor to be compensated through the external passive network, thereby increasing the power gain of the transistor;
  • the differential working mode provides a virtual location on the center symmetrical line of the circuit, which simplifies the complexity of the feed network and improves the anti-interference performance of the amplifier against external spurious signals.
  • the input and output matching network can provide a good electrostatic protection function for the input and output terminals, and enhance the anti-interference performance of the device.
  • a low-loss and miniaturized output impedance matching network is realized by using a microstrip coupled transmission line, and its input impedance tracks the best impedance value obtained by the differential power transistor load in the ultra-wide frequency band, thereby in the ultra-wide frequency band Realizing the impedance matching of the large signal greatly improves the large signal working bandwidth of the amplifier and has the advantage of extremely high efficiency.
  • Figure 1 is a schematic block diagram of the circuit structure of an ultra-wideband microwave and millimeter wave differential power amplifier provided by the present invention
  • FIG. 2 is a schematic block diagram of the structure of a single-channel two-stage differential power amplifier provided by one of the embodiments;
  • FIG. 3 is a schematic block diagram of the structure of a two-way two-stage differential power amplifier provided by one of the embodiments;
  • FIG. 4 is a schematic diagram of the circuit structure of a differential power transistor in one of the embodiments.
  • FIG. 5 is a schematic diagram of the circuit structure of a differential power transistor in another embodiment
  • FIG. 6 is a schematic diagram of the circuit structure of the input matching network in the single-channel differential power amplifier provided by one of the embodiments;
  • FIG. 7 is a schematic diagram of the circuit structure of the inter-stage matching network in the single-channel differential power amplifier provided by one of the embodiments;
  • FIG. 8 is a schematic diagram of the circuit structure of the output matching network in the single-channel differential power amplifier provided by one of the embodiments;
  • FIG. 9 is a schematic diagram of the circuit structure of the input matching network in the two-channel differential power amplifier provided by one of the embodiments;
  • FIG. 10 is a schematic diagram of the circuit structure of the inter-stage matching network in the two-channel differential power amplifier provided by one of the embodiments;
  • FIG. 11 is a schematic diagram of the circuit structure of the output matching network in the two-channel differential power amplifier provided by one of the embodiments.
  • the present invention provides an ultra-wideband microwave millimeter wave differential power amplifier, as shown in FIG. 1, which includes an input end, an output end, an input matching network connected to the input end, an output matching network connected to the output end, and a parallel connection N-way power amplifier circuit between the input matching network and the output matching network.
  • N is the number of power amplifier circuits in the power amplifier, N ⁇ 1.
  • Each power amplifier circuit includes Q differential power transistors, Q is the number of stages of the power amplifier circuit, and Q ⁇ 1; two adjacent differential power transistors on the same road are connected through an inter-stage matching network.
  • Each of the differential power transistors includes at least a pair of power transistors in a differential working mode and a gain enhancement network.
  • the power amplifier circuit includes a differential power transistor 1, a differential power transistor 2, and an inter-stage matching network.
  • the structural connection relationship of this embodiment is as follows: the input end of the input matching network is connected to the power signal source through the input end of the differential power amplifier, the output end of the input matching network is connected to the input end of the first-stage differential power transistor 1, and the first-stage differential
  • the output terminal of the power transistor 1 is connected to the input terminal of the first-stage inter-stage matching network
  • the output terminal of the first-stage inter-stage matching network is connected to the input terminal of the second-stage differential power transistor 2
  • the output terminal of the second-stage differential power transistor 2 Connect the input end of the output matching network, and finally the output end of the output matching network is connected to the load through the output end of the differential power amplifier.
  • the form of the input matching network and the inter-stage matching network can be a commonly used transmission line connection structure or a package structure, or the publication number is CN110277965A, the application date is March 15, 2018, and the publication date is September 24, 2019.
  • the circuit structure of each power amplifier circuit is the same as the circuit structure of the power amplifier circuit in the previous embodiment, and will not be repeated here.
  • the form of the input matching network and the inter-stage matching network can be a commonly used transmission line connection structure or a package structure, or the publication number is CN110277965A, the application date is March 15, 2018, and the publication date is September 24, 2019.
  • the above-mentioned input matching network, inter-stage matching network and output matching network are respectively impedance matching networks that provide the input, inter-stage and output impedances required by the differential power transistor in the ultra-wideband microwave millimeter wave frequency range.
  • each input matching network, inter-stage matching network and output matching network by controlling the odd-mode and even-mode characteristic impedance of the coupled transmission line in the network, and making the electrical length less than a quarter wavelength, a broadband impedance transformation is realized.
  • the power transistor adopts a field effect tube or a bipolar transistor.
  • the above-mentioned gain enhancement network includes a cross-connected capacitive feedback network inserted at the differential input and output ends of a pair of differential transistors.
  • each of the above-mentioned differential power transistors includes at least a pair of power transistors in a differential operation mode: a first power transistor M1 and a second power transistor M2; the gain enhancement network includes a first power transistor.
  • the emitter of the first power transistor M1 is grounded, the collector is connected to the output port JOUT+, and the base is connected to the input port JIN+; the emitter of the second power transistor M2 is grounded, and the collector is connected to the input port JIN+.
  • the electrode is connected to the output port JOUT-, and the base is connected to the input port JIN-; the collector of the second power transistor M2 is connected to the base of the first power transistor M1 through the first neutralization capacitor C1; the collector of the first power transistor M1 The electrode is connected to the base of the second power transistor M2 through the second neutralization capacitor C2. That is: one end of the first neutralization capacitor C1 is connected to the base of the first power transistor M1, and the other end is connected to the collector of the second power transistor M2; one end of the second neutralization capacitor C2 is connected to the second power transistor M2 The base is connected, and the other end is connected to the collector of the first power transistor M1.
  • the working principle of the gain enhancement network is to use a pair of inverted signals provided by the differential working mode to make the first and second neutralizing capacitors equivalent to inductances through cross interconnection.
  • the equivalent inductance resonates with the base-collector capacitance inside the power transistor, thereby eliminating the negative feedback loop of the transistor, thereby enhancing the power gain of the differential power transistor.
  • the above-mentioned gain enhancement network includes a feedback transmission line and a DC blocking capacitor respectively connected to the input and output terminals of the same transistor in a pair of differential transistors.
  • each of the above-mentioned differential power transistors includes at least a pair of power transistors in a differential operation mode: a third power transistor M3 and a fourth power transistor M4; the gain enhancement network includes a third power transistor.
  • the emitter of the third power transistor M3 is grounded, the collector is connected to the output port JOUT+, and the base is connected to the input port JIN+; the emitter of the fourth power transistor M4 is grounded, the collector is connected to the output port JOUT-, and the base is connected to The input port JIN- is connected; the collector of the third power transistor M3 is connected to the base of the third power transistor M3 through the series-connected third feedback transmission line TL3 and the third DC blocking capacitor C3; the collector of the fourth power transistor M4 is connected in series through the The fourth feedback transmission line TL4 and the fourth DC blocking capacitor C4 are connected to the base of the fourth power transistor M4.
  • one end of the third DC blocking capacitor C3 is connected to the base of the third power transistor M3, the other end is connected to one end of the third feedback transmission line TL3, and the other end of the third feedback transmission line TL3 is connected to the set of the third power transistor M3.
  • Electrode connection; one end of the fourth DC blocking capacitor C4 is connected to the base of the fourth power transistor M4, the other end is connected to one end of the fourth feedback transmission line TL4, and the other end of the fourth feedback transmission line TL4 is connected to the collection of the fourth power transistor M4 Electrode connection.
  • This structure has greater design freedom than the structure shown in the previous embodiment (FIG. 4), and can further increase the gain of the transistor within the target operating frequency range.
  • the network can not only achieve the performance of the structure shown in the previous embodiment ( Figure 4), but also the gain enhancement network can provide a proper positive feedback loop for the differential power transistor, thereby further improving the stability of the differential power transistor. Gain.
  • the above-mentioned input matching network, inter-stage matching network and output matching network all include several pairs of coupled transmission lines arranged in mirror symmetry, as well as microstrip transmission lines and matching capacitors adapted to them.
  • the above-mentioned output matching network includes M pairs of coupled transmission lines arranged in mirror symmetry, M ⁇ 1; the two coupled transmission lines in each pair are left coupled transmission lines and right coupled transmission lines.
  • the aforementioned input matching network includes N pairs of coupled transmission lines arranged in mirror symmetry, N ⁇ 1; the two coupled transmission lines in each pair are left coupled transmission lines and right coupled transmission lines.
  • the above-mentioned inter-stage matching network includes L pairs of coupled transmission lines arranged in mirror symmetry, L ⁇ 1; the two coupled transmission lines in each pair are left coupled transmission lines and right coupled transmission lines.
  • FIG. 2 the structure diagram of the single-channel two-stage ultra-wideband microwave millimeter wave differential power amplifier provided in this embodiment is shown in FIG. 2. Specifically in this embodiment:
  • the output matching network only includes a pair of coupled transmission lines arranged in mirror symmetry as shown in FIG. 8. Specifically: the isolated ends of the two coupled transmission lines in the pair are connected through the second output matching capacitor C_k2; The isolated end of the left-coupled transmission line in the pair is connected to the output port OUTk+, and the isolated end of the right-coupled transmission line in the pair is connected to the output port OUTk-; the through ends of the two coupled transmission lines in the pair are connected through the first output
  • the microstrip transmission line TL_Ak is connected to the port Ak; the coupling ends of the two coupled transmission lines in the pair are connected; the input ends of the two coupled transmission lines in the pair are connected through the first output matching capacitor C_k1; the input of the left coupling transmission line in the pair The terminal is connected to the input port INk+, and the input terminal of the right-coupled transmission line in the pair is connected to the input port INk-.
  • the input matching network only includes a pair of coupled transmission lines arranged in mirror symmetry as shown in FIG. 6. Specifically: the isolated ends of the two coupled transmission lines in the pair are connected by a second matching capacitor; The isolated end of the left-coupled transmission line in the pair is connected to the output port OUTi+, and the isolated end of the right-coupled transmission line in the pair is connected to the output port OUTi-; the through ends of the two coupled transmission lines in the pair are connected; two of the pair The coupling end of the coupled transmission line is connected, and then the port Ai is connected through the first microstrip transmission line TL_Ai; the input ends of the two coupled transmission lines in the pair are connected through the first matching capacitor; the input end of the left coupling transmission line in the pair is connected to the input port INi+ is connected, and the input end of the right-coupled transmission line in the pair is connected to the input port INi-.
  • the inter-stage matching network as shown in Fig. 7 only includes a pair of coupled transmission lines arranged in mirror symmetry. Specifically: the isolation ends of the two coupled transmission lines in the pair pass through the second inter-stage matching capacitor C_j2 Connection; the isolated end of the left-coupled transmission line in the pair is connected to port OUTj+, the isolated end of the right-coupled transmission line in each pair is connected to port OUTj-; the through ends of the two coupled transmission lines in the pair are connected through the second The inter-stage microstrip transmission line TL_Bj is connected to the output port Bj; the coupling ends of the two coupled transmission lines in the pair are connected to the output port Aj through the first inter-stage microstrip transmission line TL_Aj; the input ends of the two coupled transmission lines in the pair pass The first interstage matching capacitor C_j1 is connected; the input end of the left-coupled transmission line in the pair is connected to the input port INj+, and the input end of the right-coupled transmission line in the pair
  • FIG. 3 the schematic diagram of the structure of the two-channel two-stage ultra-wideband microwave millimeter wave differential power amplifier provided in this embodiment is shown in FIG. 3. Specifically in this embodiment:
  • the output matching network is shown in Fig. 11, including two pairs of coupled transmission lines arranged in mirror symmetry, specifically:
  • the input ends of the two coupled transmission lines in the pair on the left are connected through the third matching capacitor C_K3; the input ends of the two coupled transmission lines in the pair on the right are connected through the fourth matching capacitor C_K4;
  • the input end of the left coupling transmission line is connected to the input port INK1+, the input end of the right coupling transmission line of the left pair of coupling transmission lines is connected to the input port INK1-, and the input end of the left coupling transmission line of the right pair of coupling transmission lines is connected to the input port INK2+ connection, the input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the input port INK2-;
  • the coupling ends of the two coupled transmission lines in the pair on the left are connected; the coupling ends of the two coupled transmission lines in the pair on the right are connected;
  • the through ends of the two coupled transmission lines in the left pair are connected through the second output microstrip transmission line TL_AK to connect to port AK; the through ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_BK Port BK;
  • the isolated end of the left coupled transmission line in the left pair of coupled transmission lines and the isolated end of the right coupled transmission line in the right pair of coupled transmission lines are connected by the third output matching capacitor C_K5; the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with The output port OUTK+ is connected, and the isolated end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the output port OUTK-;
  • the isolated end of the right coupled transmission line in the pair of coupled transmission lines on the left is connected to the isolated end of the left coupled transmission line in the pair of coupled transmission lines on the right.
  • the input matching network is shown in Fig. 9 and includes two pairs of coupled transmission lines arranged in mirror symmetry. Specifically:
  • the isolated ends of the two coupled transmission lines in the left pair are connected by the fourth matching capacitor C_I4; the isolated ends of the two coupled transmission lines in the right pair are connected by the fifth matching capacitor C_I5; the middle of the left pair of coupled transmission lines
  • the isolated end of the left-coupled transmission line is connected to the output port OUTI1+, the isolated end of the right-coupled transmission line in the left pair of coupled transmission lines is connected to the output port OUTI1-; the isolated end of the left-coupled transmission line in the right pair of coupled transmission lines It is connected to the output port OUTI2+, and the isolation end of the right coupling transmission line in the pair of right coupling transmission lines is connected to the output port OUTI2-.
  • the isolation end of the left coupling transmission line and the isolation end of the right coupling transmission line in the pair of coupled transmission lines on the left are connected by a fourth matching capacitor C_I4; the isolation end of the left coupling transmission line and the isolation end of the right coupling transmission line in the pair of coupling transmission lines on the right
  • the terminal is connected through the fifth matching capacitor C_I5.
  • the through ends of the two coupled transmission lines in the left pair are connected; the through ends of the two coupled transmission lines in the right pair are connected; that is, the through ends and the right ends of the left coupled transmission line in the left pair of coupled transmission lines are connected.
  • the through end of the coupled transmission line is connected; the through end of the left coupled transmission line in the pair of coupled transmission lines on the right is connected with the through end of the right coupled transmission line.
  • the coupling ends of the two coupled transmission lines in the left pair are connected through the second microstrip transmission line TL_AI1 to connect to port AI1; the coupling ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_AI2 to connect to the port AI2; that is: the coupling end of the left coupling transmission line and the coupling end of the right coupling transmission line in the pair of coupling transmission lines on the left are connected through the second microstrip transmission line TL_AI1 to connect to port AI1; the coupling of the left coupling transmission line in the pair of coupling transmission lines on the right After connecting with the coupling end of the right coupling transmission line, connect the port AI2 through the third microstrip transmission line TL_AI2;
  • the input end of the left coupled transmission line in the left pair of coupled transmission lines and the input end of the right coupled transmission line in the right pair of coupled transmission lines are connected by a third matching capacitor C_I3; the input end of the left coupled transmission line in the left pair of coupled transmission lines is connected to the input Port INI+ connection, the input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the input port INI-;
  • the input end of the right coupling transmission line in the pair of coupling transmission lines on the left is connected to the input end of the left coupling transmission line in the pair of coupling transmission lines on the right.
  • the inter-stage matching network is shown in Fig. 10, including two pairs of coupled transmission lines arranged in mirror symmetry, specifically:
  • the isolation ends of the two coupled transmission lines in the left pair are connected through the fifth inter-stage matching capacitor C_J5;
  • the isolation ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage matching capacitor C_J6;
  • the isolation end of the left coupling transmission line in the pair of coupling transmission lines on the left is connected to the output port OUTJ1+,
  • the isolation end of the right coupling transmission line in the pair of coupling transmission lines on the left is connected to the output port OUTJ1-;
  • the isolation end of the left coupling transmission line in the pair of coupling transmission lines on the right is connected to the output port OUTJ2+,
  • the isolation end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the output port OUTJ2-;
  • the through ends of the two coupled transmission lines in the pair on the left are connected through the fifth inter-stage microstrip transmission line TL_BJ1 to connect to port BJ1; the through ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage microstrip Transmission line TL_BJ2 connects to port BJ2;
  • the coupling ends of the two coupled transmission lines in the pair on the left are connected through the third inter-level microstrip transmission line TL_AJ1 to connect to port AJ1; the coupling ends of the two coupled transmission lines in the right pair are connected through the fourth inter-level microstrip Transmission line TL_AJ2 connects to port AJ2;
  • the input ends of the two coupled transmission lines in the left pair are connected through the third inter-stage matching capacitor C_J3;
  • the input ends of the two coupled transmission lines in the right pair are connected through the fourth inter-stage matching capacitor C_J4;
  • the input end of the left coupling transmission line of the left pair of coupled transmission lines is connected to the input port INJ1+, and the input end of the right coupling transmission line of the left pair of coupled transmission lines is connected to the input port INJ1-; the left of the right pair of coupled transmission lines The input end of the coupling transmission line is connected to the input port INJ2+, and the input end of the right coupling transmission line of the pair of coupling transmission lines on the right is connected to the input port INJ2-.
  • the electrical parameters of the coupled transmission lines in the same matching network are equal and their electrical lengths are less than 90 degrees.
  • the matching capacitance is the parasitic capacitance of the transistor or MIM capacitance or MOM capacitance.
  • the microstrip transmission line is a DC bias network. That is: the electrical parameters of the coupled transmission lines in the same input matching network are equal and their electrical lengths are less than 90 degrees; the electrical parameters of the coupled transmission lines in the same inter-stage matching network are equal and their electrical lengths are less than 90 degrees; they are located in the same output matching network. The electrical parameters of each coupled transmission line in the network are equal and the electrical length is less than 90 degrees.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microwave Amplifiers (AREA)

Abstract

Disclosed is an ultra-wideband microwave and millimeter wave differential power amplifier, comprising an input end, an output end, an input matching network connected to the input end, an output matching network connected to the output end, and an N-way power amplifier circuits connected in parallel between the input matching network and the output matching network, wherein N is the number of ways of the power amplifier circuit in the power amplifier; N≥1; each way of power amplifier circuit comprises Q differential power transistors; Q is the number of stages of the power amplifier circuit; Q≥1; two adjacent differential power transistors located on the same way are connected to each other by means of an inter-stage matching network; the differential power transistors comprise at least a pair of power transistors and gain enhancement networks in a differential working mode. This implementation enhances the anti-interference performance of the amplifier, achieves impedance matching of a large signal in an ultra-wide frequency band, greatly improves the working bandwidth of the large signal of the amplifier, and has high efficiency.

Description

超宽带微波毫米波差分功率放大器Ultra-wideband microwave and millimeter wave differential power amplifier 技术领域Technical field
本发明涉及一种功率放大器，具体涉及一种超宽带功率放大器。The invention relates to a power amplifier, in particular to an ultra-wideband power amplifier.
背景技术Background technique
近些年，随着射频频谱和微波低频频谱资源的逐渐耗尽，微波和毫米波资源越来越受到军，民，商以及特种领域相关工作人员的重视。In recent years, with the gradual exhaustion of radio frequency spectrum and microwave low frequency spectrum resources, microwave and millimeter wave resources have received more and more attention from military, civilian, commercial and related personnel in special fields.
功率放大器是微波毫米波***中的关键期间，其主要起到发大和提高***输出功率的作用，高输出功率可以保证***链路具有更强的抗干扰能力，更好的信号质量以及更远的***工作半径，而基于半导体工艺的单片集成毫米波功率放大器具有高稳定，小型化，低成本，低功耗等显著特点，在通信，雷达以及特种传感应用等领域发挥着巨大的作用。The power amplifier is the key period in the microwave and millimeter wave system. It mainly plays a role in increasing the output power of the system. High output power can ensure that the system link has stronger anti-interference ability, better signal quality and farther The working radius of the system, and the monolithic integrated millimeter-wave power amplifier based on semiconductor technology has outstanding characteristics such as high stability, miniaturization, low cost, and low power consumption. It plays a huge role in the fields of communications, radar and special sensing applications.
随着应用需求的不断发展，现代微波和毫米波***对功率放大器提出了更高的要求，包括：With the continuous development of application requirements, modern microwave and millimeter wave systems have put forward higher requirements for power amplifiers, including:
1.大输出功率，用以提高***工作半径和链路的抗干扰性能。1. Large output power to improve the working radius of the system and the anti-interference performance of the link.
2.宽工作频带，用以满足高数据率传输所要求的射频带宽。2. Wide working frequency band to meet the radio frequency bandwidth required for high data rate transmission.
3.高功率附加效率，用以满足***的低功耗要求。3. High power additional efficiency to meet the low power consumption requirements of the system.
发明内容Summary of the invention
发明目的：为了解决现有技术中的不足，本发明提供了一种超宽带微波毫米波差分功率放大器。Purpose of the invention: In order to solve the deficiencies in the prior art, the present invention provides an ultra-wideband microwave and millimeter wave differential power amplifier.
技术方案：为解决上述技术问题，本发明提供的一种超宽带微波毫米波差分功率放大器，其包括输入端、输出端、与输入端连接的输入匹配网络、与输出端连接的输出匹配网络、以及并联于输入匹配网络和输出匹配网络之间的N路功率放大电路，N为该功率放大器中功率放大电路的路数，N≥1；Technical solution: In order to solve the above technical problems, the present invention provides an ultra-wideband microwave and millimeter wave differential power amplifier, which includes an input terminal, an output terminal, an input matching network connected to the input terminal, an output matching network connected to the output terminal, And N power amplifier circuits connected in parallel between the input matching network and the output matching network, where N is the number of power amplifier circuits in the power amplifier, N≥1;
每一路功率放大电路中包括Q个差分功率晶体管，Q为该功率放大电路的级数，Q≥1；位于同一路上的两个相邻的差分功率晶体管通过级间匹配网络连接；Each power amplifier circuit includes Q differential power transistors, Q is the number of stages of the power amplifier circuit, Q≥1; two adjacent differential power transistors on the same road are connected by an inter-stage matching network;
所述各差分功率晶体管至少包括一对处于差分工作模式的功率晶体管和增益增强网络。Each of the differential power transistors includes at least a pair of power transistors in a differential working mode and a gain enhancement network.
优选的，所述输入匹配网络、级间匹配网络和输出匹配网络分别为在超宽带微波毫米波频率范围内提供所述差分功率晶体管所需要的输入、级间和输出阻抗的阻抗匹配网络。Preferably, the input matching network, the inter-stage matching network and the output matching network are respectively an impedance matching network that provides the input, inter-stage and output impedance required by the differential power transistor in the ultra-wideband microwave millimeter wave frequency range.
优选的，所述功率晶体管为场效应管或双极性晶体管。Preferably, the power transistor is a field effect tube or a bipolar transistor.
作为其中一种优选方案，所述增益增强网络包括在一对差分晶体管的差分输入输出端***的交叉互连的电容反馈网络。As one of the preferred solutions, the gain enhancement network includes a cross-connected capacitive feedback network inserted at the differential input and output ends of a pair of differential transistors.
作为其中另一种优选方案，所述增益增强网络包括分别连接在一对差分晶体管中的同一晶体管输入输出端的反馈传输线和隔直电容。As another preferred solution, the gain enhancement network includes a feedback transmission line and a DC blocking capacitor respectively connected to the input and output ends of the same transistor in a pair of differential transistors.
作为进一步的优选方案，所述输出匹配网络中包括M对镜像对称设置的耦合传输 线，M≥1；每一对中的两个耦合传输线为左耦合传输线和右耦合传输线；当M＝1时，所述输出匹配网络只包括1对镜像对称设置的耦合传输线：As a further preferred solution, the output matching network includes M pairs of coupled transmission lines arranged in mirror symmetry, M≥1; the two coupled transmission lines in each pair are the left coupled transmission line and the right coupled transmission line; when M=1, The output matching network only includes a pair of coupling transmission lines arranged in mirror symmetry:
该对中的两个耦合传输线的隔离端通过第二输出匹配电容C_k2连接；该对中的左耦合传输线的隔离端与端口OUTk+连接，该对中的右耦合传输线的隔离端与端口OUTk-连接；The isolated ends of the two coupled transmission lines in the pair are connected through the second output matching capacitor C_k2; the isolated end of the left coupled transmission line in the pair is connected to the port OUTk+, and the isolated end of the right coupled transmission line in the pair is connected to the port OUTk- ；
该对中的两个耦合传输线的直通端相连后通过第一输出微带传输线TL_Ak连接端口Ak；The through ends of the two coupled transmission lines in the pair are connected to the port Ak through the first output microstrip transmission line TL_Ak;
该对中的两个耦合传输线的耦合端相连；The coupling ends of the two coupled transmission lines in the pair are connected;
该对中的两个耦合传输线的输入端通过第一输出匹配电容C_k1连接；该对中的左耦合传输线的输入端与端口INk+连接，该对中的右耦合传输线的输入端与端口INk-连接；The input ends of the two coupled transmission lines in the pair are connected through the first output matching capacitor C_k1; the input end of the left coupled transmission line in the pair is connected to the port INk+, and the input end of the right coupled transmission line in the pair is connected to the port INk- ；
当M＝2时，所述输出匹配网络包括2对镜像对称设置的耦合传输线：When M=2, the output matching network includes 2 pairs of coupled transmission lines arranged in mirror symmetry:
左侧一对中的两个耦合传输线的输入端通过第三匹配电容C_K3连接；右侧一对中的两个耦合传输线的输入端通过第四匹配电容C_K4连接；左侧一对耦合传输线中的左耦合传输线的输入端与端口INK1+连接，左侧一对耦合传输线中的右耦合传输线的输入端与端口INK1-连接，右侧一对耦合传输线中的左耦合传输线的输入端与端口INK2+连接，右侧一对耦合传输线中的右耦合传输线的输入端与端口INK2-连接；The input ends of the two coupled transmission lines in the pair on the left are connected through the third matching capacitor C_K3; the input ends of the two coupled transmission lines in the pair on the right are connected through the fourth matching capacitor C_K4; The input end of the left coupling transmission line is connected to the port INK1+, the input end of the right coupling transmission line of the left pair of coupling transmission lines is connected to the port INK1-, and the input end of the left coupling transmission line of the right pair of coupling transmission lines is connected to the port INK2+, The input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the port INK2-;
左侧一对中的两个耦合传输线的耦合端相连；右侧一对中的两个耦合传输线的耦合端相连；The coupling ends of the two coupled transmission lines in the pair on the left are connected; the coupling ends of the two coupled transmission lines in the pair on the right are connected;
左侧一对中的两个耦合传输线的直通端相连后通过第二输出微带传输线TL_AK连接端口AK；右侧一对中的两个耦合传输线的直通端相连后通过第三微带传输线TL_BK连接端口BK；The through ends of the two coupled transmission lines in the left pair are connected through the second output microstrip transmission line TL_AK to connect to port AK; the through ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_BK Port BK;
左侧一对耦合传输线中左耦合传输线的隔离端和右侧一对耦合传输线中右耦合传输线的隔离端通过第三输出匹配电容C_K5连接；左侧一对耦合传输线中左耦合传输线的隔离端与端口OUTK+连接，右侧一对耦合传输线中右耦合传输线的隔离端与端口OUTK-连接；The isolated end of the left coupled transmission line in the left pair of coupled transmission lines and the isolated end of the right coupled transmission line in the right pair of coupled transmission lines are connected by the third output matching capacitor C_K5; the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with The port OUTK+ is connected, and the isolated end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the port OUTK-;
左侧一对耦合传输线中右耦合传输线的隔离端和右侧一对耦合传输线中左耦合传输线的隔离端相连。The isolated end of the right coupled transmission line in the pair of coupled transmission lines on the left is connected to the isolated end of the left coupled transmission line in the pair of coupled transmission lines on the right.
作为进一步的优选方案，所述各差分功率晶体管至少包括一对处于差分工作模式的功率晶体管：第一功率晶体管M1和第二功率晶体管M2；As a further preferred solution, each of the differential power transistors includes at least a pair of power transistors in a differential operation mode: a first power transistor M1 and a second power transistor M2;
所述增益增强网络包括第一中和电容C1和第二中和电容C2；The gain enhancement network includes a first neutralization capacitor C1 and a second neutralization capacitor C2;
其中第一功率晶体管M1的发射级接地，集电极与端口JOUT+连接，基极与端口JIN+连接；其中第二功率晶体管M2的发射级接地，集电极与端口JOUT-连接，基极与端口JIN-连接；The emitter of the first power transistor M1 is grounded, the collector is connected to the port JOUT+, and the base is connected to the port JIN+; the emitter of the second power transistor M2 is grounded, the collector is connected to the port JOUT-, and the base is connected to the port JIN- connection;
第二功率晶体管M2的集电极通过第一中和电容C1与第一功率晶体管M1的基极连接；第一功率晶体管M1的集电极通过第二中和电容C2与第二功率晶体管M2的基极连接。The collector of the second power transistor M2 is connected to the base of the first power transistor M1 through the first neutralization capacitor C1; the collector of the first power transistor M1 is connected to the base of the second power transistor M2 through the second neutralization capacitor C2 connection.
作为进一步的优选方案，所述各差分功率晶体管至少包括一对处于差分工作模式的功率晶体管：第三功率晶体管M3和第四功率晶体管M4；As a further preferred solution, each of the differential power transistors includes at least a pair of power transistors in a differential operation mode: a third power transistor M3 and a fourth power transistor M4;
所述增益增强网络包括第三隔直电容C3、第四隔直电容C4、第三反馈传输线TL3和第四反馈传输线TL4；The gain enhancement network includes a third DC blocking capacitor C3, a fourth DC blocking capacitor C4, a third feedback transmission line TL3, and a fourth feedback transmission line TL4;
其中第三功率晶体管M3的发射级接地，集电极与端口JOUT+连接，基极与端口JIN+连接；其中第四功率晶体管M4的发射级接地，集电极与端口JOUT-连接，基极与端口JIN-连接；The emitter of the third power transistor M3 is grounded, the collector is connected to the port JOUT+, and the base is connected to the port JIN+; the emitter of the fourth power transistor M4 is grounded, the collector is connected to the port JOUT-, and the base is connected to the port JIN- connection;
第三功率晶体管M3的集电极通过串联的第三反馈传输线TL3、第三隔直电容C3与第三功率晶体管M3的基极连接；第四功率晶体管M4的集电极通过串联的第四反馈传输线TL4、第四隔直电容C4与第四功率晶体管M4的基极连接。The collector of the third power transistor M3 is connected to the base of the third power transistor M3 through the series-connected third feedback transmission line TL3 and the third DC blocking capacitor C3; the collector of the fourth power transistor M4 is connected through the series-connected fourth feedback transmission line TL4 , The fourth DC blocking capacitor C4 is connected to the base of the fourth power transistor M4.
优选的，所述输入匹配网络、级间匹配网络和输出匹配网络均包括若干对镜像对称设置的耦合传输线，以及与之适配的微带传输线和匹配电容；Preferably, the input matching network, the inter-stage matching network, and the output matching network each include several pairs of coupled transmission lines arranged in mirror symmetry, and a microstrip transmission line and matching capacitors adapted to it;
位于同一匹配网络中各耦合传输线的电气参数相等且其电长度小于90度；The electrical parameters of the coupled transmission lines in the same matching network are equal and their electrical length is less than 90 degrees;
其中匹配电容为晶体管寄生电容或MIM电容或MOM电容；The matching capacitance is the parasitic capacitance of the transistor or MIM capacitance or MOM capacitance;
其中微带传输线为直流偏置网络。The microstrip transmission line is a DC bias network.
优选的，所述输入匹配网络中包括N对镜像对称设置的耦合传输线，N≥1；每一对中的两个耦合传输线为左耦合传输线和右耦合传输线；Preferably, the input matching network includes N pairs of coupled transmission lines arranged in mirror symmetry, N≥1; the two coupled transmission lines in each pair are a left coupled transmission line and a right coupled transmission line;
当N＝1时，所述输入匹配网络只包括1对镜像对称设置的耦合传输线：When N=1, the input matching network only includes a pair of coupled transmission lines arranged in mirror symmetry:
该对中的两个耦合传输线的隔离端通过第二匹配电容连接；该对中的左耦合传输线的隔离端与端口OUTi+连接，该对中的右耦合传输线的隔离端与端口OUTi-连接；The isolated ends of the two coupled transmission lines in the pair are connected by a second matching capacitor; the isolated end of the left coupled transmission line in the pair is connected to the port OUTi+, and the isolated end of the right coupled transmission line in the pair is connected to the port OUTi-;
该对中的两个耦合传输线的直通端相连；The through ends of the two coupled transmission lines in the pair are connected;
该对中的两个耦合传输线的耦合端相连，然后通过第一微带传输线TL_Ai连接端口Ai；The coupling ends of the two coupled transmission lines in the pair are connected, and then the first microstrip transmission line TL_Ai is connected to the port Ai;
该对中的两个耦合传输线的输入端通过第一匹配电容连接；该对中的左耦合传输线的输入端与端口INi+连接，该对中的右耦合传输线的输入端与端口INi-连接；The input ends of the two coupled transmission lines in the pair are connected by a first matching capacitor; the input end of the left coupled transmission line in the pair is connected to the port INi+, and the input end of the right coupled transmission line in the pair is connected to the port INi-;
当N＝2时，所述输入匹配网络包括2对镜像对称设置的耦合传输线：When N=2, the input matching network includes 2 pairs of coupled transmission lines arranged in mirror symmetry:
左侧一对中的两个耦合传输线的隔离端通过第四匹配电容C_I4连接；右侧一对中的两个耦合传输线的隔离端通过第五匹配电容C_I5连接；左侧一对耦合传输线的中的左耦合传输线的隔离端与端口OUTI1+连接，左侧一对耦合传输线的中的右耦合传输线的隔离端与端口OUTI1-连接；右侧一对耦合传输线的中的左耦合传输线的隔离端与端口OUTI2+连接，右侧一对耦合传输线的中的右耦合传输线的隔离端与端口OUTI2-连接；The isolated ends of the two coupled transmission lines in the left pair are connected by the fourth matching capacitor C_I4; the isolated ends of the two coupled transmission lines in the right pair are connected by the fifth matching capacitor C_I5; the middle of the left pair of coupled transmission lines The isolated end of the left-coupled transmission line is connected to the port OUTI1+, the isolated end of the right-coupled transmission line of the left pair of coupled transmission lines is connected to the port OUTI1-; the isolated end of the left-coupled transmission line of the right pair of coupled transmission lines is connected to the port OUTI2+ connection, the isolated end of the right coupling transmission line of the pair of coupling transmission lines on the right is connected to the port OUTI2-;
左侧一对中的两个耦合传输线的直通端相连；右侧一对中的两个耦合传输线的直通端相连；The through ends of the two coupled transmission lines in the pair on the left are connected; the through ends of the two coupled transmission lines in the pair on the right are connected;
左侧一对中的两个耦合传输线的耦合端相连后通过第二微带传输线TL_AI1连接端口AI1；右侧一对中的两个耦合传输线的耦合端相连后通过第三微带传输线TL_AI2连接端口AI2；The coupling ends of the two coupled transmission lines in the left pair are connected through the second microstrip transmission line TL_AI1 to connect to port AI1; the coupling ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_AI2 to connect to the port AI2;
左侧一对耦合传输线中左耦合传输线的输入端和右侧一对耦合传输线中右耦合传输线的输入端通过第三匹配电容C_I3连接；左侧一对耦合传输线中左耦合传输线的输入端与端口INI+连接，右侧一对耦合传输线中右耦合传输线的输入端与端口INI-连接；The input end of the left coupled transmission line in the left pair of coupled transmission lines and the input end of the right coupled transmission line in the right pair of coupled transmission lines are connected by a third matching capacitor C_I3; the input end and port of the left coupled transmission line in the left pair of coupled transmission lines INI+ connection, the input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the port INI-;
左侧一对耦合传输线中右耦合传输线的输入端和右侧一对耦合传输线中左耦合传输线的输入端相连。The input end of the right coupling transmission line in the pair of coupling transmission lines on the left is connected to the input end of the left coupling transmission line in the pair of coupling transmission lines on the right.
优选的，所述级间匹配网络中包括L对镜像对称设置的耦合传输线，L≥1；每一对中的两个耦合传输线为左耦合传输线和右耦合传输线；Preferably, the inter-stage matching network includes L pairs of coupled transmission lines arranged in mirror symmetry, L≥1; the two coupled transmission lines in each pair are left coupled transmission lines and right coupled transmission lines;
当L＝1时，所述级间匹配网络只包括1对镜像对称设置的耦合传输线：When L=1, the inter-stage matching network only includes 1 pair of coupled transmission lines arranged in mirror symmetry:
该对中的两个耦合传输线的隔离端通过第二级间匹配电容C_j2连接；该对中的左耦合传输线的隔离端与端口OUTj+连接，每一对中的右耦合传输线的隔离端与端口OUTj-连接；The isolated ends of the two coupled transmission lines in the pair are connected through the second inter-stage matching capacitor C_j2; the isolated end of the left coupled transmission line in the pair is connected to port OUTj+, and the isolated end of the right coupled transmission line in each pair is connected to port OUTj -connection;
该对中的两个耦合传输线的直通端相连后通过第二级间微带传输线TL_Bj连接端口Bj；The through ends of the two coupled transmission lines in the pair are connected to the port Bj through the second inter-level microstrip transmission line TL_Bj;
该对中的两个耦合传输线的耦合端相连后通过第一级间微带传输线TL_Aj连接端口Aj；The coupling ends of the two coupled transmission lines in the pair are connected to the port Aj through the first inter-level microstrip transmission line TL_Aj;
该对中的两个耦合传输线的输入端通过第一级间匹配电容C_j1连接；该对中的左耦合传输线的输入端与端口INj+连接，该对中的右耦合传输线的输入端与端口INj-连接；The input ends of the two coupled transmission lines in the pair are connected through the first interstage matching capacitor C_j1; the input end of the left coupled transmission line in the pair is connected to the port INj+, and the input end of the right coupled transmission line in the pair is connected to the port INj- connection;
当L＝2时，所述级间匹配网络包括2对镜像对称设置的耦合传输线：When L=2, the inter-stage matching network includes 2 pairs of coupled transmission lines arranged in mirror symmetry:
左侧一对中的两个耦合传输线的隔离端通过第五级间匹配电容C_J5连接；The isolation ends of the two coupled transmission lines in the left pair are connected through the fifth inter-stage matching capacitor C_J5;
右侧一对中的两个耦合传输线的隔离端通过第六级间匹配电容C_J6连接；The isolation ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage matching capacitor C_J6;
左侧一对耦合传输线中的左耦合传输线的隔离端与端口OUTJ1+连接，左侧一对耦合传输线中的右耦合传输线的隔离端与端口OUTJ1-连接；右侧一对耦合传输线中的左耦合传输线的隔离端与端口OUTJ2+连接，右侧一对耦合传输线中的右耦合传输线的隔离端与端口OUTJ2-连接；The isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected to port OUTJ1+, the isolated end of the right coupled transmission line of the left pair of coupled transmission lines is connected to port OUTJ1-; the left coupled transmission line of the right pair of coupled transmission lines The isolated end of the right is connected to the port OUTJ2+, and the isolated end of the right coupled transmission line of the pair of coupled transmission lines on the right is connected to the port OUTJ2-;
左侧一对中的两个耦合传输线的直通端相连后通过第五级间微带传输线TL_BJ1连接端口BJ1；右侧一对中的两个耦合传输线的直通端相连后通过第六级间微带传输线TL_BJ2连接端口BJ2；The through ends of the two coupled transmission lines in the pair on the left are connected through the fifth inter-stage microstrip transmission line TL_BJ1 to connect to port BJ1; the through ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage microstrip Transmission line TL_BJ2 connects to port BJ2;
左侧一对中的两个耦合传输线的耦合端相连后通过第三级间微带传输线TL_AJ1连接端口AJ1；右侧一对中的两个耦合传输线的耦合端相连后通过第四级间微带传输线TL_AJ2连接端口AJ2；The coupling ends of the two coupled transmission lines in the pair on the left are connected through the third inter-level microstrip transmission line TL_AJ1 to connect to port AJ1; the coupling ends of the two coupled transmission lines in the right pair are connected through the fourth inter-level microstrip Transmission line TL_AJ2 connects to port AJ2;
左侧一对中的两个耦合传输线的输入端通过第三级间匹配电容C_J3连接；The input ends of the two coupled transmission lines in the left pair are connected through the third inter-stage matching capacitor C_J3;
右侧一对中的两个耦合传输线的输入端通过第四级间匹配电容C_J4连接；The input ends of the two coupled transmission lines in the right pair are connected through the fourth inter-stage matching capacitor C_J4;
左侧一对耦合传输线中的左耦合传输线的输入端与端口INJ1+连接，左侧一对耦合传输线中的右耦合传输线的输入端与端口INJ1-连接；右侧一对耦合传输线中的左耦合传输线的输入端与端口INJ2+，右侧一对耦合传输线中的右耦合传输线的输入端与端口INJ2-连接。The input end of the left coupled transmission line in the left pair of coupled transmission lines is connected to port INJ1+, the input end of the right coupled transmission line in the left pair of coupled transmission lines is connected to port INJ1-; the left coupled transmission line in the right pair of coupled transmission lines The input end of the right is connected to the port INJ2+, and the input end of the right coupling transmission line of the pair of coupling transmission lines on the right is connected to the port INJ2-.
有益效果：本发明提供的超宽带微波毫米波差分功率放大器，与现有技术相比，其具有如下优点：Beneficial effects: Compared with the prior art, the ultra-wideband microwave and millimeter wave differential power amplifier provided by the present invention has the following advantages:
1、差分工作模式相对于单端模式提供了更大的输出功率；1. The differential working mode provides greater output power compared to the single-ended mode;
2、差分工作模式利用了两路相位相反的特征，可以使晶体管内部反馈电容通过外部无源网络得到补偿，进而提高晶体管功率增益；2. The differential working mode takes advantage of the features of the opposite phases of the two channels, which enables the internal feedback capacitance of the transistor to be compensated through the external passive network, thereby increasing the power gain of the transistor;
3、差分工作模式在电路的中心对称线上提供了虚地点，从而简化了馈电网络的复杂性，并且提高了本放大器对于外部杂散信号的抗干扰性。3. The differential working mode provides a virtual location on the center symmetrical line of the circuit, which simplifies the complexity of the feed network and improves the anti-interference performance of the amplifier against external spurious signals.
4、所述的输入输出匹配网络能对输入输出端提供良好的静电保护功能，增强器件的抗干扰性能。4. The input and output matching network can provide a good electrostatic protection function for the input and output terminals, and enhance the anti-interference performance of the device.
5、进一步的，利用微带耦合传输线实现了低损耗和小型化的输出阻抗匹配网络， 其输入阻抗在超宽频带内追踪差分功率晶体管负载牵引得到的最佳阻抗值，从而在超宽频带内实现大信号的阻抗匹配，极大的提升了放大器的大信号工作带宽并且具有极高效率的优势。5. Further, a low-loss and miniaturized output impedance matching network is realized by using a microstrip coupled transmission line, and its input impedance tracks the best impedance value obtained by the differential power transistor load in the ultra-wide frequency band, thereby in the ultra-wide frequency band Realizing the impedance matching of the large signal greatly improves the large signal working bandwidth of the amplifier and has the advantage of extremely high efficiency.
附图说明Description of the drawings
图1为本发明提供的超宽带微波毫米波差分功率放大器的电路结构示意框图；Figure 1 is a schematic block diagram of the circuit structure of an ultra-wideband microwave and millimeter wave differential power amplifier provided by the present invention;
图2为其中一个实施例提供的单路两级的差分功率放大器的结构示意框图；2 is a schematic block diagram of the structure of a single-channel two-stage differential power amplifier provided by one of the embodiments;
图3为其中一个实施例提供的两路两级的差分功率放大器的结构示意框图；FIG. 3 is a schematic block diagram of the structure of a two-way two-stage differential power amplifier provided by one of the embodiments;
图4为其中一个实施例中的差分功率晶体管的电路结构原理图；4 is a schematic diagram of the circuit structure of a differential power transistor in one of the embodiments;
图5为其中另一个实施例中的差分功率晶体管的电路结构原理图；FIG. 5 is a schematic diagram of the circuit structure of a differential power transistor in another embodiment;
图6为其中一个实施例提供的单路差分功率放大器中的输入匹配网络的电路结构原理图；6 is a schematic diagram of the circuit structure of the input matching network in the single-channel differential power amplifier provided by one of the embodiments;
图7为其中一个实施例提供的单路差分功率放大器中的级间匹配网络的电路结构原理图；7 is a schematic diagram of the circuit structure of the inter-stage matching network in the single-channel differential power amplifier provided by one of the embodiments;
图8为其中一个实施例提供的单路差分功率放大器中的输出匹配网络的电路结构原理图；8 is a schematic diagram of the circuit structure of the output matching network in the single-channel differential power amplifier provided by one of the embodiments;
图9为其中一个实施例提供的两路差分功率放大器中的输入匹配网络的电路结构原理图；9 is a schematic diagram of the circuit structure of the input matching network in the two-channel differential power amplifier provided by one of the embodiments;
图10为其中一个实施例提供的两路差分功率放大器中的级间匹配网络的电路结构原理图；10 is a schematic diagram of the circuit structure of the inter-stage matching network in the two-channel differential power amplifier provided by one of the embodiments;
图11为其中一个实施例提供的两路差分功率放大器中的输出匹配网络的电路结构原理图。FIG. 11 is a schematic diagram of the circuit structure of the output matching network in the two-channel differential power amplifier provided by one of the embodiments.
具体实施方式Detailed ways
下面结合实施例和附图对本发明做进一步的详细说明，以下实施列对本发明不构成限定。The present invention will be further described in detail below in conjunction with the embodiments and the drawings, and the following embodiments do not limit the present invention.
本发明提供的一种超宽带微波毫米波差分功率放大器，如图1所示，其包括输入端、输出端、与输入端连接的输入匹配网络、与输出端连接的输出匹配网络、以及并联于输入匹配网络和输出匹配网络之间的N路功率放大电路。其中N为该功率放大器中功率放大电路的路数，N≥1。The present invention provides an ultra-wideband microwave millimeter wave differential power amplifier, as shown in FIG. 1, which includes an input end, an output end, an input matching network connected to the input end, an output matching network connected to the output end, and a parallel connection N-way power amplifier circuit between the input matching network and the output matching network. Where N is the number of power amplifier circuits in the power amplifier, N≥1.
其中每一路功率放大电路中包括Q个差分功率晶体管，Q为该功率放大电路的级数，Q≥1；位于同一路上的两个相邻的差分功率晶体管通过级间匹配网络连接。Each power amplifier circuit includes Q differential power transistors, Q is the number of stages of the power amplifier circuit, and Q≥1; two adjacent differential power transistors on the same road are connected through an inter-stage matching network.
其中各差分功率晶体管均至少包括一对处于差分工作模式的功率晶体管和增益增强网络。Each of the differential power transistors includes at least a pair of power transistors in a differential working mode and a gain enhancement network.
其中一种实施例提供的N＝1、Q＝2时的单路两级的超宽带微波毫米波差分功率放大器的结构示意图如图2所示，其包括与输入端连接的输入匹配网络、与输出端连接的输出匹配网络，和1路功率放大电路，该功率放大电路包括差分功率晶体管1、差分功率晶体管2和级间匹配网络。该实施例的结构连接关系如下：输入匹配网络的输入端通过该差分功率放大器的输入端连接功率信号源，输入匹配网络的输出端连接第一级差分功率晶体管1的 输入端，第一级差分功率晶体管1的输出端连接第一级级间匹配网络的输入端，第一级级间匹配网络的输出端连接第二级差分功率晶体管2的输入端，第二级差分功率晶体管2的输出端连接输出匹配网络的输入端，最后输出匹配网络的输出端通过该差分功率放大器的输出端连接负载。其中输入匹配网络和级间匹配网络的形式可以为常用的传输线连接结构或者封装结构，也可采用公开号为CN110277965A、申请日为2018年3月15日、公布日为2019年9月24日的中国专利申请文本中记载的输入匹配网络和级间匹配网络，以及其图1和图2记载的现有技术中匹配单元的结构。One of the embodiments provides a structural schematic diagram of a single-channel two-stage ultra-wideband microwave millimeter-wave differential power amplifier when N=1 and Q=2, as shown in FIG. 2, which includes an input matching network connected to the input end, and An output matching network connected to the output end, and a power amplifier circuit. The power amplifier circuit includes a differential power transistor 1, a differential power transistor 2, and an inter-stage matching network. The structural connection relationship of this embodiment is as follows: the input end of the input matching network is connected to the power signal source through the input end of the differential power amplifier, the output end of the input matching network is connected to the input end of the first-stage differential power transistor 1, and the first-stage differential The output terminal of the power transistor 1 is connected to the input terminal of the first-stage inter-stage matching network, the output terminal of the first-stage inter-stage matching network is connected to the input terminal of the second-stage differential power transistor 2, and the output terminal of the second-stage differential power transistor 2 Connect the input end of the output matching network, and finally the output end of the output matching network is connected to the load through the output end of the differential power amplifier. The form of the input matching network and the inter-stage matching network can be a commonly used transmission line connection structure or a package structure, or the publication number is CN110277965A, the application date is March 15, 2018, and the publication date is September 24, 2019. The input matching network and the inter-stage matching network described in the Chinese patent application text, and the structure of the matching unit in the prior art described in Figs. 1 and 2 thereof.
其中另一种实施例提供的N＝2、Q＝2时的两路两级的超宽带微波毫米波差分功率放大器的结构示意图如图3所示，其包括与输入端连接的输入匹配网络、与输出端连接的输出匹配网络，和2路功率放大电路，每一路功率放大电路均包括差分功率晶体管1、差分功率晶体管2和级间匹配网络。该实施例的结构连接关系中，每一路功率放大电路的电路结构均与上一实施例中的功率放大电路的电路结构相同，此处不再赘述。其中输入匹配网络和级间匹配网络的形式可以为常用的传输线连接结构或者封装结构，也可采用公开号为CN110277965A、申请日为2018年3月15日、公布日为2019年9月24日的中国专利申请文本中记载的输入匹配网络和级间匹配网络，以及其图1和图2记载的现有技术中匹配单元的结构。The structure diagram of the two-channel two-stage ultra-wideband microwave millimeter wave differential power amplifier provided by another embodiment when N=2 and Q=2 is shown in Fig. 3, which includes an input matching network connected to the input terminal, An output matching network connected to the output terminal and two power amplifier circuits, each of which includes a differential power transistor 1, a differential power transistor 2, and an inter-stage matching network. In the structural connection relationship of this embodiment, the circuit structure of each power amplifier circuit is the same as the circuit structure of the power amplifier circuit in the previous embodiment, and will not be repeated here. The form of the input matching network and the inter-stage matching network can be a commonly used transmission line connection structure or a package structure, or the publication number is CN110277965A, the application date is March 15, 2018, and the publication date is September 24, 2019. The input matching network and the inter-stage matching network described in the Chinese patent application text, and the structure of the matching unit in the prior art described in Figs. 1 and 2 thereof.
上述输入匹配网络、级间匹配网络和输出匹配网络分别为在超宽带微波毫米波频率范围内提供所述差分功率晶体管所需要的输入、级间和输出阻抗的阻抗匹配网络。各输入匹配网络、级间匹配网络和输出匹配网络中，通过控制网络中耦合传输线的奇模和偶模特性阻抗，并且令其电长度小于四分之一波长，从而实现宽频带的阻抗变换。The above-mentioned input matching network, inter-stage matching network and output matching network are respectively impedance matching networks that provide the input, inter-stage and output impedances required by the differential power transistor in the ultra-wideband microwave millimeter wave frequency range. In each input matching network, inter-stage matching network and output matching network, by controlling the odd-mode and even-mode characteristic impedance of the coupled transmission line in the network, and making the electrical length less than a quarter wavelength, a broadband impedance transformation is realized.
其中功率晶体管采用场效应管或双极性晶体管。Among them, the power transistor adopts a field effect tube or a bipolar transistor.
在某些实施例中，上述增益增强网络包括在一对差分晶体管的差分输入输出端***的交叉互连的电容反馈网络。具体在本实施例中，如图4所示，上述各差分功率晶体管至少包括一对处于差分工作模式的功率晶体管：第一功率晶体管M1和第二功率晶体管M2；该增益增强网络包括第一中和电容C1和第二中和电容C2；其中第一功率晶体管M1的发射级接地，集电极与输出端口JOUT+连接，基极与输入端口JIN+连接；其中第二功率晶体管M2的发射级接地，集电极与输出端口JOUT-连接，基极与输入端口JIN-连接；第二功率晶体管M2的集电极通过第一中和电容C1与第一功率晶体管M1的基极连接；第一功率晶体管M1的集电极通过第二中和电容C2与第二功率晶体管M2的基极连接。也即：第一中和电容C1的一端与第一功率晶体管M1的基极连接，另一端与第二功率晶体管M2的集电极连接；第二中和电容C2的一端与第二功率晶体管M2的基极连接，另一端与第一功率晶体管M1的集电极连接。该增益增强网络的工作原理为利用差分工作模式所提供的一对反相信号，通过交叉互连的方式使第一和第二中和电容等效为电感。该等效电感与功率晶体管内部的基极-集电极电容谐振，从而消除该晶体管的负反馈环路，从而增强该差分功率晶体管的功率增益。In some embodiments, the above-mentioned gain enhancement network includes a cross-connected capacitive feedback network inserted at the differential input and output ends of a pair of differential transistors. Specifically, in this embodiment, as shown in FIG. 4, each of the above-mentioned differential power transistors includes at least a pair of power transistors in a differential operation mode: a first power transistor M1 and a second power transistor M2; the gain enhancement network includes a first power transistor. The emitter of the first power transistor M1 is grounded, the collector is connected to the output port JOUT+, and the base is connected to the input port JIN+; the emitter of the second power transistor M2 is grounded, and the collector is connected to the input port JIN+. The electrode is connected to the output port JOUT-, and the base is connected to the input port JIN-; the collector of the second power transistor M2 is connected to the base of the first power transistor M1 through the first neutralization capacitor C1; the collector of the first power transistor M1 The electrode is connected to the base of the second power transistor M2 through the second neutralization capacitor C2. That is: one end of the first neutralization capacitor C1 is connected to the base of the first power transistor M1, and the other end is connected to the collector of the second power transistor M2; one end of the second neutralization capacitor C2 is connected to the second power transistor M2 The base is connected, and the other end is connected to the collector of the first power transistor M1. The working principle of the gain enhancement network is to use a pair of inverted signals provided by the differential working mode to make the first and second neutralizing capacitors equivalent to inductances through cross interconnection. The equivalent inductance resonates with the base-collector capacitance inside the power transistor, thereby eliminating the negative feedback loop of the transistor, thereby enhancing the power gain of the differential power transistor.
在某些实施例中，上述增益增强网络包括分别连接在一对差分晶体管中的同一晶体管输入输出端的反馈传输线和隔直电容。具体在本实施例中，如图5所示，上述各差分功率晶体管至少包括一对处于差分工作模式的功率晶体管：第三功率晶体管M3和第四功率晶体管M4；所述增益增强网络包括第三隔直电容C3、第四隔直电容C4、第三反馈传输线TL3和第四反馈传输线TL4。其中第三功率晶体管M3的发射级接地，集电极与输出端口JOUT+连接， 基极与输入端口JIN+连接；其中第四功率晶体管M4的发射级接地，集电极与输出端口JOUT-连接，基极与输入端口JIN-连接；第三功率晶体管M3的集电极通过串联的第三反馈传输线TL3、第三隔直电容C3与第三功率晶体管M3的基极连接；第四功率晶体管M4的集电极通过串联的第四反馈传输线TL4、第四隔直电容C4与第四功率晶体管M4的基极连接。也即：第三隔直电容C3的一端与第三功率晶体管M3的基极连接，另一端与第三反馈传输线TL3的一端连接，第三反馈传输线TL3的另一端与第三功率晶体管M3的集电极连接；第四隔直电容C4的一端与第四功率晶体管M4的基极连接，另一端与第四反馈传输线TL4的一端连接，第四反馈传输线TL4的另一端与第四功率晶体管M4的集电极连接。该结构比上一实施例(图4)所示结构具有更大的设计自由度，并且在目标工作频率范围内可以更进一步地提升晶体管的增益。该网络不但可以实现上一实施例(图4)所示结构的性能，而且该增益增强网络可以为差分功率晶体管提供适当的正反馈环路，从而在保证该差分功率晶体管稳定的前提下进一步提升增益。In some embodiments, the above-mentioned gain enhancement network includes a feedback transmission line and a DC blocking capacitor respectively connected to the input and output terminals of the same transistor in a pair of differential transistors. Specifically, in this embodiment, as shown in FIG. 5, each of the above-mentioned differential power transistors includes at least a pair of power transistors in a differential operation mode: a third power transistor M3 and a fourth power transistor M4; the gain enhancement network includes a third power transistor. The DC blocking capacitor C3, the fourth DC blocking capacitor C4, the third feedback transmission line TL3, and the fourth feedback transmission line TL4. The emitter of the third power transistor M3 is grounded, the collector is connected to the output port JOUT+, and the base is connected to the input port JIN+; the emitter of the fourth power transistor M4 is grounded, the collector is connected to the output port JOUT-, and the base is connected to The input port JIN- is connected; the collector of the third power transistor M3 is connected to the base of the third power transistor M3 through the series-connected third feedback transmission line TL3 and the third DC blocking capacitor C3; the collector of the fourth power transistor M4 is connected in series through the The fourth feedback transmission line TL4 and the fourth DC blocking capacitor C4 are connected to the base of the fourth power transistor M4. That is, one end of the third DC blocking capacitor C3 is connected to the base of the third power transistor M3, the other end is connected to one end of the third feedback transmission line TL3, and the other end of the third feedback transmission line TL3 is connected to the set of the third power transistor M3. Electrode connection; one end of the fourth DC blocking capacitor C4 is connected to the base of the fourth power transistor M4, the other end is connected to one end of the fourth feedback transmission line TL4, and the other end of the fourth feedback transmission line TL4 is connected to the collection of the fourth power transistor M4 Electrode connection. This structure has greater design freedom than the structure shown in the previous embodiment (FIG. 4), and can further increase the gain of the transistor within the target operating frequency range. The network can not only achieve the performance of the structure shown in the previous embodiment (Figure 4), but also the gain enhancement network can provide a proper positive feedback loop for the differential power transistor, thereby further improving the stability of the differential power transistor. Gain.
上述输入匹配网络、级间匹配网络和输出匹配网络均包括若干对镜像对称设置的耦合传输线，以及与之适配的微带传输线和匹配电容。The above-mentioned input matching network, inter-stage matching network and output matching network all include several pairs of coupled transmission lines arranged in mirror symmetry, as well as microstrip transmission lines and matching capacitors adapted to them.
本发明中，上述输出匹配网络中包括M对镜像对称设置的耦合传输线，M≥1；每一对中的两个耦合传输线为左耦合传输线和右耦合传输线。In the present invention, the above-mentioned output matching network includes M pairs of coupled transmission lines arranged in mirror symmetry, M≥1; the two coupled transmission lines in each pair are left coupled transmission lines and right coupled transmission lines.
本发明中，上述输入匹配网络中包括N对镜像对称设置的耦合传输线，N≥1；每一对中的两个耦合传输线为左耦合传输线和右耦合传输线。In the present invention, the aforementioned input matching network includes N pairs of coupled transmission lines arranged in mirror symmetry, N≥1; the two coupled transmission lines in each pair are left coupled transmission lines and right coupled transmission lines.
本发明中，上述级间匹配网络中包括L对镜像对称设置的耦合传输线，L≥1；每一对中的两个耦合传输线为左耦合传输线和右耦合传输线。In the present invention, the above-mentioned inter-stage matching network includes L pairs of coupled transmission lines arranged in mirror symmetry, L≥1; the two coupled transmission lines in each pair are left coupled transmission lines and right coupled transmission lines.
当M＝N＝L＝1，且Q＝2时，该实施例提供的单路两级的超宽带微波毫米波差分功率放大器的结构示意图如图2所示。具体在该实施例中：When M=N=L=1 and Q=2, the structure diagram of the single-channel two-stage ultra-wideband microwave millimeter wave differential power amplifier provided in this embodiment is shown in FIG. 2. Specifically in this embodiment:
此时M＝1，所述输出匹配网络如图8所示只包括1对镜像对称设置的耦合传输线，具体的：该对中的两个耦合传输线的隔离端通过第二输出匹配电容C_k2连接；该对中的左耦合传输线的隔离端与输出端口OUTk+连接，该对中的右耦合传输线的隔离端与输出端口OUTk-连接；该对中的两个耦合传输线的直通端相连后通过第一输出微带传输线TL_Ak连接端口Ak；该对中的两个耦合传输线的耦合端相连；该对中的两个耦合传输线的输入端通过第一输出匹配电容C_k1连接；该对中的左耦合传输线的输入端与输入端口INk+连接，该对中的右耦合传输线的输入端与输入端口INk-连接。At this time M=1, the output matching network only includes a pair of coupled transmission lines arranged in mirror symmetry as shown in FIG. 8. Specifically: the isolated ends of the two coupled transmission lines in the pair are connected through the second output matching capacitor C_k2; The isolated end of the left-coupled transmission line in the pair is connected to the output port OUTk+, and the isolated end of the right-coupled transmission line in the pair is connected to the output port OUTk-; the through ends of the two coupled transmission lines in the pair are connected through the first output The microstrip transmission line TL_Ak is connected to the port Ak; the coupling ends of the two coupled transmission lines in the pair are connected; the input ends of the two coupled transmission lines in the pair are connected through the first output matching capacitor C_k1; the input of the left coupling transmission line in the pair The terminal is connected to the input port INk+, and the input terminal of the right-coupled transmission line in the pair is connected to the input port INk-.
此时N＝1，所述输入匹配网络如图6所示只包括1对镜像对称设置的耦合传输线，具体的：该对中的两个耦合传输线的隔离端通过第二匹配电容连接；该对中的左耦合传输线的隔离端与输出端口OUTi+连接，该对中的右耦合传输线的隔离端与输出端口OUTi-连接；该对中的两个耦合传输线的直通端相连；该对中的两个耦合传输线的耦合端相连，然后通过第一微带传输线TL_Ai连接端口Ai；该对中的两个耦合传输线的输入端通过第一匹配电容连接；该对中的左耦合传输线的输入端与输入端口INi+连接，该对中的右耦合传输线的输入端与输入端口INi-连接。At this time, N=1, the input matching network only includes a pair of coupled transmission lines arranged in mirror symmetry as shown in FIG. 6. Specifically: the isolated ends of the two coupled transmission lines in the pair are connected by a second matching capacitor; The isolated end of the left-coupled transmission line in the pair is connected to the output port OUTi+, and the isolated end of the right-coupled transmission line in the pair is connected to the output port OUTi-; the through ends of the two coupled transmission lines in the pair are connected; two of the pair The coupling end of the coupled transmission line is connected, and then the port Ai is connected through the first microstrip transmission line TL_Ai; the input ends of the two coupled transmission lines in the pair are connected through the first matching capacitor; the input end of the left coupling transmission line in the pair is connected to the input port INi+ is connected, and the input end of the right-coupled transmission line in the pair is connected to the input port INi-.
此时L＝1，所述级间匹配网络如图7所示只包括1对镜像对称设置的耦合传输线，具体的：该对中的两个耦合传输线的隔离端通过第二级间匹配电容C_j2连接；该对中的左耦合传输线的隔离端与端口OUTj+连接，每一对中的右耦合传输线的隔离端与端口OUTj-连 接；该对中的两个耦合传输线的直通端相连后通过第二级间微带传输线TL_Bj连接输出端口Bj；该对中的两个耦合传输线的耦合端相连后通过第一级间微带传输线TL_Aj连接输出端口Aj；该对中的两个耦合传输线的输入端通过第一级间匹配电容C_j1连接；该对中的左耦合传输线的输入端与输入端口INj+连接，该对中的右耦合传输线的输入端与输入端口INj-连接。At this time, L=1, the inter-stage matching network as shown in Fig. 7 only includes a pair of coupled transmission lines arranged in mirror symmetry. Specifically: the isolation ends of the two coupled transmission lines in the pair pass through the second inter-stage matching capacitor C_j2 Connection; the isolated end of the left-coupled transmission line in the pair is connected to port OUTj+, the isolated end of the right-coupled transmission line in each pair is connected to port OUTj-; the through ends of the two coupled transmission lines in the pair are connected through the second The inter-stage microstrip transmission line TL_Bj is connected to the output port Bj; the coupling ends of the two coupled transmission lines in the pair are connected to the output port Aj through the first inter-stage microstrip transmission line TL_Aj; the input ends of the two coupled transmission lines in the pair pass The first interstage matching capacitor C_j1 is connected; the input end of the left-coupled transmission line in the pair is connected to the input port INj+, and the input end of the right-coupled transmission line in the pair is connected to the input port INj-.
当M＝N＝L＝2，且Q＝2时，该实施例提供的两路两级的超宽带微波毫米波差分功率放大器的结构示意图如图3所示。具体在这一实施例中：When M=N=L=2 and Q=2, the schematic diagram of the structure of the two-channel two-stage ultra-wideband microwave millimeter wave differential power amplifier provided in this embodiment is shown in FIG. 3. Specifically in this embodiment:
此时M＝2，所述输出匹配网络如图11所示，包括2对镜像对称设置的耦合传输线，具体的：At this time M=2, the output matching network is shown in Fig. 11, including two pairs of coupled transmission lines arranged in mirror symmetry, specifically:
左侧一对中的两个耦合传输线的输入端通过第三匹配电容C_K3连接；右侧一对中的两个耦合传输线的输入端通过第四匹配电容C_K4连接；左侧一对耦合传输线中的左耦合传输线的输入端与输入端口INK1+连接，左侧一对耦合传输线中的右耦合传输线的输入端与输入端口INK1-连接，右侧一对耦合传输线中的左耦合传输线的输入端与输入端口INK2+连接，右侧一对耦合传输线中的右耦合传输线的输入端与输入端口INK2-连接；The input ends of the two coupled transmission lines in the pair on the left are connected through the third matching capacitor C_K3; the input ends of the two coupled transmission lines in the pair on the right are connected through the fourth matching capacitor C_K4; The input end of the left coupling transmission line is connected to the input port INK1+, the input end of the right coupling transmission line of the left pair of coupling transmission lines is connected to the input port INK1-, and the input end of the left coupling transmission line of the right pair of coupling transmission lines is connected to the input port INK2+ connection, the input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the input port INK2-;
左侧一对中的两个耦合传输线的耦合端相连；右侧一对中的两个耦合传输线的耦合端相连；The coupling ends of the two coupled transmission lines in the pair on the left are connected; the coupling ends of the two coupled transmission lines in the pair on the right are connected;
左侧一对中的两个耦合传输线的直通端相连后通过第二输出微带传输线TL_AK连接端口AK；右侧一对中的两个耦合传输线的直通端相连后通过第三微带传输线TL_BK连接端口BK；The through ends of the two coupled transmission lines in the left pair are connected through the second output microstrip transmission line TL_AK to connect to port AK; the through ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_BK Port BK;
左侧一对耦合传输线中左耦合传输线的隔离端和右侧一对耦合传输线中右耦合传输线的隔离端通过第三输出匹配电容C_K5连接；左侧一对耦合传输线中左耦合传输线的隔离端与输出端口OUTK+连接，右侧一对耦合传输线中右耦合传输线的隔离端与输出端口OUTK-连接；The isolated end of the left coupled transmission line in the left pair of coupled transmission lines and the isolated end of the right coupled transmission line in the right pair of coupled transmission lines are connected by the third output matching capacitor C_K5; the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with The output port OUTK+ is connected, and the isolated end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the output port OUTK-;
左侧一对耦合传输线中右耦合传输线的隔离端和右侧一对耦合传输线中左耦合传输线的隔离端相连。The isolated end of the right coupled transmission line in the pair of coupled transmission lines on the left is connected to the isolated end of the left coupled transmission line in the pair of coupled transmission lines on the right.
此时N＝2，所述输入匹配网络如图9所示，包括2对镜像对称设置的耦合传输线，具体的：At this time, N=2, and the input matching network is shown in Fig. 9 and includes two pairs of coupled transmission lines arranged in mirror symmetry. Specifically:
左侧一对中的两个耦合传输线的隔离端通过第四匹配电容C_I4连接；右侧一对中的两个耦合传输线的隔离端通过第五匹配电容C_I5连接；左侧一对耦合传输线的中的左耦合传输线的隔离端与输出端口OUTI1+连接，左侧一对耦合传输线的中的右耦合传输线的隔离端与输出端口OUTI1-连接；右侧一对耦合传输线的中的左耦合传输线的隔离端与输出端口OUTI2+连接，右侧一对耦合传输线的中的右耦合传输线的隔离端与输出端口OUTI2-连接。The isolated ends of the two coupled transmission lines in the left pair are connected by the fourth matching capacitor C_I4; the isolated ends of the two coupled transmission lines in the right pair are connected by the fifth matching capacitor C_I5; the middle of the left pair of coupled transmission lines The isolated end of the left-coupled transmission line is connected to the output port OUTI1+, the isolated end of the right-coupled transmission line in the left pair of coupled transmission lines is connected to the output port OUTI1-; the isolated end of the left-coupled transmission line in the right pair of coupled transmission lines It is connected to the output port OUTI2+, and the isolation end of the right coupling transmission line in the pair of right coupling transmission lines is connected to the output port OUTI2-.
具体为：左侧一对耦合传输线中左耦合传输线的隔离端和右耦合传输线的隔离端通过第四匹配电容C_I4连接；右侧一对耦合传输线中左耦合传输线的隔离端和右耦合传输线的隔离端通过第五匹配电容C_I5连接。Specifically: the isolation end of the left coupling transmission line and the isolation end of the right coupling transmission line in the pair of coupled transmission lines on the left are connected by a fourth matching capacitor C_I4; the isolation end of the left coupling transmission line and the isolation end of the right coupling transmission line in the pair of coupling transmission lines on the right The terminal is connected through the fifth matching capacitor C_I5.
左侧一对中的两个耦合传输线的直通端相连；右侧一对中的两个耦合传输线的直通端相连；也即具体为：左侧一对耦合传输线中左耦合传输线的直通端和右耦合传输线的直通端相连；右侧一对耦合传输线中左耦合传输线的直通端和右耦合传输线的直通端相 连。The through ends of the two coupled transmission lines in the left pair are connected; the through ends of the two coupled transmission lines in the right pair are connected; that is, the through ends and the right ends of the left coupled transmission line in the left pair of coupled transmission lines are connected. The through end of the coupled transmission line is connected; the through end of the left coupled transmission line in the pair of coupled transmission lines on the right is connected with the through end of the right coupled transmission line.
左侧一对中的两个耦合传输线的耦合端相连后通过第二微带传输线TL_AI1连接端口AI1；右侧一对中的两个耦合传输线的耦合端相连后通过第三微带传输线TL_AI2连接端口AI2；也即：左侧一对耦合传输线中左耦合传输线的耦合端和右耦合传输线的耦合端相连后通过第二微带传输线TL_AI1连接端口AI1；右侧一对耦合传输线中左耦合传输线的耦合端和右耦合传输线的耦合端相连后通过第三微带传输线TL_AI2连接端口AI2；The coupling ends of the two coupled transmission lines in the left pair are connected through the second microstrip transmission line TL_AI1 to connect to port AI1; the coupling ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_AI2 to connect to the port AI2; that is: the coupling end of the left coupling transmission line and the coupling end of the right coupling transmission line in the pair of coupling transmission lines on the left are connected through the second microstrip transmission line TL_AI1 to connect to port AI1; the coupling of the left coupling transmission line in the pair of coupling transmission lines on the right After connecting with the coupling end of the right coupling transmission line, connect the port AI2 through the third microstrip transmission line TL_AI2;
左侧一对耦合传输线中左耦合传输线的输入端和右侧一对耦合传输线中右耦合传输线的输入端通过第三匹配电容C_I3连接；左侧一对耦合传输线中左耦合传输线的输入端与输入端口INI+连接，右侧一对耦合传输线中右耦合传输线的输入端与输入端口INI-连接；The input end of the left coupled transmission line in the left pair of coupled transmission lines and the input end of the right coupled transmission line in the right pair of coupled transmission lines are connected by a third matching capacitor C_I3; the input end of the left coupled transmission line in the left pair of coupled transmission lines is connected to the input Port INI+ connection, the input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the input port INI-;
左侧一对耦合传输线中右耦合传输线的输入端和右侧一对耦合传输线中左耦合传输线的输入端相连。The input end of the right coupling transmission line in the pair of coupling transmission lines on the left is connected to the input end of the left coupling transmission line in the pair of coupling transmission lines on the right.
此时L＝2，所述级间匹配网络如图10所示，包括2对镜像对称设置的耦合传输线，具体的：At this time L=2, the inter-stage matching network is shown in Fig. 10, including two pairs of coupled transmission lines arranged in mirror symmetry, specifically:
左侧一对中的两个耦合传输线的隔离端通过第五级间匹配电容C_J5连接；The isolation ends of the two coupled transmission lines in the left pair are connected through the fifth inter-stage matching capacitor C_J5;
右侧一对中的两个耦合传输线的隔离端通过第六级间匹配电容C_J6连接；The isolation ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage matching capacitor C_J6;
左侧一对耦合传输线中的左耦合传输线的隔离端与输出端口OUTJ1+连接，The isolation end of the left coupling transmission line in the pair of coupling transmission lines on the left is connected to the output port OUTJ1+,
左侧一对耦合传输线中的右耦合传输线的隔离端与输出端口OUTJ1-连接；The isolation end of the right coupling transmission line in the pair of coupling transmission lines on the left is connected to the output port OUTJ1-;
右侧一对耦合传输线中的左耦合传输线的隔离端与输出端口OUTJ2+连接，The isolation end of the left coupling transmission line in the pair of coupling transmission lines on the right is connected to the output port OUTJ2+,
右侧一对耦合传输线中的右耦合传输线的隔离端与输出端口OUTJ2-连接；The isolation end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the output port OUTJ2-;
左侧一对中的两个耦合传输线的直通端相连后通过第五级间微带传输线TL_BJ1连接端口BJ1；右侧一对中的两个耦合传输线的直通端相连后通过第六级间微带传输线TL_BJ2连接端口BJ2；The through ends of the two coupled transmission lines in the pair on the left are connected through the fifth inter-stage microstrip transmission line TL_BJ1 to connect to port BJ1; the through ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage microstrip Transmission line TL_BJ2 connects to port BJ2;
左侧一对中的两个耦合传输线的耦合端相连后通过第三级间微带传输线TL_AJ1连接端口AJ1；右侧一对中的两个耦合传输线的耦合端相连后通过第四级间微带传输线TL_AJ2连接端口AJ2；The coupling ends of the two coupled transmission lines in the pair on the left are connected through the third inter-level microstrip transmission line TL_AJ1 to connect to port AJ1; the coupling ends of the two coupled transmission lines in the right pair are connected through the fourth inter-level microstrip Transmission line TL_AJ2 connects to port AJ2;
左侧一对中的两个耦合传输线的输入端通过第三级间匹配电容C_J3连接；The input ends of the two coupled transmission lines in the left pair are connected through the third inter-stage matching capacitor C_J3;
右侧一对中的两个耦合传输线的输入端通过第四级间匹配电容C_J4连接；The input ends of the two coupled transmission lines in the right pair are connected through the fourth inter-stage matching capacitor C_J4;
左侧一对耦合传输线中的左耦合传输线的输入端与输入端口INJ1+连接，左侧一对耦合传输线中的右耦合传输线的输入端与输入端口INJ1-连接；右侧一对耦合传输线中的左耦合传输线的输入端与输入端口INJ2+，右侧一对耦合传输线中的右耦合传输线的输入端与输入端口INJ2-连接。The input end of the left coupling transmission line of the left pair of coupled transmission lines is connected to the input port INJ1+, and the input end of the right coupling transmission line of the left pair of coupled transmission lines is connected to the input port INJ1-; the left of the right pair of coupled transmission lines The input end of the coupling transmission line is connected to the input port INJ2+, and the input end of the right coupling transmission line of the pair of coupling transmission lines on the right is connected to the input port INJ2-.
在这一实施例中，位于同一匹配网络中各耦合传输线的电气参数相等且其电长度小于90度。其中匹配电容为晶体管寄生电容或MIM电容或MOM电容。其中微带传输线为直流偏置网络。也即：位于同一输入匹配网络中各耦合传输线的电气参数相等且其电长度小于90度；位于同一级间匹配网络中各耦合传输线的电气参数相等且其电长度小于90度；位于同一输出匹配网络中各耦合传输线的电气参数相等且其电长度小于90度。In this embodiment, the electrical parameters of the coupled transmission lines in the same matching network are equal and their electrical lengths are less than 90 degrees. The matching capacitance is the parasitic capacitance of the transistor or MIM capacitance or MOM capacitance. The microstrip transmission line is a DC bias network. That is: the electrical parameters of the coupled transmission lines in the same input matching network are equal and their electrical lengths are less than 90 degrees; the electrical parameters of the coupled transmission lines in the same inter-stage matching network are equal and their electrical lengths are less than 90 degrees; they are located in the same output matching network. The electrical parameters of each coupled transmission line in the network are equal and the electrical length is less than 90 degrees.
以上仅是本发明的优选实施方式，应当指出以上实施列对本发明不构成限定，相关工作人员在不偏离本发明技术思想的范围内，所进行的多样变化和修改，均落在本发明的保护范围内。The above are only the preferred embodiments of the present invention. It should be pointed out that the above implementation list does not limit the present invention. Various changes and modifications made by relevant staff within the scope of the technical idea of the present invention fall under the protection of the present invention. Within range.

Claims (10)

  1. 一种超宽带微波毫米波差分功率放大器，其特征在于：包括输入端、输出端、与输入端连接的输入匹配网络、与输出端连接的输出匹配网络、以及并联于输入匹配网络和输出匹配网络之间的N路功率放大电路，N为该功率放大器中功率放大电路的路数，N≥1；An ultra-wideband microwave and millimeter wave differential power amplifier, which is characterized by: comprising an input end, an output end, an input matching network connected to the input end, an output matching network connected to the output end, and an input matching network and an output matching network connected in parallel N power amplifying circuits between, N is the number of power amplifying circuits in the power amplifier, N≥1;
    每一路功率放大电路中包括Q个差分功率晶体管，Q为该功率放大电路的级数，Q≥1；位于同一路上的两个相邻的差分功率晶体管通过级间匹配网络连接；Each power amplifier circuit includes Q differential power transistors, Q is the number of stages of the power amplifier circuit, Q≥1; two adjacent differential power transistors on the same road are connected by an inter-stage matching network;
    所述各差分功率晶体管至少包括一对处于差分工作模式的功率晶体管和增益增强网络。Each of the differential power transistors includes at least a pair of power transistors in a differential working mode and a gain enhancement network.
  2. 根据权利要求1所述的超宽带微波毫米波差分功率放大器，其特征在于：所述输入匹配网络、级间匹配网络和输出匹配网络分别为在超宽带微波毫米波频率范围内提供所述差分功率晶体管所需要的输入、级间和输出阻抗的阻抗匹配网络。The ultra-wideband microwave and millimeter wave differential power amplifier according to claim 1, wherein the input matching network, the inter-stage matching network and the output matching network respectively provide the differential power in the ultra-wideband microwave and millimeter wave frequency range. The impedance matching network of the input, inter-stage and output impedance required by the transistor.
  3. 根据权利要求1所述的超宽带微波毫米波差分功率放大器，其特征在于：所述功率晶体管为场效应管或双极性晶体管。The ultra-wideband microwave and millimeter wave differential power amplifier according to claim 1, wherein the power transistor is a field effect tube or a bipolar transistor.
  4. 根据权利要求1所述的超宽带微波毫米波差分功率放大器，其特征在于：所述增益增强网络包括在一对差分晶体管的差分输入输出端***的交叉互连的电容反馈网络；或The ultra-wideband microwave and millimeter wave differential power amplifier according to claim 1, wherein the gain enhancement network comprises a cross-connected capacitive feedback network inserted at the differential input and output ends of a pair of differential transistors; or
    所述增益增强网络包括分别连接在一对差分晶体管中的同一晶体管输入输出端的反馈传输线和隔直电容。The gain enhancement network includes a feedback transmission line and a DC blocking capacitor respectively connected to the input and output ends of the same transistor in a pair of differential transistors.
  5. 根据权利要求1所述的超宽带微波毫米波差分功率放大器，其特征在于：所述输出匹配网络中包括M对镜像对称设置的耦合传输线，M≥1；每一对中的两个耦合传输线为左耦合传输线和右耦合传输线；The ultra-wideband microwave and millimeter wave differential power amplifier according to claim 1, wherein the output matching network includes M pairs of coupled transmission lines arranged in mirror symmetry, M≥1; the two coupled transmission lines in each pair are Left coupling transmission line and right coupling transmission line;
    当M＝1时，所述输出匹配网络只包括1对镜像对称设置的耦合传输线：When M=1, the output matching network only includes a pair of coupled transmission lines arranged in mirror symmetry:
    该对中的两个耦合传输线的隔离端通过第二输出匹配电容C_k2连接；该对中的左耦合传输线的隔离端与端口OUTk+连接，该对中的右耦合传输线的隔离端与端口OUTk-连接；The isolated ends of the two coupled transmission lines in the pair are connected through the second output matching capacitor C_k2; the isolated end of the left coupled transmission line in the pair is connected to the port OUTk+, and the isolated end of the right coupled transmission line in the pair is connected to the port OUTk- ；
    该对中的两个耦合传输线的直通端相连后通过第一输出微带传输线TL_Ak连接端口Ak；The through ends of the two coupled transmission lines in the pair are connected to the port Ak through the first output microstrip transmission line TL_Ak;
    该对中的两个耦合传输线的耦合端相连；The coupling ends of the two coupled transmission lines in the pair are connected;
    该对中的两个耦合传输线的输入端通过第一输出匹配电容C_k1连接；该对中的左耦合传输线的输入端与端口INk+连接，该对中的右耦合传输线的输入端与端口INk-连接；The input ends of the two coupled transmission lines in the pair are connected through the first output matching capacitor C_k1; the input end of the left coupled transmission line in the pair is connected to the port INk+, and the input end of the right coupled transmission line in the pair is connected to the port INk- ；
    当M＝2时，所述输出匹配网络包括2对镜像对称设置的耦合传输线：When M=2, the output matching network includes 2 pairs of coupled transmission lines arranged in mirror symmetry:
    左侧一对中的两个耦合传输线的输入端通过第三匹配电容C_K3连接；右侧一对中的两个耦合传输线的输入端通过第四匹配电容C_K4连接；左侧一对耦合传输线中的左耦合传输线的输入端与端口INK1+连接，左侧一对耦合传输线中的右耦合传输线的输入端与端口INK1-连接，右侧一对耦合传输线中的左耦合传输线的输入端与端口INK2+连接，右侧一对耦合传输线中的右耦合传输线的输入端与端口INK2-连接；The input ends of the two coupled transmission lines in the pair on the left are connected through the third matching capacitor C_K3; the input ends of the two coupled transmission lines in the pair on the right are connected through the fourth matching capacitor C_K4; The input end of the left coupling transmission line is connected to the port INK1+, the input end of the right coupling transmission line of the left pair of coupling transmission lines is connected to the port INK1-, and the input end of the left coupling transmission line of the right pair of coupling transmission lines is connected to the port INK2+, The input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the port INK2-;
    左侧一对中的两个耦合传输线的耦合端相连；右侧一对中的两个耦合传输线的耦合端相连；The coupling ends of the two coupled transmission lines in the pair on the left are connected; the coupling ends of the two coupled transmission lines in the pair on the right are connected;
    左侧一对中的两个耦合传输线的直通端相连后通过第二输出微带传输线TL_AK连接端口AK；右侧一对中的两个耦合传输线的直通端相连后通过第三微带传输线TL_BK连接端口BK；The through ends of the two coupled transmission lines in the left pair are connected through the second output microstrip transmission line TL_AK to connect to port AK; the through ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_BK Port BK;
    左侧一对耦合传输线中左耦合传输线的隔离端和右侧一对耦合传输线中右耦合传输 线的隔离端通过第三输出匹配电容C_K5连接；左侧一对耦合传输线中左耦合传输线的隔离端与端口OUTK+连接，右侧一对耦合传输线中右耦合传输线的隔离端与端口OUTK-连接；The isolated end of the left coupled transmission line in the left pair of coupled transmission lines and the isolated end of the right coupled transmission line in the right pair of coupled transmission lines are connected by the third output matching capacitor C_K5; the isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected with The port OUTK+ is connected, and the isolated end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the port OUTK-;
    左侧一对耦合传输线中右耦合传输线的隔离端和右侧一对耦合传输线中左耦合传输线的隔离端相连。The isolated end of the right coupled transmission line in the pair of coupled transmission lines on the left is connected to the isolated end of the left coupled transmission line in the pair of coupled transmission lines on the right.
  6. 根据权利要求1所述的超宽带微波毫米波差分功率放大器，其特征在于：The ultra-wideband microwave and millimeter wave differential power amplifier according to claim 1, characterized in that:
    所述各差分功率晶体管至少包括一对处于差分工作模式的功率晶体管：第一功率晶体管M1和第二功率晶体管M2；Each of the differential power transistors includes at least a pair of power transistors in a differential operation mode: a first power transistor M1 and a second power transistor M2;
    所述增益增强网络包括第一中和电容C1和第二中和电容C2；The gain enhancement network includes a first neutralization capacitor C1 and a second neutralization capacitor C2;
    其中第一功率晶体管M1的发射级接地，集电极与端口JOUT+连接，基极与端口JIN+连接；其中第二功率晶体管M2的发射级接地，集电极与端口JOUT-连接，基极与端口JIN-连接；The emitter of the first power transistor M1 is grounded, the collector is connected to the port JOUT+, and the base is connected to the port JIN+; the emitter of the second power transistor M2 is grounded, the collector is connected to the port JOUT-, and the base is connected to the port JIN- connection;
    第二功率晶体管M2的集电极通过第一中和电容C1与第一功率晶体管M1的基极连接；第一功率晶体管M1的集电极通过第二中和电容C2与第二功率晶体管M2的基极连接。The collector of the second power transistor M2 is connected to the base of the first power transistor M1 through the first neutralization capacitor C1; the collector of the first power transistor M1 is connected to the base of the second power transistor M2 through the second neutralization capacitor C2 connection.
  7. 根据权利要求1所述的超宽带微波毫米波差分功率放大器，其特征在于：The ultra-wideband microwave and millimeter wave differential power amplifier according to claim 1, characterized in that:
    所述各差分功率晶体管至少包括一对处于差分工作模式的功率晶体管：第三功率晶体管M3和第四功率晶体管M4；Each of the differential power transistors includes at least a pair of power transistors in a differential operation mode: a third power transistor M3 and a fourth power transistor M4;
    所述增益增强网络包括第三隔直电容C3、第四隔直电容C4、第三反馈传输线TL3和第四反馈传输线TL4；The gain enhancement network includes a third DC blocking capacitor C3, a fourth DC blocking capacitor C4, a third feedback transmission line TL3, and a fourth feedback transmission line TL4;
    其中第三功率晶体管M3的发射级接地，集电极与端口JOUT+连接，基极与端口JIN+连接；其中第四功率晶体管M4的发射级接地，集电极与端口JOUT-连接，基极与端口JIN-连接；The emitter of the third power transistor M3 is grounded, the collector is connected to the port JOUT+, and the base is connected to the port JIN+; the emitter of the fourth power transistor M4 is grounded, the collector is connected to the port JOUT-, and the base is connected to the port JIN- connection;
    第三功率晶体管M3的集电极通过串联的第三反馈传输线TL3、第三隔直电容C3与第三功率晶体管M3的基极连接；第四功率晶体管M4的集电极通过串联的第四反馈传输线TL4、第四隔直电容C4与第四功率晶体管M4的基极连接。The collector of the third power transistor M3 is connected to the base of the third power transistor M3 through the series-connected third feedback transmission line TL3 and the third DC blocking capacitor C3; the collector of the fourth power transistor M4 is connected through the series-connected fourth feedback transmission line TL4 , The fourth DC blocking capacitor C4 is connected to the base of the fourth power transistor M4.
  8. 根据权利要求1所述的超宽带微波毫米波差分功率放大器，其特征在于：所述输入匹配网络、级间匹配网络和输出匹配网络均包括若干对镜像对称设置的耦合传输线，以及与之适配的微带传输线和匹配电容；The ultra-wideband microwave and millimeter wave differential power amplifier according to claim 1, wherein the input matching network, the inter-stage matching network, and the output matching network all comprise several pairs of coupled transmission lines arranged in mirror symmetry, and adapted to Microstrip transmission line and matching capacitor;
    位于同一匹配网络中各耦合传输线的电气参数相等且其电长度小于90度；The electrical parameters of the coupled transmission lines in the same matching network are equal and their electrical length is less than 90 degrees;
    其中匹配电容为晶体管寄生电容或MIM电容或MOM电容；The matching capacitance is the parasitic capacitance of the transistor or MIM capacitance or MOM capacitance;
    其中微带传输线为直流偏置网络。The microstrip transmission line is a DC bias network.
  9. 根据权利要求1所述的超宽带微波毫米波差分功率放大器，其特征在于：The ultra-wideband microwave and millimeter wave differential power amplifier according to claim 1, characterized in that:
    所述输入匹配网络中包括N对镜像对称设置的耦合传输线，N≥1；每一对中的两个耦合传输线为左耦合传输线和右耦合传输线；The input matching network includes N pairs of coupled transmission lines arranged in mirror symmetry, N≥1; the two coupled transmission lines in each pair are a left coupled transmission line and a right coupled transmission line;
    当N＝1时，所述输入匹配网络只包括1对镜像对称设置的耦合传输线：When N=1, the input matching network only includes a pair of coupled transmission lines arranged in mirror symmetry:
    该对中的两个耦合传输线的隔离端通过第二匹配电容连接；该对中的左耦合传输线的隔离端与端口OUTi+连接，该对中的右耦合传输线的隔离端与端口OUTi-连接；The isolated ends of the two coupled transmission lines in the pair are connected by a second matching capacitor; the isolated end of the left coupled transmission line in the pair is connected to the port OUTi+, and the isolated end of the right coupled transmission line in the pair is connected to the port OUTi-;
    该对中的两个耦合传输线的直通端相连；The through ends of the two coupled transmission lines in the pair are connected;
    该对中的两个耦合传输线的耦合端相连，然后通过第一微带传输线TL_Ai连接端口Ai；The coupling ends of the two coupled transmission lines in the pair are connected, and then the first microstrip transmission line TL_Ai is connected to the port Ai;
    该对中的两个耦合传输线的输入端通过第一匹配电容连接；该对中的左耦合传输线的输入端与端口INi+连接，该对中的右耦合传输线的输入端与端口INi-连接；The input ends of the two coupled transmission lines in the pair are connected by a first matching capacitor; the input end of the left coupled transmission line in the pair is connected to the port INi+, and the input end of the right coupled transmission line in the pair is connected to the port INi-;
    当N＝2时，所述输入匹配网络包括2对镜像对称设置的耦合传输线：When N=2, the input matching network includes 2 pairs of coupled transmission lines arranged in mirror symmetry:
    左侧一对中的两个耦合传输线的隔离端通过第四匹配电容C_I4连接；右侧一对中的两个耦合传输线的隔离端通过第五匹配电容C_I5连接；左侧一对耦合传输线的中的左耦合传输线的隔离端与端口OUTI1+连接，左侧一对耦合传输线的中的右耦合传输线的隔离端与端口OUTI1-连接；右侧一对耦合传输线的中的左耦合传输线的隔离端与端口OUTI2+连接，右侧一对耦合传输线的中的右耦合传输线的隔离端与端口OUTI2-连接；The isolated ends of the two coupled transmission lines in the left pair are connected by the fourth matching capacitor C_I4; the isolated ends of the two coupled transmission lines in the right pair are connected by the fifth matching capacitor C_I5; the middle of the left pair of coupled transmission lines The isolated end of the left-coupled transmission line is connected to the port OUTI1+, the isolated end of the right-coupled transmission line of the left pair of coupled transmission lines is connected to the port OUTI1-; the isolated end of the left-coupled transmission line of the right pair of coupled transmission lines is connected to the port OUTI2+ connection, the isolated end of the right coupling transmission line of the pair of coupling transmission lines on the right is connected to the port OUTI2-;
    左侧一对中的两个耦合传输线的直通端相连；右侧一对中的两个耦合传输线的直通端相连；The through ends of the two coupled transmission lines in the pair on the left are connected; the through ends of the two coupled transmission lines in the pair on the right are connected;
    左侧一对中的两个耦合传输线的耦合端相连后通过第二微带传输线TL_AI1连接端口AI1；右侧一对中的两个耦合传输线的耦合端相连后通过第三微带传输线TL_AI2连接端口AI2；The coupling ends of the two coupled transmission lines in the left pair are connected through the second microstrip transmission line TL_AI1 to connect to port AI1; the coupling ends of the two coupled transmission lines in the right pair are connected through the third microstrip transmission line TL_AI2 to connect to the port AI2;
    左侧一对耦合传输线中左耦合传输线的输入端和右侧一对耦合传输线中右耦合传输线的输入端通过第三匹配电容C_I3连接；左侧一对耦合传输线中左耦合传输线的输入端与端口INI+连接，右侧一对耦合传输线中右耦合传输线的输入端与端口INI-连接；The input end of the left coupled transmission line in the left pair of coupled transmission lines and the input end of the right coupled transmission line in the right pair of coupled transmission lines are connected by a third matching capacitor C_I3; the input end and port of the left coupled transmission line in the left pair of coupled transmission lines INI+ connection, the input end of the right coupling transmission line in the pair of coupling transmission lines on the right is connected to the port INI-;
    左侧一对耦合传输线中右耦合传输线的输入端和右侧一对耦合传输线中左耦合传输线的输入端相连。The input end of the right coupling transmission line in the pair of coupling transmission lines on the left is connected to the input end of the left coupling transmission line in the pair of coupling transmission lines on the right.
  10. 根据权利要求1所述的超宽带微波毫米波差分功率放大器，其特征在于：所述级间匹配网络中包括L对镜像对称设置的耦合传输线，L≥1；每一对中的两个耦合传输线为左耦合传输线和右耦合传输线；The ultra-wideband microwave and millimeter wave differential power amplifier according to claim 1, wherein the inter-stage matching network includes L pairs of mirror-symmetrically arranged coupled transmission lines, L≥1; two coupled transmission lines in each pair Is the left-coupled transmission line and the right-coupled transmission line;
    当L＝1时，所述级间匹配网络只包括1对镜像对称设置的耦合传输线：When L=1, the inter-stage matching network only includes 1 pair of coupled transmission lines arranged in mirror symmetry:
    该对中的两个耦合传输线的隔离端通过第二级间匹配电容C_j2连接；该对中的左耦合传输线的隔离端与端口OUTj+连接，每一对中的右耦合传输线的隔离端与端口OUTj-连接；The isolated ends of the two coupled transmission lines in the pair are connected through the second inter-stage matching capacitor C_j2; the isolated end of the left coupled transmission line in the pair is connected to port OUTj+, and the isolated end of the right coupled transmission line in each pair is connected to port OUTj -connection;
    该对中的两个耦合传输线的直通端相连后通过第二级间微带传输线TL_Bj连接端口Bj；The through ends of the two coupled transmission lines in the pair are connected to the port Bj through the second inter-level microstrip transmission line TL_Bj;
    该对中的两个耦合传输线的耦合端相连后通过第一级间微带传输线TL_Aj连接端口Aj；The coupling ends of the two coupled transmission lines in the pair are connected to the port Aj through the first inter-level microstrip transmission line TL_Aj;
    该对中的两个耦合传输线的输入端通过第一级间匹配电容C_j1连接；该对中的左耦合传输线的输入端与端口INj+连接，该对中的右耦合传输线的输入端与端口INj-连接；The input ends of the two coupled transmission lines in the pair are connected through the first interstage matching capacitor C_j1; the input end of the left coupled transmission line in the pair is connected to the port INj+, and the input end of the right coupled transmission line in the pair is connected to the port INj- connection;
    当L＝2时，所述级间匹配网络包括2对镜像对称设置的耦合传输线：When L=2, the inter-stage matching network includes 2 pairs of coupled transmission lines arranged in mirror symmetry:
    左侧一对中的两个耦合传输线的隔离端通过第五级间匹配电容C_J5连接；The isolation ends of the two coupled transmission lines in the left pair are connected through the fifth inter-stage matching capacitor C_J5;
    右侧一对中的两个耦合传输线的隔离端通过第六级间匹配电容C_J6连接；The isolation ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage matching capacitor C_J6;
    左侧一对耦合传输线中的左耦合传输线的隔离端与端口OUTJ1+连接，左侧一对耦合传输线中的右耦合传输线的隔离端与端口OUTJ1-连接；右侧一对耦合传输线中的左耦合传输线的隔离端与端口OUTJ2+连接，右侧一对耦合传输线中的右耦合传输线的隔离端与端口OUTJ2-连接；The isolated end of the left coupled transmission line in the left pair of coupled transmission lines is connected to port OUTJ1+, the isolated end of the right coupled transmission line of the left pair of coupled transmission lines is connected to port OUTJ1-; the left coupled transmission line of the right pair of coupled transmission lines The isolated end of the right is connected to the port OUTJ2+, and the isolated end of the right coupled transmission line of the pair of coupled transmission lines on the right is connected to the port OUTJ2-;
    左侧一对中的两个耦合传输线的直通端相连后通过第五级间微带传输线TL_BJ1连接端口BJ1；右侧一对中的两个耦合传输线的直通端相连后通过第六级间微带传输线TL_BJ2连接端口BJ2；The through ends of the two coupled transmission lines in the pair on the left are connected through the fifth inter-stage microstrip transmission line TL_BJ1 to connect to port BJ1; the through ends of the two coupled transmission lines in the right pair are connected through the sixth inter-stage microstrip Transmission line TL_BJ2 connects to port BJ2;
    左侧一对中的两个耦合传输线的耦合端相连后通过第三级间微带传输线TL_AJ1连接端口AJ1；右侧一对中的两个耦合传输线的耦合端相连后通过第四级间微带传输线TL_AJ2 连接端口AJ2；The coupling ends of the two coupled transmission lines in the left pair are connected through the third inter-stage microstrip transmission line TL_AJ1 to connect to port AJ1; the coupling ends of the two coupled transmission lines in the right pair are connected through the fourth inter-stage microstrip Transmission line TL_AJ2 connects to port AJ2;
    左侧一对中的两个耦合传输线的输入端通过第三级间匹配电容C_J3连接；The input ends of the two coupled transmission lines in the left pair are connected through the third inter-stage matching capacitor C_J3;
    右侧一对中的两个耦合传输线的输入端通过第四级间匹配电容C_J4连接；The input ends of the two coupled transmission lines in the right pair are connected through the fourth inter-stage matching capacitor C_J4;
    左侧一对耦合传输线中的左耦合传输线的输入端与端口INJ1+连接，左侧一对耦合传输线中的右耦合传输线的输入端与端口INJ1-连接；右侧一对耦合传输线中的左耦合传输线的输入端与端口INJ2+，右侧一对耦合传输线中的右耦合传输线的输入端与端口INJ2-连接。The input end of the left coupled transmission line in the left pair of coupled transmission lines is connected to port INJ1+, the input end of the right coupled transmission line in the left pair of coupled transmission lines is connected to port INJ1-; the left coupled transmission line in the right pair of coupled transmission lines The input end of the right is connected to the port INJ2+, and the input end of the right coupling transmission line of the pair of coupling transmission lines on the right is connected to the port INJ2-.
PCT/CN2020/116263 2019-12-31 2020-09-18 Ultra-wideband microwave and millimeter wave differential power amplifier WO2021135408A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911406199.7A CN110995180A (en) 2019-12-31 2019-12-31 Ultra-wideband microwave millimeter wave differential power amplifier
CN201911406199.7 2019-12-31

Publications (1)

Publication Number Publication Date
WO2021135408A1 true WO2021135408A1 (en) 2021-07-08

Family

ID=70079518

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/116263 WO2021135408A1 (en) 2019-12-31 2020-09-18 Ultra-wideband microwave and millimeter wave differential power amplifier

Country Status (2)

Country Link
CN (1) CN110995180A (en)
WO (1) WO2021135408A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116317978A (en) * 2023-05-22 2023-06-23 广东工业大学 Dual-mode power amplifier, power amplifying method and related equipment thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN210839483U (en) * 2019-12-31 2020-06-23 南京米乐为微电子科技有限公司 Output matching network for differential power amplifier
CN110995180A (en) * 2019-12-31 2020-04-10 南京米乐为微电子科技有限公司 Ultra-wideband microwave millimeter wave differential power amplifier
CN112068635B (en) * 2020-08-13 2021-08-27 成都天锐星通科技有限公司 Multi-channel phased array
CN113556092B (en) * 2021-09-16 2021-12-31 深圳飞骧科技股份有限公司 Radio frequency power amplifier based on transformer matching network

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120126891A1 (en) * 2010-11-23 2012-05-24 Postech Academy-Industry Foundation Power amplification apparatus
CN107404294A (en) * 2017-08-23 2017-11-28 广州慧智微电子有限公司 A kind of output matching network circuit and amplifying circuit with directional coupler
CN107707209A (en) * 2017-09-18 2018-02-16 曾传德 High-gain broadband millimeter wave difference amplifier
CN110995180A (en) * 2019-12-31 2020-04-10 南京米乐为微电子科技有限公司 Ultra-wideband microwave millimeter wave differential power amplifier
CN210839488U (en) * 2019-12-31 2020-06-23 南京米乐为微电子科技有限公司 Ultra-wideband microwave millimeter wave differential power amplifier

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120126891A1 (en) * 2010-11-23 2012-05-24 Postech Academy-Industry Foundation Power amplification apparatus
CN107404294A (en) * 2017-08-23 2017-11-28 广州慧智微电子有限公司 A kind of output matching network circuit and amplifying circuit with directional coupler
CN107707209A (en) * 2017-09-18 2018-02-16 曾传德 High-gain broadband millimeter wave difference amplifier
CN110995180A (en) * 2019-12-31 2020-04-10 南京米乐为微电子科技有限公司 Ultra-wideband microwave millimeter wave differential power amplifier
CN210839488U (en) * 2019-12-31 2020-06-23 南京米乐为微电子科技有限公司 Ultra-wideband microwave millimeter wave differential power amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116317978A (en) * 2023-05-22 2023-06-23 广东工业大学 Dual-mode power amplifier, power amplifying method and related equipment thereof
CN116317978B (en) * 2023-05-22 2023-07-21 广东工业大学 Dual-mode power amplifier, power amplifying method and related equipment thereof

Also Published As

Publication number Publication date
CN110995180A (en) 2020-04-10

Similar Documents

Publication Publication Date Title
WO2021135408A1 (en) Ultra-wideband microwave and millimeter wave differential power amplifier
CN109167575A (en) A kind of power amplifier of wide band high-gain flatness
CN105811895A (en) Optimized high-efficiency K-waveband MMIC power amplifier based on harmonic terminal
WO2023040201A1 (en) Radio-frequency power amplifier based on transformer matching network
CN108306622A (en) A kind of S-band broadband MMIC low-noise amplifiers
WO2024141109A1 (en) Power amplifier circuit
WO2023065843A1 (en) Transformer matching-based three-power synthesis radio frequency power amplifier
CN112910417B (en) Broadband high-efficiency microwave power amplifier
CN111600553A (en) Microwave monolithic integration ultra-wideband power amplifier
CN115940990B (en) Ultra-wideband transceiver multifunctional chip
CN112994627B (en) High-efficiency power amplifier circuit topology structure with high impedance transformation ratio and low matching loss
CN210839488U (en) Ultra-wideband microwave millimeter wave differential power amplifier
CN112019168A (en) Power amplifier based on slow wave microstrip line matching network
CN211046870U (en) High-power two-dimensional traveling wave CMOS power amplifier
WO2023045543A1 (en) Three-stage power amplifier based on transformer matching, and radio frequency front-end architecture
WO2023226581A1 (en) Class-j distributed power amplifier based on harmonic regulation and control, and optimization method for class-j distributed power amplifier
CN110034738A (en) A kind of ultra-wideband low-noise amplifier based on modified impedance matching network
CN112865725A (en) Ultra-wideband high-power high-efficiency monolithic integrated power amplifier circuit structure
CN113922780A (en) Power divider applicable to Doherty PA
CN115412037A (en) Parallel negative feedback ultra-wideband low-noise amplifier based on cross-junction type microstrip matching
CN111628737A (en) Improved ultra-wideband high-efficiency power amplifier
CN112994619B (en) High-efficiency power amplifier circuit topology structure with harmonic matching structure
WO2021135407A1 (en) Output matching network for differential power amplifier
CN111884615B (en) High-order broadband input impedance matching network and application thereof
CN110233599A (en) E-Band microwave F power-like amplifier based on CMOS

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20911126

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20911126

Country of ref document: EP

Kind code of ref document: A1