CN110990229A - System information acquisition method and device - Google Patents

System information acquisition method and device Download PDF

Info

Publication number
CN110990229A
CN110990229A CN201911305477.XA CN201911305477A CN110990229A CN 110990229 A CN110990229 A CN 110990229A CN 201911305477 A CN201911305477 A CN 201911305477A CN 110990229 A CN110990229 A CN 110990229A
Authority
CN
China
Prior art keywords
variable
nmi
system information
processing function
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201911305477.XA
Other languages
Chinese (zh)
Other versions
CN110990229B (en
Inventor
范鸿雷
李沛盈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Topsec Technology Co Ltd
Beijing Topsec Network Security Technology Co Ltd
Beijing Topsec Software Co Ltd
Original Assignee
Beijing Topsec Technology Co Ltd
Beijing Topsec Network Security Technology Co Ltd
Beijing Topsec Software Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Topsec Technology Co Ltd, Beijing Topsec Network Security Technology Co Ltd, Beijing Topsec Software Co Ltd filed Critical Beijing Topsec Technology Co Ltd
Priority to CN201911305477.XA priority Critical patent/CN110990229B/en
Publication of CN110990229A publication Critical patent/CN110990229A/en
Application granted granted Critical
Publication of CN110990229B publication Critical patent/CN110990229B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The application provides a system information acquisition method and device. The method comprises the following steps: starting timing by a non-maskable interrupt NMI timer; when the non-maskable interrupt NMI is triggered according to a preset period, counting system information in one period through an NMI interrupt processing function and a system soft interrupt processing function; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate. According to the embodiment of the application, the NMI terminal processing function and the system soft interrupt processing function are used for periodically collecting the system information, the two functions cannot be influenced by faults of the operating system, and therefore the system information can be accurately obtained.

Description

System information acquisition method and device
Technical Field
The application relates to the technical field of computers, in particular to a system information acquisition method and device.
Background
At present, network attacks are increasing, a large number of network security devices are developed and applied to practical environments, the requirements for information visualization of the network security devices are increasing due to the rich and diverse applications and the popularization of networks, but the real-time performance and accuracy of data acquisition are often difficult to guarantee due to the complex information acquisition of the network devices and the possible software logic errors of the system.
In the prior art, system information is periodically read by using a system process or a thread, but when a process scheduling error, a memory error or a thread deadlock and other systematic errors occur in an operating system, the system cannot record the system information.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method and an apparatus for acquiring system information, so as to solve the problem in the prior art that a system cannot record system information when a systematic error such as a process scheduling error, a memory error, or a thread deadlock occurs in an operating system.
In a first aspect, an embodiment of the present application provides a system information acquisition method, including: starting timing by a non-maskable interrupt NMI timer; when the non-maskable interrupt NMI is triggered according to a preset period, counting system information in one period through an NMI interrupt processing function and a system soft interrupt processing function; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate.
According to the embodiment of the application, the NMI terminal processing function and the system soft interrupt processing function are used for periodically collecting the system information, the two functions cannot be influenced by faults of the operating system, and therefore the system information can be accurately obtained.
Further, before reading the system information through the NMI interrupt handling function and the system soft interrupt handling function, the method further comprises: when the security gateway is started, initializing a packet receiving start variable, a packet receiving end variable, a CPU statistical variable and a memory statistical variable, and registering an NMI interrupt processing function and a system soft interrupt processing function.
According to the embodiment of the application, the relevant variables are initialized and the functions are registered, so that the preparation work is performed for the subsequent acquisition of the system information, and the accurate system information can be obtained.
Further, the counting system information in a cycle through the NMI interrupt handling function and the system soft interrupt handling function includes: assigning the read hardware network card data to a packet receiving end variable through an NMI interrupt processing function, assigning the CPU utilization rate to a CPU statistical variable, and assigning the memory utilization rate to a memory statistical variable; acquiring a packet receiving start variable through a system soft interrupt processing function, and acquiring network card receiving and transmitting packet data according to the packet receiving start variable and the packet receiving end variable; and obtaining the CPU utilization rate according to the CPU statistical variable, and obtaining the memory utilization rate according to the memory statistical variable.
According to the embodiment of the application, the relevant information of the system is firstly acquired from the CPU through the NMI interrupt processing function, and then the final system information is obtained through the system soft interrupt processing function, so that the CPU is prevented from bringing large calculation pressure.
Further, the obtaining network card transceiving packet data according to the packet receiving start variable and the packet receiving end variable includes: and taking the difference value of the packet receiving starting variable and the packet receiving ending variable as the data of the network card receiving and sending packets. And obtaining the network card transceiving packet data in one period through difference calculation.
Further, after counting the system information in one cycle through the NMI interrupt handling function and the system soft interrupt handling function, the method further includes: and assigning the packet receiving end variable to the packet receiving start variable, and initializing the packet receiving end variable, the CPU statistical variable and the memory statistical variable.
According to the embodiment of the application, the packet receiving start variable, the packet receiving end face changing, the CPU statistical variable and the memory statistical variable are initialized so as to receive the system information in the next period.
In a second aspect, an embodiment of the present application provides a system information collecting device, including:
the timing module is used for starting timing through the non-maskable interrupt NMI timer; the information counting module is used for counting the system information in one period through an NMI interrupt processing function and a system soft interrupt processing function after the non-maskable interrupt NMI is triggered according to a preset period; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate.
Further, the apparatus further comprises:
and the initialization module is used for initializing a packet receiving start variable, a packet receiving end variable, a CPU statistical variable and a memory statistical variable when the security gateway is started, and registering the NMI interrupt processing function and the system soft interrupt processing function.
In a third aspect, an embodiment of the present application provides a CPU, including the system information acquisition device of the second aspect.
In a fourth aspect, an embodiment of the present application provides an electronic device, including: a processor, a memory, and a bus, wherein,
the processor and the memory are communicated with each other through the bus;
the memory stores program instructions executable by the processor, the processor being capable of performing the method of the first aspect when invoked by the program instructions.
In a fifth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium, including:
the non-transitory computer readable storage medium stores computer instructions that cause the computer to perform the method of the first aspect.
Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic flow chart of a system information acquisition method according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart of a system information acquisition method according to an embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of an apparatus according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Non Maskable Interrupts (NMI) are one type of Interrupt request. The external non-maskable interrupt request informs the CPU of a catastrophic event, such as a power down, a bus parity bit error, etc., via a special CPU pin NMI. The internal non-maskable interrupt request is generated spontaneously in the CPU, such as memory read-write error, overflow interrupt, division error interrupt and the like. Interrupt requests on the NMI line are not masked (neither disabled) and are immediately latched by the CPU. NMI is therefore edge triggered and does not require level triggering. NMI is also higher priority than INTR. The type of non-maskable interrupt is designated as 2, and the interrupt type code does not have to be provided by the interrupt source when the CPU responds to NMI, and therefore the NMI response also does not require execution of the bus cycle INTA.
Therefore, in order to solve the problem that the system cannot record the system information when a systematic error such as a process scheduling error, a memory error or a thread deadlock occurs in the operating system, an embodiment of the present application also provides a system information acquisition method. Because the unmasked interrupt is not influenced by system logic errors, the information can be accurately and periodically acquired, difference values are made, and the system information can be accurately acquired.
Fig. 1 is a schematic flow chart of a system information acquisition method provided in an embodiment of the present application, as shown in fig. 1, including:
step 101: starting timing by a non-maskable interrupt NMI timer;
step 102: when the non-maskable interrupt NMI is triggered according to a preset period, counting system information in one period through an NMI interrupt processing function and a system soft interrupt processing function; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate.
The main body for executing the method is an acquisition device, and the acquisition device can be a Central Processing Unit (CPU) or a functional module running on the CPU. The preset period may be a default value, or may be set by itself according to an actual situation, for example: and may be 2 seconds, 4 seconds, etc. Because the NMI interrupt processing function can only process short tasks, the system information is collected through the system soft interrupt function and the NMI interrupt processing function. It should be noted that, the NMI interrupt processing function and the system interrupt processing function are both custom functions, and can realize the collection of system information.
In addition, whether the period triggered by the NMI comes or not can be judged through the NMI timer, when the system starts or the statistics of the previous round of system information is completed, the NMI timer starts to time, and when the preset period is reached, the NMI is triggered to be interrupted.
It can be understood that the network card transceiving packet data indicates the number of transceiving packets of the network card from the end of the last NMI interrupt to the time limit that the current NMI interrupt is triggered, that is, in the preset period. CPU usage represents the CPU occupancy at the time the NMI interrupt is triggered, and may be expressed as a percentage. The memory usage rate indicates the situation that the memory is occupied when the NMI interrupt is triggered, and can also be expressed by a percentage. And, the system information may also include other parameters, such as: the number of threads, the number of processes, and the like, and therefore, specific parameters in the system information may be set according to actual situations, which is not specifically limited in this embodiment of the present application.
According to the embodiment of the application, the NMI terminal processing function and the system soft interrupt processing function are used for periodically collecting the system information, the two functions cannot be influenced by faults of the operating system, and therefore the system information can be accurately obtained.
On the basis of the above embodiment, before reading the system information by the NMI interrupt handling function and the system soft interrupt handling function, the method further includes:
when the security gateway is started, initializing a packet receiving start variable, a packet receiving end variable, a CPU statistical variable and a memory statistical variable, and registering an NMI interrupt processing function and a system soft interrupt processing function.
In a specific implementation process, the packet receiving start variable may be denoted by packercv _ begin, the packet receiving end variable may be denoted by packercv _ end, the CPU statistical variable may be denoted by CPU _ stat, and the memory statistical variable may be denoted by mem _ stat. When the security gateway is started, values of the four variables are initialized to 0, and in the running process of the system and after one NMI interruption triggering, data stored in the packercv _ begin is the receiving and sending packet data of the hardware network card when the security gateway is started to start to calculate until the last NMI interruption is triggered; starting the security gateway by using data stored in the packercv _ end as the data for starting calculation until the NMI interruption is triggered, wherein the data is the data of the hardware network card for receiving and transmitting the packet data; the data stored in the CPU _ stat is the utilization rate of the CPU when the current interrupt is triggered, and the data stored in the mem _ stat is the utilization rate of the memory when the current interrupt is triggered.
The NMI interrupt processing function and the system soft interrupt processing function need to be registered before being called, and can be called in subsequent operation after the registration is successful. And the NMI interrupt processing function is used for acquiring data of the hardware network card, the CPU utilization rate and the memory utilization rate, assigning the data of the hardware network card to a packercv _ end variable, assigning the CPU utilization rate to a CPU _ stat variable and assigning the memory utilization rate to a mem _ stat variable. The system soft-interrupt processing function is used for calculating according to the variables to obtain system information, namely, the system soft-interrupt processing function obtains the network card receiving and sending packet data according to the packet receiving start variable and the packet receiving end variable; and obtaining the CPU utilization rate according to the CPU statistical variable, and obtaining the memory utilization rate according to the memory statistical variable.
It should be noted that, in obtaining the network card transceiving packet data according to the packet receiving start variable and the packet receiving end variable, specifically, the packet receiving end variable is subtracted from the packet receiving start variable, and the obtained difference is the network card transceiving packet data.
The advantage of this is that the NMI interrupt processing function does not occupy the CPU for a long time, and after the data is acquired, the system soft interrupt processing function performs statistics to acquire the final data. Thus, the operating pressure of the CPU can be reduced.
On the basis of the above embodiment, after counting the system information in one cycle by the NMI interrupt handling function and the system soft interrupt handling function, the method further includes:
and assigning the packet receiving end variable to the packet receiving start variable, and initializing the packet receiving end variable, the CPU statistical variable and the memory statistical variable.
In a specific implementation process, after system information acquisition of an NMI interrupt is completed once, a packet receiving end variable needs to be assigned to a packet receiving start variable, values of the packet receiving end variable, a CPU statistical variable and a memory statistical variable are initialized to 0, and a next NMI terminal cycle is waited for.
The following describes a system information collecting method provided by the embodiment of the present application more clearly and completely.
Fig. 2 is a schematic flow chart of a system information acquisition method provided in an embodiment of the present application, and as shown in fig. 2, the method includes:
step 201: initializing variables and registering functions; when the security gateway is started, initializing a packet receiving start variable packercv _ begin, a packet receiving end variable packercv _ end, a CPU statistical variable CPU _ stat and a memory statistical variable mem _ stat, setting the four variables to be 0, and registering an NMI interrupt processing function do _ NMI and a system soft interrupt processing function NMI _ stat;
step 202: an NMI interrupt is triggered; when NMI interruption is triggered, because NMI is non-maskable interruption provided by a CPU, is triggered periodically and is not influenced by system errors, even if an operating system has software logic errors, an NMI interruption processing function do _ NMI is called;
step 203: assigning a value to the variable; reading data of the hardware network card through the called do _ nmi, assigning the data to a variable packercv _ end, assigning the CPU utilization rate to a CPU _ stat, and assigning the memory utilization rate to a mem _ stat;
step 204: counting variables; after the variable assignment is completed, triggering a system soft interrupt processing function nmi _ stat, taking a difference value between a packercv _ begin variable and a packercv _ end variable as network card transceiving packet data, recording the data in statistics of system network card transceiving packets, taking a value corresponding to the CPU _ stat variable as a CPU utilization rate, recording the value in CPU utilization rate statistics, taking a value corresponding to the mem _ stat variable as a memory utilization rate, recording the memory utilization rate statistics, and assigning the packercv _ end to the packercv _ begin variable;
step 205: initializing variables; three variables, namely packercv _ end, cpu _ stat and mem _ stat, are set to 0, and step 202 is executed after the next NMI interrupt is triggered.
According to the embodiment of the application, the NMI terminal processing function and the system soft interrupt processing function are used for periodically collecting the system information, the two functions cannot be influenced by faults of the operating system, and therefore the system information can be accurately obtained.
Fig. 3 is a schematic structural diagram of an apparatus provided in an embodiment of the present application, where the apparatus may be a module, a program segment, or code on an electronic device. It should be understood that the apparatus corresponds to the above-mentioned embodiment of the method of fig. 1, and can perform various steps related to the embodiment of the method of fig. 1, and the specific functions of the apparatus can be referred to the description above, and the detailed description is appropriately omitted here to avoid redundancy. The device includes: a timing module 301 and an information statistic module 302; wherein:
the timing module 301 is configured to start timing by using a non-maskable interrupt NMI timer;
the information counting module 302 is configured to count system information in a period through an NMI interrupt processing function and a system soft interrupt processing function after the non-maskable interrupt NMI is triggered according to a preset period; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate.
On the basis of the above embodiment, the apparatus further includes:
and the initialization module is used for initializing a packet receiving start variable, a packet receiving end variable, a CPU statistical variable and a memory statistical variable when the security gateway is started, and registering the NMI interrupt processing function and the system soft interrupt processing function.
On the basis of the foregoing embodiment, the information statistics module 302 is specifically configured to:
assigning the read hardware network card data to a packet receiving end variable through an NMI interrupt processing function, assigning the CPU utilization rate to a CPU statistical variable, and assigning the memory utilization rate to a memory statistical variable;
acquiring a packet receiving start variable through a system soft interrupt processing function, and acquiring network card receiving and transmitting packet data according to the packet receiving start variable and the packet receiving end variable; and obtaining the CPU utilization rate according to the CPU statistical variable, and obtaining the memory utilization rate according to the memory statistical variable.
On the basis of the foregoing embodiment, the information statistics module 302 is specifically configured to:
and taking the difference value of the packet receiving starting variable and the packet receiving ending variable as the data of the network card receiving and sending packets.
On the basis of the above embodiment, the apparatus further includes a variable initialization module, configured to:
and assigning the packet receiving end variable to the packet receiving start variable, and initializing the packet receiving end variable, the CPU statistical variable and the memory statistical variable.
To sum up, the embodiment of the application periodically acquires the system information by using the NMI terminal processing function and the system soft interrupt processing function, and the two functions are not affected by the fault of the operating system, so that the system information can be accurately acquired.
Fig. 4 is a schematic structural diagram of an entity of an electronic device provided in an embodiment of the present application, and as shown in fig. 4, the electronic device includes: a processor (processor)401, a memory (memory)402, and a bus 403; wherein the content of the first and second substances,
the processor 401 and the memory 402 complete communication with each other through the bus 403;
the processor 401 is configured to call the program instructions in the memory 402 to execute the methods provided by the above-mentioned method embodiments, for example, including: starting timing by a non-maskable interrupt NMI timer; when the NMI is triggered according to a preset period, counting system information in one period through an NMI interrupt processing function and a system soft interrupt processing function; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate.
The processor 401 may be an integrated circuit chip having signal processing capabilities. The processor 401 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. Which may implement or perform the various methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The Memory 402 may include, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read Only Memory (PROM), Erasable Read Only Memory (EPROM), electrically Erasable Read Only Memory (EEPROM), and the like.
The present embodiment discloses a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, enable the computer to perform the method provided by the above-mentioned method embodiments, for example, comprising: starting timing by a non-maskable interrupt NMI timer; when the NMI is triggered according to a preset period, counting system information in one period through an NMI interrupt processing function and a system soft interrupt processing function; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate.
The present embodiments provide a non-transitory computer-readable storage medium storing computer instructions that cause the computer to perform the methods provided by the above method embodiments, for example, including: starting timing by a non-maskable interrupt NMI timer; when the NMI is triggered according to a preset period, counting system information in one period through an NMI interrupt processing function and a system soft interrupt processing function; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate.
In addition, the embodiment of the application also provides a CPU, and the CPU comprises the system information acquisition device provided by each embodiment.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A system information acquisition method is characterized by comprising the following steps:
starting timing by a non-maskable interrupt NMI timer;
when the NMI is triggered according to a preset period, counting system information in one period through an NMI interrupt processing function and a system soft interrupt processing function; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate.
2. The method of claim 1, wherein prior to reading system information via an NMI interrupt handling function and a system soft interrupt handling function, the method further comprises:
when the security gateway is started, initializing a packet receiving start variable, a packet receiving end variable, a CPU statistical variable and a memory statistical variable, and registering an NMI interrupt processing function and a system soft interrupt processing function.
3. The method according to claim 1 or 2, wherein the counting the system information in one cycle by the NMI interrupt handling function and the system soft interrupt handling function comprises:
assigning the read hardware network card data to a packet receiving end variable through an NMI interrupt processing function, assigning the CPU utilization rate to a CPU statistical variable, and assigning the memory utilization rate to a memory statistical variable;
acquiring a packet receiving start variable through a system soft interrupt processing function, and acquiring network card receiving and transmitting packet data according to the packet receiving start variable and the packet receiving end variable; and obtaining the CPU utilization rate according to the CPU statistical variable, and obtaining the memory utilization rate according to the memory statistical variable.
4. The method according to claim 3, wherein the obtaining of the network card transceiving packet data according to the packet receiving start variable and the packet receiving end variable comprises:
and taking the difference value of the packet receiving starting variable and the packet receiving ending variable as the data of the network card receiving and sending packets.
5. The method of claim 3, wherein after counting system information for one cycle by the NMI interrupt handling function and the system soft interrupt handling function, the method further comprises:
and assigning the packet receiving end variable to the packet receiving start variable, and initializing the packet receiving end variable, the CPU statistical variable and the memory statistical variable.
6. A system information acquisition device, comprising:
the timing module is used for starting timing through the non-maskable interrupt NMI timer;
the information counting module is used for counting the system information in one period through an NMI interrupt processing function and a system soft interrupt processing function after the non-maskable interrupt NMI is triggered according to a preset period; the system information comprises network card receiving and sending packet data, CPU utilization rate and memory utilization rate.
7. The apparatus of claim 6, further comprising:
and the initialization module is used for initializing a packet receiving start variable, a packet receiving end variable, a CPU statistical variable and a memory statistical variable when the security gateway is started, and registering the NMI interrupt processing function and the system soft interrupt processing function.
8. A CPU, comprising: the system information acquisition apparatus of claim 6.
9. An electronic device, comprising: a processor, a memory, and a bus, wherein,
the processor and the memory are communicated with each other through the bus;
the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of any one of claims 1-5.
10. A non-transitory computer-readable storage medium storing computer instructions which, when executed by a computer, cause the computer to perform the method of any one of claims 1-5.
CN201911305477.XA 2019-12-17 2019-12-17 System information acquisition method and device Active CN110990229B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911305477.XA CN110990229B (en) 2019-12-17 2019-12-17 System information acquisition method and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911305477.XA CN110990229B (en) 2019-12-17 2019-12-17 System information acquisition method and device

Publications (2)

Publication Number Publication Date
CN110990229A true CN110990229A (en) 2020-04-10
CN110990229B CN110990229B (en) 2023-07-18

Family

ID=70094879

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911305477.XA Active CN110990229B (en) 2019-12-17 2019-12-17 System information acquisition method and device

Country Status (1)

Country Link
CN (1) CN110990229B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112383414A (en) * 2020-10-28 2021-02-19 北京中科网威信息技术有限公司 Method and device for fast switching of dual-computer hot backup
CN114518991A (en) * 2020-11-18 2022-05-20 中移物联网有限公司 Method and device for counting CPU utilization rate

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1632760A (en) * 2003-12-24 2005-06-29 华为技术有限公司 Method for preserving abnormal state information of control system
CN101895440A (en) * 2010-07-22 2010-11-24 北京天融信科技有限公司 Security gateway and failure detection method thereof
CN104899125A (en) * 2015-06-04 2015-09-09 杭州华三通信技术有限公司 Operation information acquisition method and operation information acquisition device for single-board system
US20180225143A1 (en) * 2015-10-16 2018-08-09 Huawei Technologies Co., Ltd. Method and apparatus for executing non-maskable interrupt
CN109144873A (en) * 2018-08-22 2019-01-04 郑州云海信息技术有限公司 A kind of linux kernel processing method and processing device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1632760A (en) * 2003-12-24 2005-06-29 华为技术有限公司 Method for preserving abnormal state information of control system
CN101895440A (en) * 2010-07-22 2010-11-24 北京天融信科技有限公司 Security gateway and failure detection method thereof
CN104899125A (en) * 2015-06-04 2015-09-09 杭州华三通信技术有限公司 Operation information acquisition method and operation information acquisition device for single-board system
US20180225143A1 (en) * 2015-10-16 2018-08-09 Huawei Technologies Co., Ltd. Method and apparatus for executing non-maskable interrupt
CN109144873A (en) * 2018-08-22 2019-01-04 郑州云海信息技术有限公司 A kind of linux kernel processing method and processing device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112383414A (en) * 2020-10-28 2021-02-19 北京中科网威信息技术有限公司 Method and device for fast switching of dual-computer hot backup
CN112383414B (en) * 2020-10-28 2023-09-29 北京中科网威信息技术有限公司 Dual-machine hot backup quick switching method and device
CN114518991A (en) * 2020-11-18 2022-05-20 中移物联网有限公司 Method and device for counting CPU utilization rate

Also Published As

Publication number Publication date
CN110990229B (en) 2023-07-18

Similar Documents

Publication Publication Date Title
EP3352083B1 (en) Debugging method, multi-core processor, and debugging equipment
EP3343377A1 (en) Debugging method, multi-core processor, and debugging equipment
CN110990229B (en) System information acquisition method and device
CN109189509B (en) Interface calling method, interface calling response method and server
CN109144873B (en) Linux kernel processing method and device
CN113407414A (en) Program operation monitoring method, device, terminal and storage medium
CN111880916A (en) Multi-drawing task processing method, device, terminal, medium and host in GPU
CN115102653A (en) Time synchronization method and device, computer equipment and storage medium
WO2020098266A1 (en) Abnormal response method and device
CN113177045A (en) Data extraction method and device, computable storage equipment and data request equipment
US9563494B2 (en) Systems and methods for managing task watchdog status register entries
CN114637656B (en) Redis-based monitoring method and device, storage medium and equipment
CN108418730B (en) Network flow testing method, device, equipment and computer readable storage medium
US10846162B2 (en) Secure forking of error telemetry data to independent processing units
CN111786856A (en) Browser environment checking method and device
CN112130982A (en) Interrupt control device, method and system
CN111175573A (en) Method, device, equipment and medium for detecting alternating voltage frequency
CN112463125B (en) Timing method and equipment of virtual timer
CN117992126B (en) Processor cooperative work method and system based on software lockstep
CN108304167A (en) A kind of raising interface calls stability approach and device
WO2022237570A1 (en) Deadlock detection method, apparatus, and related device
CN109408035B (en) Flow configuration method, storage medium and server of business system
CN109981397B (en) Network performance acquisition method and system
CN109471663B (en) Method and device for executing single chip microcomputer program
CN117234764A (en) Electronic system, exception handling method and device thereof and electronic equipment

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant