CN110943049B - 光学感测器 - Google Patents

光学感测器 Download PDF

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Publication number
CN110943049B
CN110943049B CN201811114904.1A CN201811114904A CN110943049B CN 110943049 B CN110943049 B CN 110943049B CN 201811114904 A CN201811114904 A CN 201811114904A CN 110943049 B CN110943049 B CN 110943049B
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chip
sensing
redistribution
substrate
insulator
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CN110943049A (zh
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洪立群
李建成
杜修文
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Tong Hsing Electronic Industries Ltd
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Kingpak Technology Inc
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Priority to US16/294,436 priority patent/US10700111B2/en
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Solid State Image Pick-Up Elements (AREA)

Abstract

本发明公开一种光学感测器，包含基板、设置于基板的重布式芯片结构、设置于重布式芯片结构的感测芯片、位于感测芯片上方的透光片、电性连接基板与感测芯片的多条金属线、及设置于基板上的封装体。重布式芯片结构包含绝缘体、埋置于绝缘体的第一电子芯片、及连接于绝缘体与第一电子芯片底部的重置线路。重置线路电性连接于第一电子芯片、并通过覆晶固定于基板。感测芯片的感测区朝向重布式芯片结构正投影所形成的投影区域位于重布式芯片结构的外轮廓内。重布式芯片结构、感测芯片、部分的透光片、及金属线埋置于封装体内。据此，重布式芯片结构能够有效地支撑感测芯片，以在感测芯片进行打线的过程中，有效地抵抗施加于感测芯片的外力。

Description

光学感测器
技术领域
本发明涉及一种感测器，尤其涉及一种光学感测器。
背景技术
现有的光学感测器包含有大尺寸芯片堆栈于小尺寸芯片上方的态样，并且现有光学感测器的大尺寸芯片周缘通过打线而电性连接于基板。然而，现有光学感测器在上述打线的过程中，由于大尺寸芯片周缘是呈悬空状，所以打线过程所施予大尺寸芯片周缘的外力易导致缺陷产生。
于是，本发明人认为上述缺陷可改善，乃特潜心研究并配合科学原理的运用，终于提出一种设计合理且有效改善上述缺陷的本发明。
发明内容
本发明实施例在于提供一种光学感测器，其能有效地改善现有光学感测器所可能产生的缺陷。
本发明实施例公开一种光学感测器，包括：一基板；一重布式芯片结构，包含有一绝缘体、埋置于所述绝缘体的一第一电子芯片、及连接于所述绝缘体与所述第一电子芯片底部的一重置线路；其中，所述重置线路电性连接于所述第一电子芯片，并且所述重布式芯片结构通过所述重置线路覆晶固定于所述基板；一感测芯片，具有大于所述第一电子芯片的尺寸，并且所述感测芯片设置于所述重布式芯片结构上；其中，所述感测芯片的一顶面包含有一感测区，并且所述感测区朝向所述重布式芯片结构正投影所形成的一投影区域位于所述重布式芯片结构的外轮廓之内；一透光片，位于所述感测芯片的上方；多条金属线，电性连接所述基板与所述感测芯片；一封装体，设置于所述基板上，并且所述重布式芯片结构、所述感测芯片、及多个所述金属线埋置于所述封装体内；其中，所述封装体固定所述透光片于所述感测芯片上方、并裸露所述透光片的部分表面。
优选地，所述重布式芯片结构包含有一第二电子芯片，并且所述第一电子芯片与所述第二电子芯片间隔地埋置于所述绝缘体内，所述第一电子芯片与所述第二电子芯片各自电性连接于所述重置线路。
优选地，所述绝缘体包含有突伸出所述感测芯片的一延伸部，所述光学感测器进一步包括有设置于所述延伸部上的一第三电子芯片，并且所述第三电子芯片通过打线而电性连接于所述基板。
优选地，所述绝缘体的至少局部侧边缘相对于所述感测芯片的邻近侧边缘突伸出一距离，并且所述距离小于1毫米。
优选地，所述绝缘体的至少局部侧边缘相对于所述感测芯片的邻近侧边缘内缩有一距离，并且所述距离小于1毫米。
优选地，所述重布式芯片结构包含有多个焊球，所述重置线路通过多个所述焊球而焊接于所述基板；所述封装体包含有一底部填充剂，并且所述底部填充剂布满于所述重布式芯片结构与所述基板之间的一间隙。
优选地，所述封装体包含有：一支撑体，至少部分夹持于所述感测芯片的所述顶面以及所述透光片之间；一包覆体，设置于所述基板上；其中，所述重布式芯片结构、所述感测芯片、及所述支撑体埋置于所述包覆体内，并且所述包覆体裸露所述透光片的所述部分表面。
优选地，每条所述金属线的一部分埋置于所述支撑体内，而每条所述金属线的另一部分埋置于所述包覆体内。
优选地，所述感测芯片的所述顶面包含有位于所述感测区外侧且未接触多个所述金属线的一非打线区，所述绝缘体包含有突伸出所述感测芯片的所述非打线区的一承载部，所述封装体进一步包含有设置于所述承载部上且邻近于所述非打线区的一延伸体；其中，所述支撑体的一部分夹持于所述感测芯片的所述顶面以及所述透光片之间，而所述支撑体的另一部分夹持于所述透光片以及所述延伸体之间，并且所述支撑体埋置于所述包覆体内。
优选地，所述重布式芯片结构包含有多个焊球，所述重置线路通过多个所述焊球而焊接于所述基板，并且所述包覆体布满于所述重布式芯片结构与所述基板之间的一间隙。
综上所述，本发明实施例所公开的光学感测器，其将所述第一电子芯片埋置于所述重布式芯片结构的绝缘体中，并使所述重布式芯片结构与所述感测芯片之间存在特定的配置关系(如：所述感测区朝向所述重布式芯片结构正投影所形成的投影区域位于所述重布式芯片结构的外轮廓之内)，所以所述重布式芯片结构能够有效地支撑感测芯片，据以在感测芯片进行打线的过程中，有效地抵抗施加于感测芯片的外力，并避免产生缺陷。
为能更进一步了解本发明的特征及技术内容，请参阅以下有关本发明的详细说明与附图，但是此等说明与附图仅用来说明本发明，而非对本发明的保护范围作任何的限制。
附图说明
图1为本发明实施例一的光学感测器的剖视示意图。
图2为图1的部位II的局部放大示意图。
图3为本发明实施例一的光学感测器另一态样的剖视示意图。
图4为本发明实施例二的光学感测器的剖视示意图。
具体实施方式
请参阅图1至图4，其为本发明的实施例，需先说明的是，本实施例对应附图所提及的相关数量与外型，仅用来具体地说明本发明的实施方式，以便于了解本发明的内容，而非用来局限本发明的保护范围。
[实施例一]
请参阅图1至图3所示，其为本发明的实施例一。如图1和图2所示，本实施例公开一种光学感测器100，包含有一基板1、设置于所述基板1的一重布式芯片结构2、设置于所述重布式芯片结构2的一感测芯片3、位于所述感测芯片3上方的一透光片4、电性连接所述基板1与所述感测芯片3的多条金属线5、及设置于所述基板1上的一封装体6。
需先阐明的是，为便于说明本实施例光学感测器100，图式是以剖视图呈现，但可以理解的是，在图式所未呈现的光学感测器100部位也会形成有相对应的构造。例如：图1仅呈现两条金属线5，但在图1所未呈现的光学感测器100部位还包含其他金属线5。以下将分别就本实施例光学感测器100的各个组件构造与连接关系作以说明。
所述基板1于本实施例中呈方形或矩形，并且所述基板1于其顶面的大致中央处设有一芯片固定区11，而于所述芯片固定区11的外侧部位设置有多个第一接垫12。再者，所述基板1于底面可进一步设有多个焊接球(未标示)，通过基板1的多个所述焊接球而焊接固定于一电子构件(图未示，如：印刷电路板)上，据以使所述光学感测器100能电性连接所述电子构件。
所述重布式芯片结构2包含有一绝缘体21、埋置于所述绝缘体21的一第一电子芯片22、连接于所述绝缘体21与所述第一电子芯片22底部的一重置线路23(redistributionlayer，RDL)、及多个焊球24。其中，所述第一电子芯片22于本实施例中是以一影像信号处理器(image signal processor)来说明，但不以此为限。
进一步地说，所述绝缘体21于本实施例中是通过模制成形而包围在所述第一电子芯片22的周围，并且所述绝缘体21的顶面与底面分别切齐于所述第一电子芯片22的顶面与底面。所述重置线路23则是成形于所述绝缘体21的底面与所述第一电子芯片22的底面，并且所述重置线路23电性连接于所述第一电子芯片22。其中，位于所述第一电子芯片22底部的多个接点221可以通过所述重置线路23而连接到位于所述重布式芯片结构2底部且具有较大间距的多个新接点231。也就是说，所述重置线路23相当于一种线路扇出结构(circuitfan-out structure)。另，位于所述绝缘体21下方的所述重置线路23部位较佳是设置有至少部分的多个所述新接点231，但本发明不受限于此。
再者，所述重布式芯片结构2通过所述重置线路23覆晶固定于所述基板1(的芯片固定区11)。于本实施例中，所述重置线路23通过多个所述焊球24而焊接于所述基板1的芯片固定区11(上述焊接于本实施例中包含有结构上与电性上的连接)。
所述感测芯片3于本实施例中是以一影像感测芯片来说明，但不以此为限。其中，所述感测芯片3包含有位于相反两侧的一顶面31及一底面32，并且所述感测芯片3于其顶面31的大致中央处设有一感测区311，而于所述感测区311的外侧部位设置有多个第二接垫312，并且多个所述第二接垫312的位置与数量对应于多个所述第一接垫12的位置与数量。
再者，所述感测芯片3具有大于所述第一电子芯片22的尺寸，并且所述感测芯片3设置于所述重布式芯片结构2上；例如：所述感测芯片3的底面32以黏着层(未标示)固定于所述绝缘体21的顶面与所述第一电子芯片22的顶面。换个角度来看，所述感测芯片3的所述感测区311朝向所述重布式芯片结构2正投影所形成的一投影区域，其位于所述重布式芯片结构2的外轮廓(如：图1中的所述绝缘体21的侧边缘211)之内，并且所述投影区域于本实施例中较佳是覆盖所述第一电子芯片22，但本发明不受限于此。
更详细地说，所述绝缘体21的至少局部侧边缘211相对于所述感测芯片3的邻近侧边缘33(如：图1中的所述绝缘体21左侧边缘211相对于所述感测芯片3的左侧边缘33)突伸出一距离Da，并且所述距离Da小于1毫米，但本发明不受限于此。举例来说，在本发明未绘示的其他实施例中，所述绝缘体21的各个侧边缘211可以是相对于所述感测芯片3的对应侧边缘33皆突伸出所述距离Da。
再者，所述绝缘体21的至少局部侧边缘211相对于所述感测芯片3的邻近侧边缘33(如：图1中的所述绝缘体21右侧边缘211相对于所述感测芯片3的右侧边缘33)内缩有一距离Db，并且所述距离Db小于1毫米，但本发明不受限于此。举例来说，在本发明未绘示的其他实施例中，所述绝缘体21的各个侧边缘211可以是相对于所述感测芯片3的对应侧边缘33皆内缩有所述距离Db。
多个所述金属线5的一端分别连接所述基板1的多个所述第一接垫12，而多个所述金属线5的另一端分别连接于所述感测芯片3的多个所述第二接垫312，据以使所述基板1与所述感测芯片3能通过多个所述金属线5而达成电性连接。
依上所述，由于所述第一电子芯片22于本实施例中是被埋置于所述重布式芯片结构2的绝缘体21中，并且所述重布式芯片结构2与所述感测芯片3之间存在特定的配置关系(如：所述感测区311朝向所述重布式芯片结构2正投影所形成的投影区域位于所述重布式芯片结构2的外轮廓之内)，所以所述重布式芯片结构2能够有效地支撑感测芯片3，据以在感测芯片3进行打线的过程中，有效地抵抗施加于感测芯片3的外力，避免造成缺陷。
进一步地说，所述绝缘体21的侧边缘211与所述感测芯片3的邻近侧边缘33之间形成有小于等于1毫米的距离Da、Db，以避免所述感测芯片3与基板1之间形成过于狭长的缝隙，进而使所述感测芯片3与基板1之间不易产生气泡。
再者，所述重布式芯片结构2于本实施例中以覆晶方式固定于所述基板1的芯片固定区11，也就是说，所述重布式芯片结构2是位于多个所述第一接垫12的内侧。据此，本实施例的所述重布式芯片结构2因为非使用打线方式，因而能够有效地降低成本、并避免所述重布式芯片结构2与位于其上方的所述感测芯片3之间产生短路的问题。
所述透光片4于本实施例中是以呈透明状的一平板玻璃来说明，但本发明不受限于此。其中，所述透光片4通过封装体6(如：下述封装体6所包含的支撑体61)而设置于所述感测芯片3的顶面31上方，所述透光片4面向所述感测芯片3的感测区311，并且所述透光片4、所述支撑体61、及所述感测芯片3共同包围形成有一密封空间S。
再者，所述透光片4的尺寸于本实施例中是小于所述感测芯片3的尺寸。其中，所述透光片4朝向所述感测芯片3顶面31正投影所形成的投影区域，其覆盖所述感测区311并位于所述感测芯片3的外轮廓之内，但本发明不受限于此。
所述封装体6设置于所述基板1上，并且所述重布式芯片结构2、所述感测芯片3、及多个所述金属线5皆埋置于所述封装体6内；而所述封装体6固定所述透光片4于所述感测芯片3上方、并裸露所述透光片4的部分表面(如：图1中的透光片4顶面)。
更详细地说，所述封装体6主要由一包覆体63及一模制体64(molding compound)构成。但所述封装体6于本实施例中是包含有一支撑体61(如：胶材)、一底部填充剂62(underfill epoxy)、一包覆体63、及一模制体64(molding compound)来说明；也就是说，支撑体61及底部填充剂62也可以视为是所述封装体6的一部分。其中，所述支撑体61夹持于所述感测芯片3的顶面31以及所述透光片4之间，并且所述支撑体61位于所述感测区311的外侧及多个所述第二接垫312的内侧。所述底部填充剂62布满于所述重布式芯片结构2与所述基板1之间的一间隙；也就是说，所述重布式芯片结构2的多个所述焊球24埋置于所述底部填充剂62内。
再者，所述包覆体63设置于所述基板1上，并且所述重布式芯片结构2、所述感测芯片3、及所述支撑体61埋置于所述包覆体63内，并且所述包覆体63裸露所述透光片4的所述部分表面。也就是说；所述包覆体63是包围在所述底部填充剂62、所述重布式芯片结构2、所述感测芯片3、所述支撑体61、及所述透光片4的外侧。再者，每条金属线5在本实施例中完全埋置于所述包覆体63内。
另，本实施例的所述包覆体63是由液态封胶(liquid compound)所固化形成，并且所述模制体64是模制成形于所述包覆体63的顶面，但本发明不受限于此。举例来说，于本发明未绘示的其他实施例中，所述封装体6也可以省略所述模制体64。
此外，在本实施例的图1中，所述封装体6是以包含有支撑体61、包覆体63、及底部填充剂62来说明，但本发明不受限于此。举例来说，如图3所示的光学感测器100另一态样，所述封装体6也可以省略底部填充剂62，并且所述封装体6以其包覆体63布满于所述重布式芯片结构2与所述基板1之间的一间隙。其中，所述包覆体63较佳是通过模制方式而成形，以利于填入所述重布式芯片结构2与所述基板1之间的间隙。
[实施例二]
请参阅图4所示，其为本发明的实施例二，本实施例类似于上述实施例一，所以两个实施例的相同处则不再加以赘述，而本实施例与实施例一的差异主要如下所载：
于本实施例中，所述重布式芯片结构2进一步包含有一第二电子芯片25。其中，所述第一电子芯片22与所述第二电子芯片25间隔地埋置于所述绝缘体21内，并且所述感测芯片3的所述感测区311朝向所述重布式芯片结构2正投影所形成的一投影区域，其较佳是覆盖所述第一电子芯片22与所述第二电子芯片25，但本发明不受限于此。再者，所述重置线路23则是成形于所述绝缘体21的底面、所述第一电子芯片22的底面、及所述第二电子芯片25的底面，并且所述第一电子芯片22与所述第二电子芯片25各自电性连接于所述重置线路23。
进一步地说，所述光学感测器100可以进一步包括有非埋置于所述重布式芯片结构2的一第三电子芯片7，所述基板1与所述绝缘体21则对应所述第三电子芯片7而形成有下述构造。
所述绝缘体21包含有突伸出所述感测芯片3的一延伸部212，并且所述基板1在多个所述第一接垫12的内侧且邻近所述延伸部212的部位设置有一第三接垫13；也就是说，所述第三接垫13大致位于多个所述第一接垫12与所述延伸部212之间，但本发明不受限于此。
再者，所述第三电子芯片7设置于所述延伸部212上，并且所述第三电子芯片7是通过导线5a而电性连接于所述基板1(的第三接垫13)。其中，所述第三电子芯片7邻近于所述感测芯片3，并且所述第三电子芯片7相较于所述绝缘体21的高度较佳是低于所述感测芯片3顶面31相较于所述绝缘体21的高度，避以避免第三电子芯片7的讯号干扰到金属线5的讯号。
另，所述感测芯片3的顶面31可以包含有位于所述感测区311外侧且未接触多个所述金属线5的一非打线区313，而所述绝缘体21与所述封装体6则对应所述非打线区313而形成有下述构造。
所述透光片4的尺寸大于所述感测芯片3的尺寸，并且所述重布式芯片结构2的尺寸大于所述透光片4的尺寸，所述绝缘体21包含有突伸出所述感测芯片3的非打线区313的一承载部213。其中，所述封装体6进一步包含有设置于所述承载部213上且邻近于所述非打线区313的一延伸体65，并且所述延伸体65于本实施例中是相连于邻近所述非打线区313的所述感测芯片3侧边缘33(如：图4中的所述感测芯片3的右侧边缘33)，并且所述延伸体65相对于所述绝缘体21的高度较佳是等于所述非打线区313相对于所述绝缘体21的高度。
更详细地说，所述支撑体61的一部分夹持于所述感测芯片3的顶面31以及所述透光片4之间(如图4中的感测芯片3之左侧位置)，而所述支撑体61的另一部分夹持于所述透光片4以及所述延伸体65之间(如图4中的感测芯片3之右侧位置)，并且所述支撑体61埋置于所述包覆体63内。然而，在本发明未绘示的其他实施例中，所述封装体6也可以省略所述延伸体65；也就是说，图4中的所述感测芯片3左、右侧的构造是对称的，所以所述支撑体61可以是完全夹持于所述感测芯片3的顶面31以及所述透光片4之间。依上所载，本发明的所述支撑体61可以是至少部分夹持于所述感测芯片3的顶面31以及所述透光片4之间。
再者，于本实施例中，每条金属线5的一部分(及其相连接的第二接垫312)埋置于所述支撑体61内，而每条金属线5的另一部分(及其相连接的第一接垫12)埋置于所述包覆体63内，但本发明不以此为限。
此外，在本发明未绘示的其他实施例中，实施例一与实施例二的所述光学感测器100可以依据设计需求而彼此参酌置换内部构造，例如：实施例一的所述光学感测器100也可以设有所述第三电子芯片7，并且所述基板1与所述绝缘体21对应所述第三电子芯片7而形成有如同实施例二记载的构造。
[本发明实施例的技术效果]
综上所述，本发明实施例所公开的光学感测器100，其将所述第一电子芯片22埋置于所述重布式芯片结构2的绝缘体21中，并使所述重布式芯片结构2与所述感测芯片3之间存在特定的配置关系(如：所述感测区311朝向所述重布式芯片结构2正投影所形成的投影区域位于所述重布式芯片结构2的外轮廓之内)，所以所述重布式芯片结构2能够有效地支撑感测芯片3，据以在感测芯片3进行打线的过程中，有效地抵抗施加于感测芯片3的外力。
再者，在所述绝缘体21的侧边缘211与所述感测芯片3的邻近侧边缘33之间形成有小于等于1毫米的距离Da、Db，可以避免所述感测芯片3与基板1之间形成过于狭长的缝隙，进而使所述感测芯片3与基板1之间不易产生气泡。
以上所述仅为本发明的优选可行实施例，并非用来局限本发明的保护范围，凡依本发明专利范围所做的均等变化与修饰，皆应属本发明的权利要求书的保护范围。

Claims (8)

1.一种光学感测器，其特征在于，所述光学感测器包括：
一基板；
一重布式芯片结构，包含有一绝缘体、埋置于所述绝缘体的一第一电子芯片、及连接于所述绝缘体与所述第一电子芯片底部的一重置线路；其中，所述重置线路电性连接于所述第一电子芯片，并且所述重布式芯片结构通过所述重置线路覆晶固定于所述基板；
一感测芯片，具有大于所述第一电子芯片的尺寸，并且所述感测芯片设置于所述重布式芯片结构上；其中，所述感测芯片的一顶面包含有一感测区，并且所述感测区朝向所述重布式芯片结构正投影所形成的一投影区域位于所述重布式芯片结构的外轮廓之内；
一透光片，位于所述感测芯片的上方；
多条金属线，电性连接所述基板与所述感测芯片；以及
一封装体，设置于所述基板上，并且所述重布式芯片结构、所述感测芯片、及多个所述金属线埋置于所述封装体内；其中，所述封装体固定所述透光片于所述感测芯片上方、并裸露所述透光片的部分表面；
其中，所述封装体包含有：
一支撑体，至少部分夹持于所述感测芯片的所述顶面以及所述透光片之间；及
一包覆体，设置于所述基板上；其中，所述重布式芯片结构、所述感测芯片、及所述支撑体埋置于所述包覆体内，并且所述包覆体裸露所述透光片的所述部分表面；
其中，所述感测芯片的所述顶面包含有位于所述感测区外侧且未接触多个所述金属线的一非打线区，所述绝缘体包含有突伸出所述感测芯片的所述非打线区的一承载部，所述封装体进一步包含有设置于所述承载部上且邻近于所述非打线区的一延伸体；其中，所述支撑体的一部分夹持于所述感测芯片的所述顶面以及所述透光片之间，而所述支撑体的另一部分夹持于所述透光片以及所述延伸体之间，并且所述支撑体埋置于所述包覆体内。
2.依据权利要求1所述的光学感测器，其特征在于，所述重布式芯片结构包含有一第二电子芯片，并且所述第一电子芯片与所述第二电子芯片间隔地埋置于所述绝缘体内，所述第一电子芯片与所述第二电子芯片各自电性连接于所述重置线路。
3.依据权利要求2所述的光学感测器，其特征在于，所述绝缘体包含有突伸出所述感测芯片的一延伸部，所述光学感测器进一步包括有设置于所述延伸部上的一第三电子芯片，并且所述第三电子芯片通过打线而电性连接于所述基板。
4.依据权利要求1所述的光学感测器，其特征在于，所述绝缘体的至少局部侧边缘相对于所述感测芯片的邻近侧边缘突伸出一距离，并且所述距离小于1毫米。
5.依据权利要求1所述的光学感测器，其特征在于，所述绝缘体的至少局部侧边缘相对于所述感测芯片的邻近侧边缘内缩有一距离，并且所述距离小于1毫米。
6.依据权利要求1所述的光学感测器，其特征在于，所述重布式芯片结构包含有多个焊球，所述重置线路通过多个所述焊球而焊接于所述基板；所述封装体包含有一底部填充剂，并且所述底部填充剂布满于所述重布式芯片结构与所述基板之间的一间隙。
7.依据权利要求1所述的光学感测器，其特征在于，每条所述金属线的一部分埋置于所述支撑体内，而每条所述金属线的另一部分埋置于所述包覆体内。
8.依据权利要求1所述的光学感测器，其特征在于，所述重布式芯片结构包含有多个焊球，所述重置线路通过多个所述焊球而焊接于所述基板，并且所述包覆体布满于所述重布式芯片结构与所述基板之间的一间隙。
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