CN110914963A - Semiconductor manufacturing method and wafer inspection method - Google Patents
Semiconductor manufacturing method and wafer inspection method Download PDFInfo
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- CN110914963A CN110914963A CN201880047424.XA CN201880047424A CN110914963A CN 110914963 A CN110914963 A CN 110914963A CN 201880047424 A CN201880047424 A CN 201880047424A CN 110914963 A CN110914963 A CN 110914963A
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
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Abstract
The present invention provides a semiconductor manufacturing method capable of coping with the densification of an integrated circuit. A semiconductor manufacturing method according to an aspect of the present invention includes: the wafer having a plurality of chip forming regions is formed corresponding to each chip forming region: a memory cell; a photodiode that outputs an electrical signal corresponding to an input optical signal; and a signal processing circuit which generates a logic signal based on the electric signal output from the photodiode and outputs the logic signal to the memory cell; after the forming step, inputting pumping light for confirming the operation of the memory cell to the photodiode, and checking the operation state of the memory cell; and after the step of inspecting, dicing the chip-forming regions one by one.
Description
Technical Field
One embodiment of the present invention relates to a semiconductor manufacturing method and a wafer inspection method.
Background
In a semiconductor manufacturing process, after a circuit is formed on a semiconductor wafer, an operation state of the circuit is checked to determine whether or not a chip (more precisely, a region to be a chip after dicing) is good. The operating state of the circuit is checked by, for example, probing. In probing, a pin is brought into contact with a terminal of a circuit on a semiconductor wafer, and an electric signal is input from the pin to the terminal to check an operation state of the circuit (see, for example, patent document 1).
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open No. 2006-261218
Disclosure of Invention
Problems to be solved by the invention
In recent years, with the increase in the capacity and density of integrated circuits and the increase in the density of wiring rules, the number of circuits per 1 chip of a semiconductor wafer has increased, and accordingly, the number of terminals per 1 chip has increased. When such a semiconductor wafer is subjected to the above probing, the number of pins increases, and the pressing force (pressing force against the semiconductor wafer) when the pins contact the terminals of the circuit increases. This may cause damage to the semiconductor wafer.
An aspect of the present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor manufacturing method and a wafer inspection method that can cope with an increase in density of integrated circuits.
Means for solving the problems
A semiconductor manufacturing method according to an aspect of the present invention includes: the semiconductor wafer having a plurality of chip forming regions is formed corresponding to each of the chip forming regions: an internal circuit; a light receiving element that outputs an electrical signal corresponding to an input optical signal; and a signal processing circuit that generates a logic signal based on the electric signal output from the light receiving element and outputs the logic signal to the internal circuit; after the forming step, inputting a 1 st optical signal for confirming the operation of the internal circuit to the light receiving element, and checking the operation state of the internal circuit; and after the step of inspecting, dicing the chip-forming regions one by one.
In a semiconductor manufacturing method according to an aspect of the present invention, the following are formed in correspondence with a chip formation region: a light receiving element that outputs an electrical signal corresponding to the optical signal; and a signal processing circuit that generates a logic signal based on the electrical signal. Then, the operation state of the internal circuit is checked by inputting the 1 st optical signal to the light receiving element, and then the chip is cut for each chip formation region. In this way, since a signal for confirming the operation of the internal circuit is input as an optical signal, it is not necessary to bring a pin for signal input into contact with a terminal of the circuit. Therefore, in the method of bringing the pins for signal input into contact with the terminals of the circuit, the increase in pressing force against the semiconductor wafer, which is a problem when the operating state of the integrated circuit is confirmed to have a high density, does not become a problem. Therefore, since a logic signal is generated by the signal processing circuit based on the electric signal output from the light receiving element and the logic signal is input to the internal circuit, even in a system in which a signal for operation confirmation is input as an optical signal, the operation confirmation of the internal circuit is appropriately performed in the same manner as in a conventional system in which a pin is brought into contact with a terminal. In addition, in the method of bringing the pins for signal input into contact with the terminals of the circuit, when the operation of the integrated circuit is checked with a high density, the pins need to be brought into contact with the densely arranged terminals with high precision, and therefore, the pin tip needs to be miniaturized. This may not sufficiently cope with the increase in density of the integrated circuit. In the semiconductor manufacturing method according to one aspect of the present invention, since the signal for operation confirmation is input as an optical signal, the shape of the pin tip does not become a problem when the operation confirmation of the integrated circuit with higher density is performed. Thus, according to an embodiment of the present invention, a semiconductor manufacturing method which can cope with high density of an integrated circuit is provided. In the method of physically contacting the pin for signal input with the terminal of the circuit, there is an upper limit (for example, 100 MHz) to the frequency band of the signal that can be supplied from the pin, and there is a case where the upper limit cannot cope with a high-speed input signal. In the semiconductor manufacturing method according to the aspect of the present invention, since the signal for confirming the operation is supplied not by physical contact of the pin but by input of the optical signal, the signal having the frequency band exceeding the upper limit can be supplied as the signal for confirming the operation.
In the semiconductor manufacturing method, the light receiving element and the signal processing circuit may be formed outside the chip formation region in correspondence with the chip formation region in the forming step. In this way, the light receiving element and the signal processing circuit, which are components for operation confirmation, are separated from the chip by dicing after operation confirmation (inspection of the operation state). Thus, the chip has a minimum structure, and the chip area is not limited by the formation of the inspection device such as the light receiving element.
In the above semiconductor manufacturing method, the light receiving element and the signal processing circuit may be formed in the chip formation region in correspondence with the chip formation region in the forming step. This can shorten the wiring for electrically connecting the light receiving element and the like to the input/output terminal formed on the chip. With such a configuration, a chip having a preferable configuration (for example, a configuration in which a plurality of chips are stacked via a through electrode or the like) in which wires such as wire bonding are shortened as much as possible can be provided.
In the semiconductor manufacturing method, in the step of forming, an output terminal for outputting an output signal from the internal circuit may be formed in correspondence with the chip forming region, and in the step of inspecting, the 2 nd optical signal may be input to the region corresponding to the output terminal, so that a signal corresponding to the output signal output from the output terminal in response to an input of the logic signal to the internal circuit is detected, and an operation state of the internal circuit may be inspected. By inputting the optical signal to the area corresponding to the output terminal and detecting the signal corresponding to the output signal in this way, the signal relating to the inspection of the operating state of the internal circuit is detected without bringing the pin into contact with the output terminal. This also suppresses an increase in the pressing force against the semiconductor wafer, which is a problem in the method of bringing the pin into contact with the terminal. Namely, a semiconductor manufacturing method more suitable for increasing the density of an integrated circuit is provided.
In the above semiconductor manufacturing method, in the forming step, a switch portion that is electrically connected to the output terminal and outputs a signal corresponding to the output signal during the input of the optical signal may be further formed in correspondence with the chip forming region; in the inspection step, a2 nd optical signal, which is pulse light synchronized with the 1 st optical signal, is repeatedly input to the switch unit while changing a delay time of an input timing of the 1 st optical signal to the light receiving element, and a signal corresponding to the output signal output from the switch unit is detected. In this way, the 2 nd optical signal as probe light is repeatedly input to the switch unit with a delay in the timing of input to the light receiving element with respect to the 1 st optical signal as pump light, and the delay time is changed during the repeated input, whereby the output signal output from the output terminal can be sampled, and the operating state of the internal circuit can be appropriately checked from the result of the sampling. In the case of such an inspection, the output signal output from the switching unit is sampled by measuring the signal output from the switching unit a plurality of times, instead of directly measuring the output signal output from the output terminal. Since the signal (signal corresponding to the output signal) output from the switch unit is a signal having a narrow frequency band, for example, when the frequency band of the output signal output from the output terminal is wide even when the logic signal is a high-speed signal, detection is easy using a probe pin or the like. That is, by performing the inspection in the above-described manner, even when a high-speed signal is input, the operating state of the internal circuit is appropriately detected by using a simple configuration in which only a signal having a narrow frequency band can be detected, such as a probe pin.
In the semiconductor manufacturing method, in the inspection step, a nonlinear optical crystal may be disposed on the output terminal, the 2 nd optical signal may be input to the nonlinear optical crystal, and the reflected light from the nonlinear optical crystal may be detected as a signal corresponding to the output signal. The refractive index of the nonlinear optical crystal changes in accordance with the voltage of the output terminal (i.e., the voltage of the output signal output from the output terminal). Therefore, the reflected light from the nonlinear optical crystal changes in polarization state according to the voltage of the output signal output from the output terminal. By detecting such a change in polarization state as a change in light intensity via a polarization beam splitter or the like, for example, the operating state of the internal circuit can be checked in accordance with the intensity of reflected light. By performing the inspection in the above-described manner, the operating state of the internal circuit is appropriately inspected by a simple configuration relating to the detection of reflected light without bringing the probe pin or the like into contact with the semiconductor wafer.
In the semiconductor manufacturing method, in the inspection step, the 2 nd optical signal may be input to a surface of the semiconductor wafer opposite to the surface on which the light receiving element is formed, and the operation state of the internal circuit may be inspected by detecting reflected light from the opposite surface. By inputting a logic signal to the internal circuit, the thickness of the depletion layer of the chip is varied. Such thickness deformation of the depletion layer can be detected by, for example, a change in intensity of reflected light when an optical signal is input from the back surface (the surface opposite to the surface on which the light receiving element is formed). Thus, the operation state of the internal circuit is appropriately checked by detecting the reflected light from the back surface without using a pin or the like. Further, since the light source of the 1 st optical signal is provided on the side where the light receiving element is formed and the light source of the 2 nd optical signal is provided on the opposite side, an installation space for each light source is appropriately secured with a margin.
A wafer inspection method according to an aspect of the present invention includes: preparing a semiconductor wafer having formed thereon: an internal circuit; a light receiving element that outputs an electrical signal corresponding to an input optical signal; and a signal processing circuit that generates a logic signal based on the electric signal output from the light receiving element and outputs the logic signal to the internal circuit; and after the preparation step, inputting a 1 st optical signal for checking the operation of the internal circuit to the light receiving element, and checking the operation state of the internal circuit.
In the wafer inspection method, the semiconductor wafer further having the output terminal for outputting the output signal from the internal circuit is prepared in the preparation step, and the 2 nd optical signal is input to the region corresponding to the output terminal in the inspection step, and the signal corresponding to the output signal output from the output terminal in response to the input of the logic signal to the internal circuit is detected, thereby inspecting the operating state of the internal circuit.
In the wafer inspection method, the preparation step may further include forming a switch unit electrically connected to the output terminal and outputting a signal corresponding to the output signal during the input of the optical signal; in the inspection step, a2 nd optical signal, which is pulse light synchronized with the 1 st optical signal, is repeatedly input to the switch unit while changing a delay time of an input timing of the 1 st optical signal to the light receiving element, and a signal corresponding to the output signal output from the switch unit is detected.
In the wafer inspection method, the nonlinear optical crystal may be disposed on the output terminal in the inspection step, the 2 nd optical signal may be input to the nonlinear optical crystal, and the reflected light from the nonlinear optical crystal may be detected as a signal corresponding to the output signal.
In the wafer inspection method, in the inspection step, the 2 nd optical signal may be input to a surface of the semiconductor wafer opposite to the surface on which the light receiving element is formed, and the operation state of the internal circuit may be inspected by detecting reflected light from the opposite surface.
ADVANTAGEOUS EFFECTS OF INVENTION
According to one aspect of the present invention, a semiconductor manufacturing method and a wafer inspection method that can cope with high density of integrated circuits are provided.
Drawings
Fig. 1 is a schematic perspective view showing a wafer inspection apparatus according to embodiment 1.
Fig. 2 is a schematic plan view of the wafer viewed from the device formation region side.
Fig. 3 is a schematic plan view of 1 chip formation region and scribe lines around the chip formation region as viewed from the device formation region side.
Fig. 4 is a schematic cross-sectional view of a wafer relating to a photodiode formation region.
Fig. 5 is a block diagram showing the electrical connections of the devices.
Fig. 6 is a flowchart of the semiconductor manufacturing method of embodiment 1.
Fig. 7 is a schematic plan view of a silicon substrate before device formation.
Fig. 8 is a flowchart of an inspection process of the semiconductor manufacturing method.
Fig. 9 is a schematic plan view of 1 chip formation region and scribe lines around the chip formation region as viewed from the device formation region side.
Fig. 10 is a schematic perspective view showing the wafer inspection apparatus according to embodiment 2.
Fig. 11 is a diagram for explaining reflection of probe light by the nonlinear optical crystal disposed on the output terminal.
Fig. 12 is a flowchart of a semiconductor manufacturing method according to embodiment 2.
Fig. 13 is a schematic diagram of the wafer inspection apparatus according to embodiment 3.
Fig. 14 is a diagram illustrating a change in reflectance according to expansion and contraction of a depletion layer.
Fig. 15 is a flowchart of a semiconductor manufacturing method according to embodiment 3.
Fig. 16 is a block diagram showing the electrical connection of each device of the modification.
Fig. 17 is a schematic plan view of 1 chip formation region of a wafer according to a modification example, as viewed from the device formation region side.
Detailed Description
< embodiment 1 >
Hereinafter, embodiment 1 of the present invention will be described in detail with reference to the drawings. In the description, the same elements or elements having the same functions will be denoted by the same reference numerals, and redundant description thereof will be omitted.
Fig. 1 is a schematic perspective view showing a wafer inspection apparatus 1 according to embodiment 1. The wafer inspection apparatus 1 shown in fig. 1 is an apparatus for inspecting an operation state of an internal circuit formed in a chip forming region 51 of a wafer 50 (semiconductor wafer). First, a wafer 50 to be inspected by the wafer inspection apparatus 1 will be described with reference to fig. 2 to 5.
[ wafer ]
Fig. 2 is a schematic plan view of the wafer 50 as viewed from the device formation region side. The device formation region is a region of the main surface of the silicon substrate 59 (see fig. 4) included in the wafer 50, and is a region where various devices such as the below-described inspection device 70 (see fig. 3) are formed. In fig. 2, the inspection device 70 is not shown. As shown in fig. 2, the wafer is substantially circular in plan view and has a plurality of chip formation regions 51 substantially rectangular in plan view. The chip formation region 51 is a region that becomes a chip after dicing. After the operation state of the memory cell 57, which is an internal circuit of the chip forming region 51, is inspected by the wafer inspection apparatus 1, the wafer is diced for each chip forming region 51 along the dicing streets 60, and a plurality of chips are generated from the wafer 50.
Fig. 3 is a schematic plan view of 1 chip formation region 51 included in the wafer 50 and scribe lines 60 around the chip formation region 51, as viewed from the device formation region side. As shown in fig. 3, the wafer 50 includes a memory block 52, an input terminal 53, an output terminal 54, a power supply terminal 55, and a ground terminal 56 as a structure formed in the chip formation region 51. The wafer 50 includes an inspection device 70 as a structure formed on the scribe line 60. Since each structure of the inspection device 70 is disposed on the dicing street 60, it is separated from each structure on the chip formation region 51 by dicing and is not included in the structure of the diced chip. The width of the scribe line 60 (i.e., the width of the margin of dicing) is set to, for example, about 25 μm.
The memory block 52 has a plurality of memory cells 57 (internal circuits) and is disposed in a substantially central portion of the chip formation region 51. The Memory cell 57 is a Memory circuit such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), a flash EEPRO (electrically erasable Programmable Read-Only Memory), or the like. The memory cell 57 includes a MOS transistor, a capacitor element for storing information, and the like. The input terminals 53 are provided in plural numbers corresponding to the number of the memory cells 57, for example. The memory block 52 may have other circuit elements (semiconductor elements), word lines, bit lines, sense amplifiers, fuses, and the like, in addition to the plurality of memory cells 57.
The input terminal 53 is an input terminal for inputting an input signal to the memory cell 57 or the like, which is an internal circuit. The output terminal 54 is an output terminal for outputting an output signal from the memory cell 57 or the like, which is an internal circuit. The input terminal 53 and the output terminal 54 are made of conductive metal such as aluminum, for example. The input terminal 53 and the output terminal 54 are provided in correspondence with each other. In fig. 3, for convenience of explanation, the input terminal 53 and the output terminal 54 are displayed by 3, respectively, but in practice, the number of the terminals may be about 10 to 1000. Note that, in fig. 3, for convenience of explanation, the rows of the input terminals 53 and the rows of the output terminals 54 are shown as being distinguished, but the rows of the input terminals 53 and the rows of the output terminals 54 may not be distinguished, and the input terminals 53 and the output terminals 54 may be arranged at random. In addition, the same terminal may have both functions of the input terminal 53 and the output terminal 54.
The inspection device 70 is a device for inspecting the operating state of the memory cell 57 and the like, which are internal circuits. The inspection device 70 includes a photodiode 71 (light receiving element), a signal processing circuit 72, a PCA (Photo Conductive antenna) 73 (switching section), and pads 74, 75, 76, and 77.
The photodiode 71 receives pump light (first optical signal) for confirming the operation of the memory cell 57 or the like as an internal circuit, converts the brightness of the pump light into an electric signal, and outputs the electric signal to the signal processing circuit 72. The pump light is output from the light source 11 of the wafer inspection apparatus 1 shown in fig. 1 (details will be described later). A plurality of photodiodes 71 are provided so as to correspond one-to-one to each of the plurality of input terminals 53. In this way, in the present embodiment, the signal for operation confirmation is supplied to the internal circuit via the photodiode 71 by an optical signal (pump light). Therefore, the signal for confirming the operation can be supplied to the internal circuit without bringing the pins into contact with each other. The upper limit of the frequency band of the photodiode 71 is, for example, 10GHz or more. In the present embodiment, the photodiode 71 is described as corresponding to the input terminal 53 on a one-to-one basis, but the present invention is not limited thereto, and the photodiode and the input terminal may not be corresponding on a one-to-one basis.
The signal processing circuit 72 generates a logic signal based on the electric signal output from the photodiode 71, and outputs the logic signal to an internal circuit such as the memory cell 57. The signal processing circuit 72 includes, for example, an amplifier 72a and a frequency discriminator 72 b. The amplifier 72a is an operational amplifier that amplifies the electric signal output from the photodiode 71 at a predetermined amplification factor. The frequency discriminator 72b converts the electric signal into a logic signal represented by High (High) or Low (Low) in accordance with whether the electric signal amplified by the amplifier 72a exceeds a predetermined threshold value. The amplifier 72a and the frequency discriminator 72b set the amplification factor and the threshold value so that the light quantity received by the photodiode 71 becomes high when the light quantity is equal to or more than a certain value.
The electrical connection between the photodiode 71 and the amplifier 72a will be described with reference to fig. 4. Fig. 4 is a schematic cross-sectional view of the wafer 50 relating to the formation region of the photodiode 71. In fig. 4, only a part of the structure of the wafer 50, such as the photodiode 71 and the amplifier 72a, is shown, and the other structure is omitted. As shown in fig. 4, the photodiode 71 and the amplifier 72a are formed on the main surface of the silicon substrate 59. In the wafer 50, an oxide film 58 as an insulating layer is formed on a main surface of a silicon substrate 59 made of a silicon crystal. The photodiode 71 constitutes a so-called PIN photodiode.
The photodiode 71 includes an n-type impurity layer 81, a p-type impurity layer 82, a connection p-type impurity layer 83, and an electrode 84. The n-type impurity layer 81 is a semiconductor layer containing a high concentration of n-type impurities formed in a shallow region of the main surface of the silicon substrate 59. The shallow region is, for example, a region having a depth of about 0.1 μm. The n-type impurity is, for example, antimony, arsenic, phosphorus, or the like. The high concentration is, for example, a concentration of impurities of 1X 1017cm-3Right and left. The n-type impurity layer 81 functions as a part of the photosensitive region that receives the incidence of the pump light. The p-type impurity layer 82 is a semiconductor layer containing a high concentration of p-type impurities formed in a deep region of the main surface of the silicon substrate 59. The deep region is, for example, a region having a depth of about 3 μm in the central regionA domain. The region where the n-type impurity layer 81 is formed and the region where the p-type impurity layer 82 is formed may be formed to be spaced apart from each other by about 2 μm. The p-type impurity is, for example, boron. The connection p-type impurity layer 83 is a semiconductor layer formed between the p-type impurity layer 82 and the electrode 84 in order to electrically connect the p-type impurity layer 82 and the electrode 84. The electrode 84 is an electrode for inputting a predetermined voltage (for example, 2V) of the photodiode 71. The electrode 84 is made of a conductive metal such as aluminum. The n-type impurity layer 81 of the photodiode 71 is electrically connected to a gate electrode 85 of an FET (Field effect transistor) constituting the amplifier 72a, and an electric signal output from the photodiode 71 is input to the gate electrode 85 of the FET.
The details of the transmission path of the electric signal from the photodiode 71 to the memory cell 57 will be described with reference to fig. 5. Fig. 5 is a block diagram showing electrical connections of the respective devices related to the transmission paths of the electrical signals. As shown in fig. 5, the electric signal output from the photodiode 71 by the pump light is amplified at a predetermined amplification factor by an amplifier 72a, then input to a frequency discriminator 72b, and output as a logic signal from the frequency discriminator 72b, and input to the input terminal 53. The logic signal output from the input terminal 53 is input to the memory cell 57 via an ESD (Electro-Static Discharge) prevention circuit 91 and a signal buffer circuit 92. The ESD protection circuit 91 is a circuit for preventing a surge voltage due to electrostatic discharge. The ESD protection circuit 91 has a function of discharging the surge voltage entering from the input terminal 53 to the ground. The signal buffer circuit 92 is a circuit that directly outputs an input logic signal (digital signal) in its original state, and is provided for speeding up signal transmission (improvement of driving capability of an exposed signal).
Returning to fig. 3, the PCA73 is electrically connected to the output terminal 54, receives probe light (2 nd optical signal), and outputs a measurement signal, which is a signal corresponding to an output signal output from the output terminal 54 (an output signal output from the output terminal 54 corresponding to an input of a logic signal to the memory cell 57 or the like), only during a period in which the probe light is received. The probe light is output from the light source 11 of the wafer inspection apparatus 1 shown in fig. 1 (details will be described later). PCA73 is a photoconductive switch often used for megahertz (terahertz) generation and detection. Alternatively, a photodiode for high-speed signals may be used instead of the PCA 73. The PCA73 is provided in plural numbers so as to correspond one-to-one to each of the plural output terminals 54. The PCA73 is electrically connected to one-to-one corresponding pad 76. The measurement signal output from PCA73 is input to pad 76.
The pads 74, 75, 76, 77 are terminals for contacting the pins. The pad 74 is a terminal that contacts the pin 31 that supplies power to the signal processing circuit 72. The pad 75 is a terminal that comes into contact with the pin 32 that supplies power to the wafer 50 to be inspected. The pads 76 are terminals that are in contact with the pins 33 for outputting a signal from the PCA73, and are provided in the same number as the PCA73 in a one-to-one correspondence with the PCA 73. In addition, as shown in fig. 9, one pad 76 may be provided for all PCAs 73 instead of one for each PCA 73. In this case, the detection read results are grouped into one, and output from 1 pin 33 to the lock amplifier 18. This reduces the number of pins 33, thereby reducing the load applied to the wafer 50 from the pins 33. The pad 77 is a terminal to be brought into contact with the ground connection pin 34.
[ wafer inspection apparatus ]
Next, the wafer inspection apparatus 1 according to embodiment 1 will be described with reference to fig. 1. The wafer inspection apparatus 1 irradiates the photodiode 71 of the wafer 50 with pump light and irradiates the PCA73 with probe light, thereby inspecting the operating state of the internal circuits such as the memory cells 57 in the chip formation region 51 by a so-called pump probe method. The pump probe method is a measurement method for verifying a phenomenon in a time region of ultra high speed (femtosecond to picosecond), and excites the wafer 50 with pump light and observes an operation state of the wafer 50 with probe light. In the pump probe method, probe light synchronized with pump light is generated, the incidence timing of the probe light is delayed with respect to the incidence timing of the pump light, and the delay time is changed, whereby the start to the end of the optical reaction can be observed. The wafer inspection apparatus 1 includes a light source 11, a beam splitter 12, a light delay device 13, optical scanners 14 and 15, condenser lenses 16 and 17, a lock-in amplifier 18, and a control/analysis device 19.
The light source 11 is operated by a power source (not shown) and outputs pulsed light to be irradiated to the wafer 50. The light source 11 is, for example, a femtosecond pulse laser light source. As the femtosecond pulse laser light source, for example, the following transmitters (e.g., titanium sapphire laser transmitter, etc.) can be used: an optical pulse having a wavelength of about 800nm, a pulse width of about 100fs and an output of about 100mW is generated at a repetition frequency of 100 MHz. Thus, the light source 11 outputs pulsed light that is continuously output at a predetermined cycle. The light output from the light source 11 is input to the beam splitter 12. The light output from the light source 11 may be input to the light reduction filter and may be reduced before being input to the beam splitter 12.
The beam splitter 12 transmits part of the light output from the light source 11 directly and reflects the rest in a direction substantially orthogonal to the transmission direction. The light transmitted through the beam splitter 12 becomes the pump light and is input to the photointerrupter 20, and the reflected light becomes the probe light and is input to the optical delay device 13. The pump light and the probe light are pulsed lights output from the light source 11 and are synchronized with each other. The photointerrupter 20 periodically chops the pump light by interrupting the pump light at a certain period. The photointerrupter 20 is configured as, for example, a rotating disk in which a portion through which the pump light passes and a portion through which the pump light does not pass are alternately arranged, and rotates by rotational driving of a motor, thereby periodically transmitting the pump light. By providing the photointerrupter 20 and performing the measurement with the lock-in amplifier 18, the SN ratio of the signal can be improved. The pump light transmitted through the photointerrupter 20 is reflected toward the optical scanner 14 by the reflection plate 21.
The optical scanner 14 is constituted by an optical scanning element such as a galvanometer mirror or MEMS (Micro Electro Mechanical Systems). The optical scanner 14 scans the pump light so that the pump light is irradiated to a predetermined irradiation region (specifically, a position where each photodiode 71 is disposed) in response to a control signal from the control/analysis device 19. The optical scanner 14 has a structure for 2-dimensionally scanning the pump light over a predetermined irradiation region, and includes, for example, 2 motors, mirrors attached to the motors, drivers for driving the motors, and an interface for receiving a control signal from the control/analysis device 19. The pump light scanned by the optical scanner 14 is irradiated to the arrangement portion of the photodiode 71 through the condenser lens 16. The optical scanner 14 successively irradiates one or more photodiodes 71 as irradiation targets so that the photodiodes 71 are sequentially irradiated with pump light, for example. The condenser lens 16 is a lens that condenses the pump light to the arrangement portion of the photodiode 71, and is, for example, an objective lens.
The optical delay device 13 changes the delay time of the probe light by changing the timing of incidence of the probe light to the PCA 73. The delay time of the probe light is a delay time of the incident timing of the probe light to the PCA73 with respect to the incident timing of the pump light to the photodiode 71. The optical delay device 13 changes the delay time of the probe light. The optical delay device 13 changes the delay time of the probe light by changing the optical path length of the probe light, for example. The optical delay device 13 is constituted by an optical system including movable mirrors 22 and 23. The movable mirrors 22 and 23 are a pair of mirrors disposed to be inclined at an angle of, for example, 45 degrees with respect to the incident optical axis of the optical delay device 13. The probe light is reflected by the movable mirror 22 in a direction perpendicular to the incident optical axis, enters the movable mirror 23, and is reflected by the movable mirror 23 in a direction parallel to the incident optical axis. The movable mirrors 22 and 23 are provided on a movable base of the optical delay device 13, and are configured to be movable in the incident optical axis direction by the optical delay device 13 by a motor driven in accordance with a control signal from the control/analysis device 19. The movable mirrors 22 and 23 move in the incident optical axis direction, thereby changing the optical path length of the probe light. That is, when the movable mirrors 22 and 23 move away from the beam splitter 12 in the incident optical axis direction, the optical path length of the probe light becomes long, and when they move closer to the beam splitter 12 in the incident optical axis direction, the optical path length of the probe light becomes short. The probe light output from the movable mirror 23 is reflected by the reflection plate 24, and the probe light reflected by the reflection plate 24 is further reflected toward the optical scanner 15 by the reflection plate 25.
The optical scanner 15 is configured by an optical scanning element such as a galvanometer mirror or MEMS (Micro Electro Mechanical Systems). The optical scanner 15 scans the probe light so as to irradiate the predetermined irradiation region (specifically, the arrangement portion of each PCA 73) with the probe light based on a control signal from the control/analysis device 19. The optical scanner 15 has a structure for 2-dimensionally scanning the probe light over a predetermined irradiation area, and includes, for example, 2 motors, mirrors attached to the motors, drivers for driving the motors, and an interface for receiving a control signal from the control/analysis device 19. The probe light scanned by the optical scanner 15 is irradiated to the arrangement portion of the PCA73 through the condenser lens 17. The optical scanner 15 successively sets one or a plurality of PCAs 73 as an irradiation target so that, for example, the respective photodiodes 71 are sequentially irradiated with probe light. The condenser lens 17 is a lens for condensing the probe light to the arrangement portion of the PCA73, and is, for example, an objective lens.
As described above, the PCA73 outputs the measurement signal, which is a signal corresponding to the output signal output from the output terminal 54, to the pad 76 only during the period when the probe light is input. For example, in the case of pulsed light with probe light of 20ps, the output (measurement signal) of the output terminal 54 is input to the pad 76 only for a time width of 20 ps. Thus, the PCA73 is turned ON (ON) only for a short period of time (state in which a measurement signal is output) based ON the pulsed light. Then, by changing the timing of incidence of the probe light on the PCA73 by the optical delay device 13, the output pulse (output signal output from the output terminal 54) is sampled at a high speed and outputted, and as a result, the output signal can be observed with a good SN ratio. The measurement signal (probe signal) thus sampled and outputted is measured in a direct current, and its frequency band is narrow, so that it can be read by the pin 33 in contact with the pad. The measurement signal read by the pin 33 is input to the lock-in amplifier 18.
The lock-in amplifier 18 amplifies only a signal having a repetition frequency that matches the repetition frequency of the pump light periodically chopped by the photointerrupter 20 among the measurement signals for the purpose of increasing the SN ratio of the measurement signals read by the pin 33. The signal (amplified signal) output from the lock-in amplifier 18 is input to the control/analysis device 19.
The control/analysis device 19 is a computer such as a PC. The control/analysis device 19 is connected to an input device such as a keyboard and a mouse for inputting measurement conditions by a user, and a display device such as a monitor for displaying measurement results to the user (both not shown). The control/resolution means 19 comprises a processor. The control/analysis device 19 executes, for example, a function of controlling the light source 11, the optical delay device 13, the optical scanners 14 and 15, and the lock-in amplifier 18, and a function of analyzing a generated waveform (analysis image) or the like based on an amplified signal from the lock-in amplifier 18 by a processor. The user can determine whether or not the chip on which the device is formed is good (defective) based on the analysis image generated by the control/analysis device 19, for example.
[ method for producing semiconductor ]
Next, an example of a semiconductor manufacturing method including an inspection process using the wafer inspection apparatus 1 will be described with reference to a flowchart of fig. 6. First, the silicon substrate 59 is prepared (step S1: preparation process). In the preparation step, as shown in fig. 7, a silicon substrate 59 on which devices such as the memory cell 57 and the inspection device 70 are not formed is prepared. As shown in fig. 7, the prepared silicon substrate 59 is substantially circular in plan view. The silicon substrate 59 has a plurality of chip formation regions 51 having a substantially rectangular shape in plan view. The chip formation region 51 is a region to be a chip by cutting along the dicing street 60 after the device formation.
Next, each device is formed in the device formation region of the silicon substrate 59 (step S2: forming process). In the forming step, as shown in fig. 3, the following are formed corresponding to each chip forming region 51 of the wafer 50 having the plurality of chip forming regions 51: a memory block 52 comprising a plurality of memory cells 57; a plurality of photodiodes 71 for receiving the pumping light for confirming the operation of the memory cell 57 and outputting an electric signal; and a signal processing circuit 72 for generating a logic signal based on the electric signal and outputting the logic signal to the memory cell 57. More specifically, in the forming step, the memory block 52, the input terminal 53, the output terminal 54, the power supply terminal 55, and the ground terminal 56 are formed in the chip forming region 51, and the photodiode 71, the amplifier 72a as the signal processing circuit 72, and the frequency discriminator 72b, the PCA73, and the pads 74, 75, 76, and 77 are formed in the scribe line 60 corresponding to the chip forming region 51 (around the chip forming region 51). That is, in the forming step, the photodiode 71 and the signal processing circuit 72 are formed outside the chip forming region 51.
Then, the pumping light is inputted to the photodiode 71 to check the operation state of the memory cell 57 (step S3: checking process). In the inspection step, probe light is input to the region corresponding to the output terminal 54, and a signal (measurement signal) corresponding to the output signal output from the output terminal 54 is detected in response to the input of the logic signal to the memory cell 57, thereby inspecting the operating state of the memory cell 57. More specifically, in the inspection step, while changing the delay time of the probe light synchronized with the pump light with respect to the timing of inputting the pump light to the photodiode 71, the probe light synchronized with the pump light is repeatedly input to the PCA73, and the operation state of the memory cell 57 is inspected by detecting the measurement signal output from the PCA 73. In this way, in the inspection step, probe light synchronized with pump light, which is pulsed light continuously output at a predetermined cycle, is delayed by a predetermined delay time from the timing of input of the pump light to the photodiode 71, and is input to the PCA73, the delay time is changed, and the measurement signal output from the PCA73 in response to the input of each pulse of the probe light is detected.
The details of the inspection process will be described in more detail with reference to the flowchart of fig. 8 and fig. 1. In the inspection step, as shown in fig. 8, first, the wafer 50 is set on the inspection stage 110 (see fig. 1) of the wafer inspection apparatus 1 (step S31). The wafer 50 placed on the inspection stage 110 is the wafer 50 on which the devices have been formed in the step S2. The wafer 50 in fig. 1 has a rectangular shape in a plan view, but may actually have a circular shape in a plan view as shown in fig. 2.
Next, one chip formation region 51 is selected from the plurality of chip formation regions 51 of the wafer 50 placed on the inspection stage 110 (step S32). Specifically, when receiving an instruction input from the user to start the inspection, for example, the control/analysis device 19 specifies the chip forming region 51 at a predetermined position as the chip forming region 51 to be inspected first. When the chip formation region 51 to be inspected is specified, as shown in fig. 3, the pin 31 is brought into contact with the pad 74 of the chip formation region 51, the pin 32 is brought into contact with the pad 75, the pin 33 is brought into contact with each pad 76, and the pin 34 is brought into contact with the pad 77. As shown in fig. 1, the pins 31 are electrically connected to a power supply portion 101 for the signal processing circuit 72, the pins 32 are electrically connected to a power supply portion 102 for the wafer 50, the plurality of pins 33 are electrically connected to the lock-in amplifiers 18, and the pins 34 are electrically connected to a ground 104. The method of supplying power to the wafer 50 is not limited to the above, and for example, the power may be supplied in a non-contact manner by forming a photodiode and a power supply voltage forming circuit on the wafer and irradiating the photodiode with light, or may be supplied in a space-transfer manner by using an electromagnetic field.
Next, one photodiode 71 is selected from the plurality of photodiodes 71 corresponding to the selected chip formation region 51 (step S33). Specifically, the control/analysis device 19 specifies the photodiode 71 at a predetermined position as the photodiode 71 on which the pump light is first incident.
Next, the selected photodiode 71 is irradiated with pump light (step S34). Specifically, the control/analysis device 19 controls the optical scanner 14 so as to irradiate the photodiode 71 of the selected chip formation region 51 with the pump light, and controls the light source 11 so as to output the femtosecond pulse laser beam from the light source 11.
Next, the detection light is irradiated to the PCA73 corresponding to the selected photodiode 71 (step S35). The PCA73 corresponding to the photodiode 71 is electrically connected to the PCA73 of the photodiode 71. Specifically, the control/analysis device 19 controls the optical scanner 15 so as to irradiate the PCA73 corresponding to the selected photodiode 71 with the probe light. The control/analysis device 19 controls the optical delay device 13 so as to repeatedly input probe light to the PCA73 while changing the delay time with respect to the pump light. The measurement signal thus sampled is input to the lock-in amplifier 18 via the pin 33. Then, an amplified signal obtained by amplifying the measurement signal is input from the lock-in amplifier 18 to the control/analysis device 19, and the amplified signal is analyzed by the control/analysis device 19. Specifically, the control/analysis device 19 generates an analysis image based on the amplification signal. For example, after the inspection of all the chip formation regions 51 of the wafer 50 is completed, the user can check whether or not the operation state of the region of the inspected memory cell 57 (the region of the memory cell 57 related to the selected chip formation region 51) is in a normal state based on the analysis image. Whether or not the operating state of each chip forming region 51 is normal (good product) may be determined by the control/analysis device 19 without being determined by the user. In this case, for example, by previously preparing an analysis result (image pattern) in the case of a good product, the control/analysis device 19 determines whether or not the good product is a good product. The control/analysis device 19 stores the position information of the chip forming region 51 determined as a good product by the user or by the control/analysis device 19.
Next, it is determined whether or not the photodiode 71 before being irradiated with the pump light exists in the selected chip forming region 51 (step S36). Since the number of photodiodes 71 corresponding to each chip formation region 51 can be grasped in advance, the control/analysis device 19 determines whether or not there is a photodiode 71 before irradiation of the pump light, for example, based on whether or not irradiation of the pump light corresponding to the number of photodiodes 71 corresponding to one chip formation region 51 is performed.
If it is determined in step S36 that there is a photodiode 71 before irradiation of the pump light corresponding to the selected chip formation region 51 (S36: no), one photodiode 71 before irradiation of the pump light is selected (step S37). Specifically, the control/analysis device 19 specifies the photodiode 71 into which the pump light is then incident according to a predetermined selection sequence. Thereafter, the processing of steps S34 to S36 described above is performed again.
On the other hand, if it is determined in step S36 that there is no photodiode 71 before irradiation of the pump light corresponding to the selected chip formation region 51 (S36: yes), it is determined whether or not there is a chip formation region 51 before inspection in the wafer 50 (step S38). Since the number of chip forming regions 51 of the wafer 50 can be grasped in advance, the control/analysis device 19 selects the chip forming regions 51 based on whether or not the number of chip forming regions 51 of the wafer 50 is equal to the number of chip forming regions 51, and determines whether or not the chip forming regions 51 before inspection exist.
If it is determined in step S38 that there is a chip formation region 51 before inspection in the wafer 50 (no in S38), one chip formation region 51 before inspection is selected (step S39). Specifically, the control/analysis device 19 specifies the chip formation region 51 to be inspected next according to a predetermined selection procedure. When the chip forming region 51 is specified, the pin 31 is brought into contact with the pad 74 of the chip forming region 51, the pin 32 is brought into contact with the pad 75, the pin 33 is brought into contact with each pad 76, and the pin 34 is brought into contact with the pad 77. Thereafter, the processing of steps S33 to S38 described above is performed again. On the other hand, when it is determined in step S38 that there is no chip formation region 51 before inspection of the wafer 50 (S38: yes), the inspection process of step S3 for the wafer 50 is ended.
Returning to fig. 6, the wafer 50 is then diced (cut) along the streets 60 (step S4: dicing process). In the dicing step, the wafer 50 is diced for each wafer forming region 51 (see fig. 2). In the present embodiment, the structures (the photodiode 71, the signal processing circuit 72, the PCA73, and the pads 74, 75, 76, and 77) of the inspection device 70, which is a device for inspecting the operating state of the memory cell 57, are formed in the scribe line 60. Therefore, the chips produced by dicing for each chip forming region 51 do not include the respective structures of the inspection device 70. The cutting is performed by a cutting device such as a cutter or a dicing saw. The cutting device cuts along the cutting path 60 with an extremely thin blade attached to the tip of a spindle rotating at high speed, for example.
Finally, the plurality of chips produced by dicing the wafer 50 are assembled (step S5: assembly process). In the assembling step, a conventionally known assembling step of a semiconductor device is performed. For example, among the chips after dicing, chips in an ordinary operating state (good chips) in the inspection step of step S3 are picked up, mounted on a large substrate, and sealed with a sealing resin. As described above, the positional information of the good chips (chip formation regions 51) is stored in the control/analysis device 19, for example, and the chips are picked up using the positional information. In the assembly process, a plurality of chips may be stacked for the purpose of increasing the capacity. The above is an example of a semiconductor manufacturing method.
[ Effect ]
As described above, the semiconductor manufacturing method according to embodiment 1 includes the steps of: the following are formed corresponding to each chip forming region 51 of the wafer 50 having a plurality of chip forming regions 51: a memory cell 57; a photodiode 71 that outputs an electrical signal corresponding to the input optical signal; and a signal processing circuit 72 for generating a logic signal based on the electric signal outputted from the photodiode 71 and outputting the logic signal to the memory cell 57; after the formation process, the pumping light for confirming the operation of the memory cell 57 is inputted to the photodiode 71, and the operation state of the memory cell 57 is checked; and after the inspection process, dicing is performed for each chip formation region 51.
In the semiconductor manufacturing method according to embodiment 1, the following are formed corresponding to the chip forming region 51: a photodiode 71 that outputs an electrical signal corresponding to the optical signal; and a signal processing circuit 72 that generates a logic signal based on the electrical signal. Then, the operation state of the internal circuit such as the memory cell 57 is checked by inputting the pump light to the photodiode 71, and then the dicing is performed for each chip formation region 51. Since the signal for confirming the operation of the internal circuit is input as an optical signal in this way, it is not necessary to bring the pin for signal input into contact with the input terminal 53. Therefore, in the method of bringing the pins for signal input into contact with the terminals of the circuit, the increase in the pressing force against the semiconductor wafer, which is a problem when the operating state of the integrated circuit is confirmed to have a high density, does not become a problem. Then, since a logic signal is generated by the signal processing circuit 72 based on the electric signal output from the photodiode 71 and the logic signal is input to the memory cell 57, even in a case where an optical signal is input as a signal for operation confirmation, the operation confirmation of the internal circuit is appropriately performed in the same manner as in a case where a pin is brought into contact with a terminal of a circuit as in the related art. In addition, in the method of bringing the pins for signal input into contact with the terminals of the circuit, when the operation of the integrated circuit is checked with a high density, the pins need to be brought into contact with the densely arranged terminals with high precision, and therefore, the pin tip needs to be miniaturized. This may not sufficiently cope with the increase in density of the integrated circuit. In this regard, in the semiconductor manufacturing method according to embodiment 1, since the signal for operation confirmation is input as the optical signal, the shape of the pin tip does not become a problem when the operation confirmation of the integrated circuit with higher density is performed. Thus, according to the semiconductor manufacturing method of embodiment 1, a semiconductor manufacturing method that can cope with the densification of an integrated circuit is provided. In the method of physically contacting the pin for signal input with the terminal of the circuit, there is an upper limit (for example, 100 MHz) to the frequency band of the signal that can be supplied from the pin, and there is a case where the upper limit cannot cope with a high-speed input signal. In this regard, in the semiconductor manufacturing method according to embodiment 1, since the signal for confirming the operation is supplied not by physical contact of the pin but by input of the optical signal, the signal having the frequency band exceeding the upper limit can be supplied as the signal for confirming the operation.
In embodiment 1, in the forming step, the photodiode 71 and the signal processing circuit 72 are formed outside the chip forming region 51 in correspondence with the chip forming region 51. Thus, the photodiode 71 and the signal processing circuit 72, which are components for operation confirmation, are separated from the chip by dicing after operation confirmation (inspection of the operation state). This makes it possible to minimize the chip, and to avoid the chip area from being limited by the formation of the inspection device 70 such as the photodiode 71. In embodiment 1, the inspection device 70 is formed on the scribe line 60. The scribe line 60 is an area that is a margin in dicing and is an area necessary for dicing. By forming the inspection device 70 in such a region, it is not necessary to separately secure a region of the semiconductor wafer 50 for forming the inspection device 70, and the region of the wafer 50 is effectively used.
In embodiment 1, the output terminal 54 which is an output terminal for outputting an output signal from the memory cell 57 is formed in correspondence with the chip forming region 51 in the forming step, and the operating state of the memory cell 57 is checked by inputting probe light to a region corresponding to the output terminal 54, detecting a signal corresponding to the output signal output from the output terminal 54 in response to the input of a logic signal to the memory cell 57 in the checking step. By inputting the optical signal into the region corresponding to the output terminal 54 and detecting the signal corresponding to the output signal in this way, the signal for checking the operating state of the internal circuit is detected without bringing the probe pin into contact with the output terminal 54. This suppresses an increase in pressing force against the wafer (particularly, a chip formation region of the wafer) which is a problem in the method of bringing the probe pins into contact with the terminals. Namely, a semiconductor manufacturing method more suitable for increasing the density of an integrated circuit is provided.
In embodiment 1, in the forming step, a PCA73 is further formed in correspondence with the chip forming region 51, the PCA73 is electrically connected to the output terminal 54 and outputs a signal corresponding to the output signal during the period of inputting the optical signal, and in the inspection step, while changing the delay time of the probe light, which is the pulse light synchronized with the pump light, with respect to the input timing of the pump light to the photodiode 71, the probe light, which is the pulse light synchronized with the pump light, is repeatedly input to the PCA73, and the signal corresponding to the output signal output from the PCA73 is detected. That is, in the inspection step, probe light synchronized with pump light, which is pulsed light continuously output in a predetermined cycle, is input to the PCA73 with a delay time of a predetermined delay time with respect to the timing of input of the pump light to the photodiode 71, and the delay time is changed to detect a signal corresponding to an output signal output from the PCA73 in response to input of each pulse of the probe light. In this way, the probe light is repeatedly input to the PCA73 with a timing delay with respect to the input of the pump light to the photodiode 71, and the delay time is changed during the repeated input, whereby the output signal output from the output terminal 54 can be sampled, and the operation state of the internal circuit can be appropriately checked from the sampling result. In the case of such an inspection, the output signal output from the output terminal 54 is not directly measured, but the output signal is sampled by measuring the signal output from the PCA73 a plurality of times. Since the signal (signal corresponding to the output signal) output from the PCA73 is a signal having a narrow frequency band, for example, when the frequency band of the output signal output from the output terminal 54 is wide even when the logic signal is a high-speed signal, detection can be easily performed using a probe pin or the like. That is, by performing the inspection in the above-described manner, even when a high-speed signal is input, the operating state of the internal circuit is appropriately detected by using a simple configuration in which only a signal having a narrow frequency band can be detected, such as a probe pin.
< embodiment 2 >
Next, embodiment 2 will be described with reference to fig. 10 to 12. Hereinafter, the description will be mainly given of points different from embodiment 1.
[ wafer ]
As shown in fig. 10, unlike the wafer 50 of embodiment 1, the wafer 50A of embodiment 2 does not have the PCA73, and the nonlinear optical crystal 150 is disposed on the output terminal 54. The nonlinear optical crystal 150 does not necessarily have to be in contact with the output terminal 54, but needs to be close to the output terminal 54 to the extent that a change in the electric field of the output terminal 54 can be detected. The nonlinear optical crystal 150 may be disposed only on the output terminals 54 of the chip formation regions 51 under inspection or on the output terminals 54 of all the chip formation regions 51 in the inspection of the operating state of the wafer inspection apparatus 1A described below. In fig. 10, a part of the structure is omitted for convenience of explanation. Specifically, in fig. 10, the amplifier 72a and the frequency discriminator 72b are shown only as the signal processing circuit 72, and the memory block 52 (memory cell 57) is not shown.
Fig. 11 is a diagram illustrating reflection of probe light by the nonlinear optical crystal 150 disposed on the output terminal 54. In fig. 11, the arrows with one dotted line represent the electric field, and the arrows with a solid line represent the probe light. The nonlinear optical crystal 150 includes a crystal portion 151, a probe mirror 152, and a transparent electrode 153. Further, a ground electrode pin 133 is connected to the nonlinear optical crystal 150. The crystal portion 151 is constituted to include, for example, a single crystal of a ZnTe-based compound semiconductor. The probe light reflector 152 is provided on the lower surface side (output terminal 54 side) of the crystal 151 and reflects probe light. The transparent electrode 153 is provided on the upper surface side of the crystal 151 and serves as an incident surface of the probe light. The nonlinear optical crystal 150 is disposed on the output terminal 54. When the electric field at the output terminal 54 changes in accordance with the output signal output from the output terminal 54 in accordance with the logic signal, the electric field leaks to the nonlinear optical crystal 150, and the refractive index of the nonlinear optical crystal 150 changes. When the probe light enters such a nonlinear optical crystal 150, the polarization state (polarization plane) of the reflected light (reflected light of the probe light) reflected by the probe light reflector 152 changes in accordance with the change in the refractive index thereof. When the polarization state (polarization wave surface) of the reflected light changes, the amount of light (light intensity) reflected by the beam splitter 12A (polarization beam splitter) changes. The change in the light intensity is detected by the photodetector 99, and it is possible to determine whether or not the chip on which the device is formed is good (defective).
[ wafer inspection apparatus ]
Fig. 10 is a schematic perspective view showing a wafer inspection apparatus 1A according to embodiment 2. The wafer inspection apparatus 1A shown in fig. 10 is an apparatus for inspecting an operation state of the memory cells 57 (internal circuits) formed in the chip forming region 51 of the wafer 50A, similarly to the wafer inspection apparatus 1 of embodiment 1. The wafer inspection apparatus 1A irradiates the photodiode 71 of the wafer 50A with pump light, irradiates the nonlinear optical crystal 150 on the output terminal 54 of the wafer 50A with probe light, and inspects the operating state of the internal circuit such as the memory cell 57 based on the reflected light from the nonlinear optical crystal 150. The wafer inspection apparatus 1 includes a tester 95, a VCSEL array 96, a probe light source 97, a beam splitter 12A, a wavelength plate 98, an optical scanner 15A, condenser lenses 16A, 17A, a photodetector 99, a lock-in amplifier 18A, and a control/analysis device 19A.
The tester 95 is operated by a power supply (not shown) to repeatedly apply an inspection electric signal to the VCSEL array 96 and the probe light source 97. Thus, the VCSEL array 96 and the probe light source 97 generate light based on a common inspection electric signal, and the light output from them can be synchronized with each other.
A VCSEL (Vertical-Cavity Surface Emitting Laser) array 96 is a Surface Emitting Laser, and irradiates a plurality of photodiodes 71 with Laser light as pump light at the same time (in parallel). The VCSEL array 96 generates laser light based on the inspection electric signal input from the tester 95. The VCSEL array 96 may be modulated, for example, around 40GBPS, and may form an incident pulse train equivalent to 40 GBPS. The VCSEL array 96 has light emitting points arranged at a predetermined pitch (e.g., 250 μm). By setting the predetermined pitch to a distance at which the plurality of photodiodes 71 are adjacent to each other, the respective photodiodes 71 can be simultaneously (parallelly) irradiated with laser light. Note that the pitch of the light emitting points of the VCSEL array 96 does not necessarily need to be equal to the pitch of the photodiodes, and for example, when the light emitting points are arranged at a pitch of 250 μm, the light may be reduced to 1/2 or 1/4 using a lens system, and the photodiodes 71 arranged in an array at a pitch of 125 μm or 62.5 μm may be irradiated with light. The pump light emitted from the VCSEL array 96 is transmitted through the condenser lens 16A and irradiated on each photodiode 71.
The probe light source 97 is a light source that outputs probe light, which is pulsed light irradiated to the nonlinear optical crystal 150. The probe light source 97 generates probe light based on the inspection electric signal input from the tester 95. The probe light is synchronized with the laser light (pump light) generated in the VCSEL array 96 described above. More specifically, the probe light output from the probe light source 97 is an optical signal that is synchronized with the pump light output from the VCSEL array 96 and is delayed from the pump light by a predetermined time. The probe light source 97 repeatedly outputs probe light while changing the delay time with respect to the pump light, for example, for each pulse. In this case, the detection light source 97 may include an electric circuit for changing the delay time. Thus, as in embodiment 1, the high-speed output pulse (output signal output from the output terminal 54) can be detected while sampling. In addition, the detection light source 97 may be a light source that outputs CW light instead of pulsed light. In this case, the probe light may not be delayed with respect to the pump light.
The beam splitter 12A is a polarization beam splitter configured to transmit light having a polarization component of 0 degrees and to reflect light having a polarization component of 90 degrees. The beam splitter 12A transmits light having a polarization component of 0 degree output from the detection light source 97. The probe light transmitted through the beam splitter 12A is irradiated to the nonlinear optical crystal 150 through the wavelength plate 98 which is a λ/8 wavelength plate, the optical scanner 15A, and the condenser lens 17A. The optical scanner 15A scans the probe light in response to a control signal from the control/analysis device 19A so as to irradiate the nonlinear optical crystal 150 on each output terminal 54 with the probe light. Further, the reflected light from the nonlinear optical crystal 150 corresponding to the probe light is input to the beam splitter 12A via the condenser lens 17A, the optical scanner 15A, and the wavelength plate 98. The reflected light passes through the wavelength plate 98, which is a λ/8 wavelength plate, 2 times to become circularly polarized light, and the reflected light having a polarization component of 90 degrees in the circularly polarized light is reflected by the beam splitter 12A and input to the photodetector 99.
The photodetector 99 is, for example, a photodiode, an avalanche photodiode, a photomultiplier tube, or an area image sensor, and receives reflected light from the nonlinear optical crystal 150 (a signal corresponding to an output signal output from the output terminal 54 in response to an input of a logic signal to an internal circuit) and outputs a detection signal. Only the signal component of the detection signal having a predetermined frequency is amplified by the lock-in amplifier 18A, and the amplified signal is input to the control/analysis device 19A. The control/analysis device 19A generates a waveform (analysis image) based on the amplified signal from the lock-in amplifier 18A. The user can determine whether or not the chip on which the device is formed is good (defective) based on the analysis image generated by the control/analysis device 19A, for example.
The inspection method according to embodiment 2 (inspecting the operating state of the internal circuit such as the memory cell 57 based on the reflected light from the nonlinear optical crystal 150) may be performed by the wafer inspection apparatus 1 according to embodiment 1 instead of the wafer inspection apparatus 1A shown in fig. 10.
[ wafer inspection method ]
Next, an example of a wafer inspection method using the wafer inspection apparatus 1A will be described with reference to a flowchart of fig. 12. The wafer inspection method is the "step S3: the method carried out in the inspection step ".
As shown in fig. 12, first, a wafer 50A on which device formation has been completed is set on an inspection stage (not shown) of the wafer inspection apparatus 1A (step S131). Next, one chip formation region 51 is selected from the plurality of chip formation regions 51 included in the wafer 50A (step S132). Specifically, upon receiving an instruction input from the user to start the inspection, for example, the control/analysis device 19A specifies the chip forming region 51 at a predetermined position as the chip forming region 51 to be inspected first. Next, the nonlinear optical crystal 150 is disposed on the output terminal 54 of the selected chip forming region 51 (step S133).
Next, the self-tester 95 applies an inspection electric signal to the VCSEL array 96 and the probe light source 97 (step S134). Thus, the VCSEL array 96 and the probe light source 97 generate light based on a common inspection electric signal, and the light output from them can be synchronized with each other.
Next, the plurality of photodiodes 71 are simultaneously (in parallel) irradiated with laser light as pump light (step S135). Specifically, the control/analysis device 19A controls the VCSEL array 96 so as to irradiate the photodiodes 71 in the selected chip formation region 51 with the pump light.
Next, one output terminal 54 is selected from among the output terminals 54 in the selected chip forming region 51 (step S136). Specifically, the control/analysis device 19A specifies one of the output terminals 54 according to a predetermined selection order. Next, probe light is irradiated to the nonlinear optical crystal 150 on the selected output terminal 54 (step S137). Specifically, the control/analysis device 19A controls the probe light source 97 and the optical scanner 15A so as to irradiate the probe light to a desired position. The control/analysis device 19A controls the probe light source 97 so that probe light synchronized with the pump light is input to the nonlinear optical crystal 150 with a delay in timing of the input of the pump light to the photodiode 71. Since the nonlinear optical crystal 150 is disposed on the output terminal 54, the electric field changes based on the output signal output from the output terminal 54 in response to the logic signal, and as a result, the refractive index changes. When the probe light is incident on the nonlinear optical crystal 150, the polarization state of the reflected light (reflected light of the probe light) reflected by the probe light reflecting mirror 152 changes in accordance with the change in the refractive index thereof. The intensity of light output from the beam splitter 12A (polarizing beam splitter) changes due to a change in the polarization state of the reflected light. The photodetector 99 receives the change in light intensity, and generates an analysis image in the control/analysis device 19A based on a detection signal from the photodetector 99. For example, after the inspection of all the chip forming regions 51 of the wafer 50A is completed, the user can check whether or not the operation state of the region of the inspected memory cell 57 is a normal state based on the analysis image.
Next, it is determined whether or not there is an output terminal 54 before selection in the selected chip forming region 51 (step S138). Since the number of output terminals 54 of each chip forming region 51 can be grasped in advance, the control/analysis device 19A determines whether or not there is an output terminal 54 before selection, for example, based on whether or not probe light irradiation is performed in accordance with the number of output terminals 54 of one chip forming region 51.
If it is determined in step S138 that there is an output terminal 54 before selection in the selected chip formation region 51 (no in S138), one output terminal 54 before selection is selected (step S139). Thereafter, the processes in steps S137 and S138 described above are performed again.
On the other hand, if it is determined in step S138 that the output terminal 54 before selection is not present in the selected chip forming region 51 (yes in S138), it is determined whether or not the chip forming region 51 before inspection is present in the wafer 50A (step S140). Since the number of chip forming regions 51 of the wafer 50A can be grasped in advance, the control/analysis device 19 selects the chip forming regions 51 based on whether or not the number of chip forming regions 51 of the wafer 50A is equal to or less than the number of chip forming regions 51, and determines whether or not the chip forming regions 51 before inspection exist.
If it is determined in step S140 that there is a chip forming region 51 before inspection in the wafer 50A (no in S140), one chip forming region 51 before inspection is selected (step S141). Specifically, the control/analysis device 19A specifies the chip formation region 51 to be inspected next according to a predetermined selection procedure. Thereafter, the processes of steps S133 to S140 described above are performed again. On the other hand, when it is determined in step S140 that there is no chip forming region 51 before inspection of the wafer 50A (S140: YES), the "inspection step" for the wafer 50A is ended.
[ Effect ]
As described above, in the semiconductor manufacturing method according to embodiment 2, in the inspection step, the nonlinear optical crystal 150 is disposed on the output terminal 54, probe light is input to the nonlinear optical crystal 150, and the reflected light from the nonlinear optical crystal 150 is detected as a signal corresponding to the output signal. The refractive index of the nonlinear optical crystal 150 changes in accordance with the voltage of the output terminal 54 (i.e., the voltage of the output signal output from the output terminal 54). Therefore, the reflected light from the nonlinear optical crystal 150 changes in polarization state according to the voltage of the output signal output from the output terminal 54. By detecting such a change in polarization state as a change in light intensity via the beam splitter 12A, the operating state of the internal circuit can be checked in accordance with the intensity of the reflected light. By performing the inspection in the above-described manner, the operating state of the internal circuit can be appropriately inspected only by a simple configuration relating to the detection of the reflected light without bringing the probe pins or the like into contact with the wafer 50A.
< embodiment 3 >
Next, embodiment 3 will be described with reference to fig. 13 to 15. Hereinafter, differences from embodiments 1 and 2 will be mainly described.
[ wafer inspection apparatus ]
Fig. 13 is a schematic diagram of a wafer inspection apparatus 1B according to embodiment 3. The wafer inspection apparatus 1B shown in fig. 13 is an apparatus for inspecting an operation state of the memory cells 57 (internal circuits) formed in the chip forming region 51 of the wafer 50, similarly to the wafer inspection apparatus 1 of embodiment 1 and the like. The wafer inspection apparatus 1B irradiates pulsed light to the photodiode 71 of the wafer 50, irradiates probe light (CW or pulsed light) from the opposite side (back side) of the wafer 50 from the surface on which the photodiode 71 is formed, and inspects the operating state of the internal circuit such as the memory cell 57 based on the light emitted from the back side.
Fig. 14 is a diagram illustrating a change in reflectance according to expansion and contraction of a depletion layer. As shown in fig. 14, the wafer 50 includes a FET including a gate 191, a source 192, and a drain 193. The depletion layer DL of the FET expands and contracts in response to high/low of a logic signal inputted to the memory cell 57, and the thickness thereof changes. Therefore, by detecting the change in the thickness of the depletion layer DL, the operating state of the internal circuit can be checked. Here, the thickness change of the depletion layer DL can be detected based on the intensity change of the reflected light when light is irradiated from the back surface side of the wafer 50 (the intensity change of the reflected light accompanying the change of the reflectance corresponding to the thickness change of the depletion layer DL). In view of this, in the wafer inspection apparatus 1B of the present embodiment, probe light is irradiated from the back surface side of the wafer 50, and the probe light is reflected on the surface of the device through the inside of the depletion layer, thereby detecting light emitted from the back surface side.
Returning to fig. 13, wafer inspection apparatus 1 includes VCSEL array 96B, probe light source 140, beam splitter 12B, wavelength plate 98B, condenser lenses 16B, 17B, photodetector 99B, lock-in amplifier 18B, and control/analysis device 19B.
The VCSEL array 96B irradiates laser light (pulsed light) to the plurality of photodiodes 71 simultaneously (in parallel). The VCSEL array 96B is disposed at a position where pulsed light can be irradiated to the photodiode 71. The pulsed light emitted from the VCSEL array 96B is transmitted through the condenser lens 16B and is irradiated to each photodiode 71. The probe light source 140 irradiates probe light (2 nd optical signal) from the back surface side opposite to the surface of the wafer 50 on which the photodiode 71 is formed. The probe light source 140 is disposed at a position where probe light can be irradiated to the back surface of the wafer 50 (i.e., the back surface side of the wafer 50).
The beam splitter 12B is a polarization beam splitter configured to transmit light having a polarization component of 0 degrees and reflect light having a polarization component of 90 degrees. The beam splitter 12B transmits light having a polarization component of 0 degree output from the detection light source 140. The probe light transmitted through the beam splitter 12B is irradiated to the back surface side of the wafer 50 through a wavelength plate 98B which is a λ/8 wavelength plate and a condenser lens 17B. Further, the reflected light from the back surface side of the wafer 50 corresponding to the probe light is input to the beam splitter 12B via the condenser lens 17B and the wavelength plate 98B. The reflected light passes through the wavelength plate 98B, which is a λ/8 wavelength plate, 2 times to become circularly polarized light, and the reflected light having a polarization component of 90 degrees in the circularly polarized light is reflected by the beam splitter 12B and input to the photodetector 99B.
The photodetector 99B receives the reflected light and outputs a detection signal. Only the signal component of the detection signal having a predetermined frequency is amplified by the lock-in amplifier 18A, and the amplified signal is input to the control/analysis device 19B. The control/analysis device 19A generates a waveform (analysis image) based on the amplified signal from the lock-in amplifier 18B. The user can determine whether or not the chip on which the device is formed is good (defective) based on the analysis image generated by the control/analysis device 19B, for example.
[ wafer inspection method ]
Next, an example of a wafer inspection method using the wafer inspection apparatus 1B will be described with reference to a flowchart of fig. 15. The wafer inspection method is the "step S3: the method carried out in the inspection step ".
As shown in fig. 15, first, the wafer 50 on which device formation has been completed is set on an inspection stage (not shown) of the wafer inspection apparatus 1B (step S231). Next, one chip formation region 51 is selected from the plurality of chip formation regions 51 included in the wafer 50 (step S232). Specifically, upon receiving an instruction input from the user to start the inspection, for example, the control/analysis device 19B specifies the chip forming region 51 at a predetermined position as the chip forming region 51 to be inspected first.
Next, the laser light from the VCSEL array 96B is simultaneously (in parallel) irradiated to the plurality of photodiodes 71 (step S233). Specifically, the control/analysis device 19B controls the VCSEL array 96B so as to irradiate laser light to each photodiode 71 corresponding to the selected chip forming region 51.
Next, probe light is irradiated to the back surface side opposite to the surface of the wafer 50 on which the photodiode 71 is formed (step S234). Specifically, the control/analysis device 19B controls the probe light source 140 so as to irradiate probe light from the back surface side of the wafer 50. The depletion layer DL (see fig. 14) of the wafer 50 expands and contracts in accordance with the high/low of the logic signal input to the memory cell 57, and changes in thickness are detected based on the change in intensity of the reflected light when the wafer 50 is irradiated with light on the back surface side. The reflected light is received by the photodetector 99B, and an analysis image is generated in the control/analysis device 19B based on a detection signal from the photodetector 99. For example, after the inspection of all the chip forming regions 51 of the wafer 50 is completed, the user can check whether or not the operation state of the region of the inspected memory cell 57 is a normal state based on the analysis image.
Next, it is determined whether or not the wafer 50 has the chip forming region 51 before the inspection (step S235). Since the number of chip forming regions 51 of the wafer 50 can be grasped in advance, the control/analysis device 19B selects the chip forming regions 51 based on whether or not the number of chip forming regions 51 of the wafer 50 is equal to or less than the number of chip forming regions 51, and determines whether or not the chip forming regions 51 before inspection exist. If it is determined in step S235 that there is a chip formation region 51 before inspection in the wafer 50 (no in S235), one chip formation region 51 before inspection is selected (step S236). Specifically, the control/analysis device 19B specifies the chip formation region 51 to be inspected next according to a predetermined selection procedure. Thereafter, the processing of steps S233 to S235 described above is performed again. On the other hand, when it is determined in step S235 that there is no chip forming region 51 before inspection of the wafer 50 (yes in S235), the "inspection process" for the wafer 50 is ended.
[ Effect ]
As described above, in the semiconductor manufacturing method according to embodiment 3, in the inspection step, probe light is input to the surface of the wafer 50 opposite to the surface on which the photodiode 71 is formed, and the operation state of the memory cell 57 is inspected by detecting reflected light from the surface opposite to the surface. By inputting a logic signal to the memory cell 57, the thickness of the depletion layer of the wafer is varied. Such a change in the thickness of the depletion layer can be detected by a change in the intensity of reflected light when an optical signal is input from the back surface (the surface opposite to the surface on which the photodiode 71 is formed). Thus, by detecting the reflected light from the back surface, the operating state of the internal circuit can be appropriately checked without using a probe pin or the like. Further, since the VCSEL array 96B is provided on the side where the photodiode 71 is formed and the detection light source 140 is provided on the opposite side, it is possible to appropriately secure an installation space for each light source with a margin.
< modification example >
While the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments 1 to 3.
For example, although the memory cell 57 is formed as an internal circuit in the chip formation region 51, the present invention is not limited to this, and a logic circuit such as a microprocessor, an application processor (high-density integrated circuit) such as an LSI (Large Scale Integration), a hybrid integrated circuit in which a memory cell and a logic circuit are combined, an integrated circuit for special applications such as a gate array or a cell-based IC, or the like may be formed as an internal circuit in the chip formation region.
The transmission path of the electrical signal from the photodiode 71 to the memory cell 57 is described with reference to fig. 5, but the transmission path of the electrical signal from the photodiode to the memory cell (internal circuit) is not limited to the path shown in fig. 5. That is, in the example shown in fig. 5, the electric signal output from the photodiode 71 is input to the memory cell 57 via the amplifier 72a, the frequency discriminator 72b, the input terminal 53, the ESD prevention circuit 91, and the signal buffer circuit 92, but the present invention is not limited thereto, and the logic signal output from the frequency discriminator 72b may be directly input to the memory cell 57 without via the input terminal 53 or the like as shown in fig. 16. That is, the frequency discriminator 72b of the signal processing circuit 72 may be connected to the memory cell 57 via the wiring 190 bypassing the input terminal 53 so that the logic signal is input to the memory cell 57 without via the input terminal 53. With this configuration, the capacitance of the input terminal does not become a problem in checking the operation of the internal circuit, and a high-speed electrical signal can be easily input to the internal circuit.
Further, as the wafer, the wafer 50 in which the structures of the inspection devices 70 are arranged on the scribe line 60 outside the chip formation region has been described, but the structure of the wafer is not limited to this, and for example, the structures of the inspection devices 70 may be formed in a region outside the chip formation region other than the scribe line 60.
In addition, each structure of the inspection device may be formed in the chip formation region. Fig. 17 is a schematic plan view of 1 chip formation region of a wafer according to a modification example, as viewed from the device formation region side. The wafer 250 shown in fig. 17 is a wafer provided with PCA, similarly to the wafer 50 of embodiment 1. As shown in fig. 17, the wafer 250 includes a memory block 252 including memory cells 257, an input terminal 253, an output terminal 254, a power supply terminal 255, a ground terminal 256, a photodiode 271 as an inspection device, an amplifier 272a, a frequency detector 272b, a PCA273, and pads 274, 275, 276, and 277 as a structure formed in the chip forming region 251. That is, in the wafer 250, the structures of the inspection devices are not formed outside the chip formation region such as the scribe line 260, but are formed entirely within the chip formation region 251.
In the wafer 250, the arrangement area of the memory blocks 252 is not limited, but in the example shown in fig. 17, a pair of memory blocks 252 are arranged at both ends so as to sandwich an inspection device or the like provided near the center. The input terminal 253 includes a through electrode 253a that penetrates the wafer 250 in the thickness direction, and similarly, the output terminal 254 includes a through electrode 254a that penetrates the wafer 250 in the thickness direction. By forming the through- electrodes 253a and 254a, in a structure in which a plurality of chips are stacked, the plurality of chips can be electrically connected to each other without using wire bonding or the like. That is, the chip having the through-electrodes is significant for reducing the number of wires for wire bonding and the like. In this regard, by adopting the structure in which the inspection device is formed in the chip formation region as in the wafer 250, the wiring such as wire bonding for the inspection device can be shortened as compared with the case in which the inspection device is formed outside the chip formation region, and the effect of the semiconductor structure in which the chips are laminated through the through electrode can be more remarkably exhibited. That is, by adopting a structure in which an inspection device or the like is formed in the chip formation region, a chip having a preferable structure (for example, a structure in which a plurality of chips are stacked via a through electrode or the like) in which wiring such as wire bonding is shortened as much as possible can be provided.
Further, the method of detecting the signal for checking the operating state of the internal circuit without bringing the pin into contact with the output terminal has been described, but the method is not limited to this, and the pin may be brought into contact with the output terminal to detect the signal. In this case, since the signal for confirming the operation of the internal circuit is also inputted as an optical signal (the pin is not in contact with the terminal of the circuit on the input side), the pressing force to the wafer can be reduced as compared with the conventional one.
Description of the symbols
50. 50A, 250 … wafer, 51, 251 … chip forming region, 53, 253 … input terminal, 54, 254 … output terminal, 57, 257 … memory cell (internal circuit), 60 … scribe, 70 … inspection device, 71, 271 … photodiode (light receiving element), 72 … signal processing circuit, 72a, 272a … amplifier, 72b, 272b … frequency discriminator, 150 … nonlinear optical crystal, 253a, 254a … through electrode.
Claims (12)
1. A method for manufacturing a semiconductor, characterized in that,
the disclosed device is provided with:
forming an internal circuit, a light receiving element, and a signal processing circuit in correspondence with each chip formation region of a semiconductor wafer having a plurality of chip formation regions, the light receiving element outputting an electrical signal corresponding to an input optical signal, the signal processing circuit generating a logic signal based on the electrical signal output from the light receiving element and outputting the logic signal to the internal circuit;
a step of inputting a 1 st optical signal for checking the operation of the internal circuit to the light receiving element after the forming step, and checking the operation state of the internal circuit; and
and a step of performing dicing for each of the chip forming regions after the step of inspecting.
2. The semiconductor manufacturing method according to claim 1,
in the forming step, the light receiving element and the signal processing circuit are formed outside the chip forming region in correspondence with the chip forming region.
3. The semiconductor manufacturing method according to claim 1,
in the forming step, the light receiving element and the signal processing circuit are formed in the chip forming region so as to correspond to the chip forming region.
4. The semiconductor manufacturing method according to any one of claims 1 to 3,
in the forming step, an output terminal for outputting an output signal from the internal circuit is further formed in correspondence with the chip forming region,
in the inspection step, the 2 nd optical signal is input to the region corresponding to the output terminal, whereby a signal corresponding to the output signal output from the output terminal in accordance with the input of the logic signal to the internal circuit is detected, and the operating state of the internal circuit is inspected.
5. The semiconductor manufacturing method according to claim 4,
in the forming step, a switch portion that is electrically connected to the output terminal and outputs a signal corresponding to the output signal during a period in which the optical signal is input is further formed in correspondence with the chip forming region,
in the inspection step, while changing a delay time of a2 nd optical signal, which is pulse light synchronized with the 1 st optical signal, with respect to an input timing of the 1 st optical signal to the light receiving element, the 2 nd optical signal is repeatedly input to the switch unit, and a signal corresponding to the output signal output from the switch unit is detected.
6. The semiconductor manufacturing method according to claim 4,
in the inspection step, a nonlinear optical crystal is disposed on the output terminal, the 2 nd optical signal is input to the nonlinear optical crystal, and the reflected light from the nonlinear optical crystal is detected as a signal corresponding to the output signal.
7. The semiconductor manufacturing method according to any one of claims 1 to 3,
in the inspection step, a2 nd optical signal is input to a surface of the semiconductor wafer opposite to the surface on which the light receiving element is formed, and the operation state of the internal circuit is inspected by detecting reflected light from the surface opposite to the surface.
8. A wafer inspection method is characterized in that,
the disclosed device is provided with:
a step of preparing a semiconductor wafer having formed thereon: an internal circuit; a light receiving element that outputs an electrical signal corresponding to an input optical signal; and a signal processing circuit that generates a logic signal based on the electric signal output from the light receiving element and outputs the logic signal to the internal circuit; and
and a step of inputting a 1 st optical signal for checking the operation of the internal circuit to the light receiving element after the preparation step, and checking the operation state of the internal circuit.
9. The wafer inspection method of claim 8,
in the preparing step, the semiconductor wafer further having an output terminal for outputting an output signal from the internal circuit is prepared,
in the inspection step, a2 nd optical signal is input to a region corresponding to the output terminal, so that a signal corresponding to an output signal output from the output terminal in accordance with the input of the logic signal to the internal circuit is detected, and the operating state of the internal circuit is inspected.
10. The wafer inspection method of claim 9,
in the preparation step, a switch portion electrically connected to the output terminal and outputting a signal corresponding to the output signal during a period in which the optical signal is input is further formed,
in the inspection step, while changing a delay time of a2 nd optical signal, which is pulse light synchronized with the 1 st optical signal, with respect to an input timing of the 1 st optical signal to the light receiving element, the 2 nd optical signal is repeatedly input to the switch unit, and a signal corresponding to the output signal output from the switch unit is detected.
11. The wafer inspection method of claim 9,
in the inspection step, a nonlinear optical crystal is disposed on the output terminal, the 2 nd optical signal is input to the nonlinear optical crystal, and the reflected light from the nonlinear optical crystal is detected as a signal corresponding to the output signal.
12. The wafer inspection method of claim 8,
in the inspection step, a2 nd optical signal is input to a surface of the semiconductor wafer opposite to the surface on which the light receiving element is formed, and the operation state of the internal circuit is inspected by detecting reflected light from the surface opposite to the surface.
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| JP2017-139301 | 2017-07-18 | ||
| JP2017139301A JP2019021778A (en) | 2017-07-18 | 2017-07-18 | Semiconductor manufacturing method and wafer inspection method |
| PCT/JP2018/022585 WO2019017120A1 (en) | 2017-07-18 | 2018-06-13 | Semiconductor production method and wafer inspection method |
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| US (1) | US20200258794A1 (en) |
| JP (1) | JP2019021778A (en) |
| KR (1) | KR20200033878A (en) |
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| CN112180505A (en) * | 2020-10-22 | 2021-01-05 | 武汉光谷信息光电子创新中心有限公司 | Photoelectric integrated chip |
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| TWI749580B (en) * | 2020-06-08 | 2021-12-11 | 星河半導體股份有限公司 | Multi-channel antenna chip test system and method |
| WO2023002688A1 (en) * | 2021-07-19 | 2023-01-26 | 浜松ホトニクス株式会社 | Semiconductor error analysis device and semiconductor error analysis method |
| JP7186934B1 (en) * | 2021-07-19 | 2022-12-09 | 浜松ホトニクス株式会社 | Semiconductor failure analysis device and semiconductor failure analysis method |
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- 2018-06-13 WO PCT/JP2018/022585 patent/WO2019017120A1/en active Application Filing
- 2018-06-13 KR KR1020207003856A patent/KR20200033878A/en not_active Application Discontinuation
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| US5751159A (en) * | 1995-09-05 | 1998-05-12 | Motorola, Inc. | Semiconductor array and switches formed on a common substrate for array testing purposes |
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| CN112180505B (en) * | 2020-10-22 | 2022-08-16 | 武汉光谷信息光电子创新中心有限公司 | Photoelectric integrated chip |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20200033878A (en) | 2020-03-30 |
| TW201918723A (en) | 2019-05-16 |
| WO2019017120A1 (en) | 2019-01-24 |
| JP2019021778A (en) | 2019-02-07 |
| US20200258794A1 (en) | 2020-08-13 |
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