CN110880934A - Successive approximation type analog-to-digital converter and calibration method - Google Patents
Successive approximation type analog-to-digital converter and calibration method Download PDFInfo
- Publication number
- CN110880934A CN110880934A CN201911242441.1A CN201911242441A CN110880934A CN 110880934 A CN110880934 A CN 110880934A CN 201911242441 A CN201911242441 A CN 201911242441A CN 110880934 A CN110880934 A CN 110880934A
- Authority
- CN
- China
- Prior art keywords
- digital
- analog
- successive approximation
- signal
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000005070 sampling Methods 0.000 claims abstract description 27
- 238000006243 chemical reaction Methods 0.000 claims description 23
- 239000003990 capacitor Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 8
- 230000006870 function Effects 0.000 description 4
- 101150071746 Pbsn gene Proteins 0.000 description 3
- 238000010845 search algorithm Methods 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000012886 linear function Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- UDQDXYKYBHKBTI-IZDIIYJESA-N 2-[4-[4-[bis(2-chloroethyl)amino]phenyl]butanoyloxy]ethyl (2e,4e,6e,8e,10e,12e)-docosa-2,4,6,8,10,12-hexaenoate Chemical compound CCCCCCCCC\C=C\C=C\C=C\C=C\C=C\C=C\C(=O)OCCOC(=O)CCCC1=CC=C(N(CCCl)CCCl)C=C1 UDQDXYKYBHKBTI-IZDIIYJESA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229920005994 diacetyl cellulose Polymers 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention provides a successive approximation type analog-to-digital converter and a calibration method, wherein the successive approximation type analog-to-digital converter comprises: the circuit comprises a sampling/holding circuit, a digital-analog converter, a comparator, a successive approximation logic circuit, a clock generation circuit and a digital pseudo-random signal generator; the analog input signal is connected to the sampling/holding circuit, the positive and negative input ends of the comparator are respectively connected with the digital-analog converter and the sampling/holding circuit, and the output end is connected with the successive approximation logic circuit; the successive approximation logic circuit and the digital pseudo-random signal generator are connected to the input of the adder, and the output of the adder is connected with the digital-analog converter; the successive approximation logic circuit and the digital pseudorandom signal generator are connected to the input of the subtracter, and the output of the subtracter is a final output result; the clock generation circuit is respectively connected with the comparator and the successive approximation logic circuit. The harmonic energy is reduced, the spurious-free dynamic range of the ADC is improved, and the linearity of the core ADC is effectively improved.
Description
Technical Field
The invention relates to the technical field of mixed signal circuits, in particular to a successive approximation type analog-to-digital converter and a calibration method.
Background
In a communication circuit, an analog-to-digital converter (ADC) is a very important module, which is responsible for converting an analog signal received by a Radio Frequency Front End (RFFE) into a digital signal, and providing the digital signal to a Digital Signal Processor (DSP) for processing. In the development process of the receiver architecture, as the radio frequency front end design is more and more simplified, the faster and more powerful the digital processor functions, the performance of the ADC becomes more and more a bottleneck restricting the performance of the receiver. The metrics for measuring the analog-to-digital converter mainly include bandwidth (speed), accuracy and power consumption.
A successive approximation type (SAR) analog-to-digital converter (ADC) occupies most of the medium-resolution ADC market, is an ADC structure based on a binary search algorithm and consists of an input sampling switch, a DAC, a comparator and an SAR digital control logic module. Due to the simple structure and no need of an analog operational amplifier, the successive approximation type analog-to-digital converter can realize the optimal energy efficiency (<10fJ/conv.) in the ADC. The basic working principle of an N-bit successive approximation type analog-to-digital converter is as follows: the analog input voltage (Va) is sample-held by a sample/hold circuit. To implement the binary search algorithm, the N-bit register in the SAR control logic module is first set at the middle scale (i.e., 100.. 00, MSB set to 1). Thus, the output of the DAC (Vdac) is set to VREF/2, where VREF is the reference voltage for the ADC. Then, the comparator compares and judges whether Va of the sample hold is smaller or larger than Vdac. If Va is greater than Vdac, the comparator outputs a logic high level or 1 and the MSB of the N-bit register remains at 1. Conversely, if Va is less than Vdac, the comparator outputs a logic low level, MSB of the N-bit register clear 0. The SAR control logic then moves to the next bit (MSB-1) and sets that bit high for the next comparison. This process continues until the LSB is completed, the N-bit conversion is completed, and the conversion result is stored in a register and output. It can be seen that the slew rate of the successive approximation type analog-to-digital converter is limited by the delay of the comparator, the delay of the SAR control logic module and the settling time of the DAC. For an N-bit successive approximation type analog-to-digital converter, the number of bits, precision and linearity of a DAC cannot be lower than that of the N-bit, so the precision of the successive approximation type analog-to-digital converter is mainly determined by the precision of the analog-to-digital converter (DAC). The DACs commonly used in the successive approximation type analog-to-digital converter at present include a voltage scaling type DAC, a current scaling type DAC and a charge scaling type DAC. The voltage scaling DAC is high in establishing speed and simple in working mode, but the increase of precision can cause the increase of switches, divider resistors and circuit area indexes, and meanwhile, precise voltage division is difficult to achieve; the matching of the current scaling type DAC current source has great influence on the precision, and the power consumption is greatly increased due to the increase of the precision; the charge scaling DAC has great advantages in power consumption, area, and matching, and is the most widely used DAC structure in recent years.
The linearity of most ADC types depends directly on the matching performance of some of the devices (such as capacitors, resistors and MOS transistors). In the actual production process of the chip, the matching degree of the devices is influenced by many factors, such as process matching parameters, the area of the devices, layout design and the like, so that the linearity of the ADC often cannot reach the preset target. There are many ideas to solve the non-linearity problem of the ADC, including calibration, non-linear cancellation, and input pre-distortion. In the prior art, a linear improved sampling switch with parasitic capacitance compensation is disclosed, so that the parasitic capacitance of the sampling switch is basically kept constant along with the change of an input signal, and the matching of a differential sampling switch is improved; another linear correction algorithm for capacitive digital to analog converters (CDACs) is also disclosed, in which the calibrated CDAC digital representation has no gain error because the capacitance weight error is represented as the difference between the actual weight and the ideal weight relative to the standard size.
Disclosure of Invention
The invention provides a successive approximation type analog-to-digital converter and a calibration method for solving the existing problems.
In order to solve the above problems, the technical solution adopted by the present invention is as follows:
a successive approximation analog to digital converter comprising: the circuit comprises a sampling/holding circuit, a digital-analog converter, a comparator, a successive approximation logic circuit, a clock generation circuit and a digital pseudo-random signal generator; the analog input signal is connected to the sampling/holding circuit, the positive and negative input ends of the comparator are respectively connected with the digital-analog converter and the sampling/holding circuit, and the output end of the comparator is connected with the successive approximation logic circuit; the successive approximation logic circuit and the digital pseudo-random signal generator are connected to the input of an adder, and the output of the adder is connected with the digital-analog converter; the successive approximation logic circuit and the digital pseudorandom signal generator are connected to the input of a subtracter, and the output of the subtracter is a final output result; the clock generation circuit is respectively connected with the comparator and the successive approximation logic circuit.
Preferably, the digital signal generated by the digital pseudo-random signal generator is simultaneous with the input of the analog input signal.
Preferably, the addition and subtraction of the digital signals generated by the digital pseudo-random signal generator are at the same time, at different locations.
Preferably, the digital pseudo-random signal generator is a linear feedback shift register, and is composed of at least three D flip-flops and at least one exclusive or gate.
Preferably, the digital signal generated by the digital pseudo-random signal generator has only one bit and acts on the most significant bit.
Preferably, the digital pseudo-random signal generator further comprises a pre-comparator and a multiplier, wherein the input end of the pre-comparator is respectively connected with the reference voltage and the input voltage signal, the input end of the multiplier is respectively connected with the output end of the comparator and the digital pseudo-random signal generator, and the output end of the multiplier is connected with one input of the adder.
Preferably, the pre-comparator is implemented by comparing the most significant bits of the comparator.
The invention also provides a calibration method of the successive approximation type analog-to-digital converter, which comprises the following steps: s1: the input analog signal is sampled and kept stable by a sampling/holding circuit; s2: the output of the sampling/holding circuit is compared by a comparator, and the comparison result is transmitted to a successive approximation logic circuit; s3: adding a digital signal generated by a digital pseudo-random signal generator and a digital signal generated by the successive approximation logic circuit to obtain a sum signal; s4: the sum signal is transmitted to a digital-analog converter to obtain an analog signal; s5: the comparator compares the analog signal generated by the digital-analog converter with the input analog signal to obtain a conversion result of the next bit, and then transmits the conversion result to the successive approximation logic circuit; s6: repeating the steps S3 to S5 until all bit conversion is completed; s7: the successive approximation logic circuit obtains a digital output result, and subtracts a digital signal generated by the digital pseudo-random signal generator from the digital output result to obtain a difference signal, namely the output result.
The invention also provides a calibration method of the successive approximation type analog-to-digital converter, which comprises the following steps: t1: the input analog signal is sampled and kept stable by a sampling/holding circuit; t2: the output of the sampling/holding circuit is compared by a comparator, and the comparison result is transmitted to a successive approximation logic circuit; t3: the analog input signal and the reference signal are compared through the pre-comparator to obtain a pre-comparison output result; t4: multiplying the pre-comparison output result by a digital signal generated by a digital pseudo-random signal generator to obtain a product signal; t5: the product signal and a digital signal generated by the successive approximation logic circuit are added to obtain a sum signal; t6: the sum signal is transmitted to a digital-analog converter to obtain an analog signal; t7: the comparator compares the analog signal generated by the digital-analog converter with the input analog signal to obtain a conversion result of the next bit, and then transmits the conversion result to the successive approximation logic circuit; t8: repeating the steps from T5 to T7 until all bit conversions are completed; t9: the successive approximation logic circuit obtains a digital output result, and subtracts a product signal from the digital output result to obtain a difference signal, namely an output result.
Preferably, the T3 step is: and obtaining a pre-comparison output result according to the most significant bit comparison result of the comparator.
The invention has the beneficial effects that: a successive approximation type analog-to-digital converter and a calibration method are provided, through adding a digital pseudo-random signal, the input of a core ADC presents randomness in time, and the selection process of devices (such as a capacitor, a resistor and an MOS (metal oxide semiconductor) transistor) determining the linearity of the core ADC is randomized. This means that the mismatch of these devices is first-order shaped, and it appears on the output spectrum of the core ADC that the harmonic energy caused by the mismatch of the original devices is dispersed to the noise energy of each frequency point of the whole signal bandwidth, thereby reducing the harmonic energy, improving the spurious-free dynamic range (SFDR) of the ADC, and effectively improving the linearity of the core ADC. Meanwhile, in order that the added analog pseudorandom signal does not reduce the precision (i.e., signal-to-noise ratio, SNR) of the core ADC, the digital pseudorandom signal needs to be subtracted at the digital output terminal of the core ADC correspondingly, so as to obtain the digital output of the overall ADC.
Drawings
Fig. 1 is a schematic structural diagram of a successive approximation type analog-to-digital converter in the prior art according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a prior art analog-to-digital converter based on a dither signal according to an embodiment of the present invention.
FIG. 3 is a diagram of a successive approximation analog-to-digital converter based on a dither signal according to an embodiment of the present invention.
FIG. 4 is a diagram of an implementation example of a successive approximation type analog-to-digital converter based on a dither signal according to an embodiment of the present invention.
FIG. 5 is a diagram of a successive approximation analog-to-digital converter based on a dither signal according to an embodiment of the present invention.
FIG. 6 is a diagram of an implementation example of a successive approximation type analog-to-digital converter based on a dither signal according to an embodiment of the present invention.
Fig. 7 is a circuit diagram of a 15-bit deep digital pseudo random signal generator (PRBS) implementation in an embodiment of the invention.
FIG. 8 is a diagram illustrating the relationship between the Spurious Free Dynamic Range (SFDR) and the added jitter signal according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a calibration method of a successive approximation analog-to-digital converter based on a dither signal according to an embodiment of the present invention.
FIG. 10 is a diagram illustrating a calibration method of a successive approximation analog-to-digital converter based on a dither signal according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the embodiments of the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element. In addition, the connection may be for either a fixing function or a circuit connection function.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the embodiments of the present invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be in any way limiting of the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless specifically limited otherwise.
Example 1
As shown in fig. 1, a successive approximation register analog-to-digital converter (SAR ADC) is a common architecture for medium to high resolution applications. The successive approximation analog-to-digital converter generally has the resolution of 8 bits to 16 bits, and has the characteristics of low power consumption, small size and the like. These features enable successive approximation analog-to-digital converters to find a wide range of applications, such as portable battery-powered instruments, pen input quantizers, industrial control and data signal collectors, and the like. Generally, the circuit consists of an input sample/hold circuit, a digital-analog converter, a comparator, a successive approximation logic circuit and a clock generation circuit. To implement the binary search algorithm, the N-bit register in the SAR control logic module is first set at the middle scale (i.e., 100.. 00, MSB set to 1). Thus, the output of the DAC (Vdac) is set to VREF/2, where VREF is the reference voltage for the ADC. Then, the comparator compares and judges whether Va of the sample hold is smaller or larger than Vdac. If Va is greater than Vdac, the comparator outputs a logic high level or 1 and the MSB of the N-bit register remains at 1. Conversely, if Va is less than Vdac, the comparator outputs a logic low level, MSB of the N-bit register clear 0. The SAR control logic then moves to the next bit (MSB-1) and sets that bit high for the next comparison. This process continues until the LSB is completed, the N-bit conversion is completed, and the conversion result is stored in a register and output. The conversion rate of the successive approximation type analog-to-digital converter is limited by the time delay of the comparator, the time delay of the SAR control logic module and the setup time of the DAC. For an N-bit successive approximation type analog-to-digital converter, the number of bits, precision and linearity of a DAC cannot be lower than that of the N-bit, so the precision of the successive approximation type analog-to-digital converter is mainly determined by the precision of the analog-to-digital converter (DAC).
As shown in fig. 2, an analog-to-digital converter based on a dither signal includes a core analog-to-digital converter, a dither digital-to-analog converter, and a random sequencer, assuming that the core analog-to-digital converter in the figure has limited linearity. Firstly, a random sequence generator generates a digital pseudorandom sequence, wherein the digital pseudorandom sequence is a digital signal; the digital pseudorandom sequence is converted into a corresponding analog pseudorandom signal through a dithering digital-to-analog converter, and the analog pseudorandom signal is superposed on an input signal, namely the dithering signal. The sum of the analog pseudorandom signal and the input signal serves as the input to the core ADC. Due to the addition of the analog pseudo-random signal, the input of the core ADC shows randomness in time, so that the selection process of devices (such as capacitors, resistors and MOS (metal oxide semiconductor) tubes) determining the ADC linearity in the core ADC is randomized, namely the mismatch of the devices is shaped in a first order, and the output spectrum of the core ADC shows that harmonic energy caused by the mismatch of the original devices is dispersed to noise energy of each frequency point of the whole signal bandwidth, so that the harmonic energy is reduced, the spurious-free dynamic range (SFDR) of the ADC is improved, and the linearity of the core ADC is effectively improved.
In order that the added analog pseudo-random signal does not degrade the accuracy (i.e., signal-to-noise ratio, SNR) of the core ADC, the digital pseudo-random sequence generated by the random sequence generator needs to be subtracted accordingly at the digital output of the core ADC, so as to obtain the digital output of the overall ADC.
The method for improving the linearity by adding the dither signal in the general case can improve the linearity of the ADC to a certain extent compared with the classical structure (the structure without adding the dither signal); however, an additional DAC is required to convert the digital dither signal into a corresponding analog dither signal, which increases hardware overhead.
As shown in fig. 3, the successive approximation type analog-to-digital converter based on a dither signal according to the present invention includes: the circuit comprises a sampling/holding circuit, a digital-analog converter, a comparator, a successive approximation logic circuit, a clock generation circuit and a digital pseudo-random signal generator; the analog input signal is connected to the sampling/holding circuit, the positive and negative input ends of the comparator are respectively connected with the digital-analog converter and the sampling/holding circuit, and the output end of the comparator is connected with the successive approximation logic circuit; the successive approximation logic circuit and the digital pseudo-random signal generator are connected to the input of an adder, and the output of the adder is connected with the digital-analog converter; the successive approximation logic circuit and the digital pseudorandom signal generator are connected to the input of a subtracter, and the output of the subtracter is a final output result; the clock generation circuit is respectively connected with the comparator and the successive approximation logic circuit.
As shown in fig. 4, an example of a successive approximation analog-to-digital converter based on a dither signal is implemented. For simplicity, a 6-bit SAR ADC is taken as an example, and assuming that b3 bits of the DAC introduce mismatch, in order to eliminate the mismatch of the capacitor DAC, a digital calibration technique of the DAC based on a jitter signal is added in fig. 4. In fig. 4, adding a digital dither signal from the digital input terminal of the capacitor DAC in the SAR ADC is equivalent to subtracting the corresponding analog dither signal from the input analog signal Vin terminal.
Compared with the general schematic diagram of fig. 2, the DAC digital calibration technique based on the dither signal according to the present invention can make full use of the DAC owned by the SAR ADC, and does not need to add an additional DAC to convert the digital dither signal into a corresponding analog dither signal, which is a great advantage of the successive approximation type analog-to-digital converter based on the dither signal according to the present invention.
Because the digital input end of the capacitor DAC is added with the random jitter signal, the overturning and using processes of the 6 capacitors of the capacitor DAC are randomized, which is equivalent to that the mismatch between the 6 capacitors of the capacitor DAC is subjected to first-order shaping, and harmonic energy generated by the mismatch is dispersed to noise energy of each frequency point of the whole signal bandwidth on a frequency spectrum, so that the linearity of the capacitor DAC and the whole SAR ADC is effectively improved, and SFDR and SNDR indexes are improved. Since the transfer function from the digital input of the capacitor DAC to the digital output of the entire SAR ADC is 1, in order to prevent the added dither signal from reducing the effective accuracy (SNR) of the entire SAR ADC, the same dither signal needs to be subtracted from the digital output of the SAR ADC, so as to obtain the true digital output of the SAR ADC.
The digital signal generated by the digital pseudo-random signal generator is simultaneously input with the input signal, and the addition and subtraction of the digital signal generated by the digital pseudo-random signal generator are carried out at the same time and at different positions, so that an additional memory is not needed for storing the digital signal generated by the digital pseudo-random signal generator at the previous moment, and the hardware expense is saved.
Due to the introduction of digital calibration of the DAC based on the jitter signal, the static mismatch of the capacitor DAC is eliminated, and the linearity index of the SARADC can be improved; meanwhile, the matching requirement of the capacitor DAC can be reduced, the capacitance value of the DAC is reduced, the establishing process of the DAC is accelerated, and therefore the dynamic error of the DAC is reduced.
As shown in fig. 5, the present invention further provides a successive approximation type analog-to-digital converter, further comprising a pre-comparator and a multiplier, wherein the input terminals of the pre-comparator are respectively connected to the reference voltage and the input voltage signal, the input terminals of the multiplier are respectively connected to the output terminal of the comparator and the digital pseudo-random signal generator, and the output terminal of the multiplier is connected to one input of the adder.
Because the random jitter signal is added to the digital input end of the DAC, the amplitude of the analog signal output by the DAC exceeds the amplitude range of the input signal of the SARADC, and the amplitude of the input signal of the comparator also exceeds the original amplitude. In order to enable the SAR ADC itself and the digital calibration technique of the DAC based on the dither signal to work properly under such a scenario, a conventional solution is to add redundancy, i.e. to increase the amplitude range of the input signal of the SAR ADC and simultaneously increase the amplitude range of the input signal of the comparator, and if necessary, even increase the number of comparators. The new analog-to-digital converter based on the jitter signal provided by the invention is added with a pre-comparator and a multiplier on the basis of the structures of the original sampling/holding circuit, a digital-to-analog converter, a comparator, a successive approximation logic circuit, a clock generation circuit and a digital pseudo-random signal generator.
Fig. 6 shows another example of a successive approximation type analog-to-digital converter based on a dither signal. Compared with the example graph in fig. 4, a pre-comparator is added in the scheme for judging the polarity of the analog input signal of the SAR ADC, and the polarity of the added digital random jitter signal is determined according to the judgment result.
On the basis of introducing digital random jitter signals, the pre-comparator is used for pre-judging, the precision of the added pre-comparator is not larger than that of the original comparator, the amplitude range of input signals and the comparator is not required to be increased, the integral performance index of the SAR ADC can be improved, and the circuit area and the power consumption are saved.
As shown in fig. 7, is a circuit diagram of a 15 bit deep digital pseudo random signal generator (PRBS) implementation. The circuit comprises at least 3D triggers and at least 1 exclusive-OR gate. The linear feedback shift register gives the output of the previous state and re-uses the linear function of that output as its input. The exclusive-or operation is the most common but bit linear function, and some bits of the register are exclusive-or operated to be used as input, and then all bits in the register are shifted integrally. For a linear feedback shift register with N D flip-flops, the number of cycles is 2^ N-1. The linear feedback shift register of fig. 5 has a depth of 15 bits, and by increasing the number of D flip-flops, the number of cycles of the digital pseudo random signal generator (PRBS) can be further increased, and the randomness of the output digital sequence can be further improved. The jitter signal is generated in a digital mode instead of an analog mode, so that the circuit structure is simpler.
Fig. 8 is a diagram showing the relationship between the Spurious Free Dynamic Range (SFDR) and the added jitter signal. The improvement of SFDR is greatest when the dither signal is close to the weight of the most significant bit, so the dither signal is added only at the MSB and not at other bits, which both maximizes performance improvement and greatly reduces hardware overhead.
As shown in fig. 9, the calibration method for a successive approximation type analog-to-digital converter includes the following steps.
S1: the input analog signal is sampled and kept stable by the sample/hold circuit;
s2: the output of the sampling/holding circuit is compared by the comparator, and the comparison result is transmitted to the successive approximation logic circuit;
s3: the digital signal generated by the digital pseudo-random signal generator and the digital signal generated by the successive approximation logic circuit are added to obtain a sum signal;
s4: the sum signal is transmitted to the digital-analog converter to obtain an analog signal;
s5: the comparator compares the analog signal generated by the digital-analog converter with the input analog signal to obtain the conversion result of the next bit, and then transmits the conversion result to the successive approximation logic circuit;
s6: repeating the steps S3 to S5 until all bit conversion is completed;
s7: the successive approximation logic circuit obtains a digital output result, and digital signals generated by the digital pseudo-random signal generator are subtracted from the digital output result to obtain a difference signal, namely the output result;
as shown in fig. 10, the calibration method for a successive approximation type analog-to-digital converter includes the following steps.
T1: the input analog signal is sampled and kept stable by the sample/hold circuit;
t2: the output of the sampling/holding circuit is compared by the comparator, and the comparison result is transmitted to the successive approximation logic circuit;
t3: comparing the analog input signal with the reference signal through the pre-comparator to obtain a pre-comparison output result;
t4: the pre-comparison output result is multiplied by the digital signal generated by the digital pseudo-random signal generator to obtain a product signal;
t5: adding the product signal and the digital signal generated by the successive approximation logic circuit to obtain a sum signal;
t6: the sum signal is transmitted to the digital-analog converter to obtain an analog signal;
t7: the comparator compares the analog signal generated by the digital-analog converter with the input analog signal to obtain the conversion result of the next bit, and then transmits the conversion result to the successive approximation logic circuit;
t8: repeating the steps from T5 to T7 until all bit conversions are completed;
t9: the successive approximation logic circuit obtains a digital output result, and subtracts the product signal from the digital output result to obtain a difference signal, which is the output result.
On the basis of fig. 10, in order to further reduce hardware cost and power consumption, since the comparison result of the highest bit can also determine the polarity of the input signal, the pre-comparator part circuit can be omitted, so that the step T3 is changed to: and obtaining a pre-comparison result according to the most significant bit comparison result of the comparator, wherein other steps are unchanged.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several equivalent substitutions or obvious modifications can be made without departing from the spirit of the invention, and all the properties or uses are considered to be within the scope of the invention.
Claims (10)
1. A successive approximation analog-to-digital converter, comprising: the circuit comprises a sampling/holding circuit, a digital-analog converter, a comparator, a successive approximation logic circuit, a clock generation circuit and a digital pseudo-random signal generator;
the analog input signal is connected to the sampling/holding circuit, the positive and negative input ends of the comparator are respectively connected with the digital-analog converter and the sampling/holding circuit, and the output end of the comparator is connected with the successive approximation logic circuit; the successive approximation logic circuit and the digital pseudo-random signal generator are connected to the input of an adder, and the output of the adder is connected with the digital-analog converter; the successive approximation logic circuit and the digital pseudorandom signal generator are connected to the input of a subtracter, and the output of the subtracter is a final output result;
the clock generation circuit is respectively connected with the comparator and the successive approximation logic circuit.
2. The successive approximation analog-to-digital converter of claim 1 wherein the digital signal generated by the digital pseudo-random signal generator is simultaneous with the input of the analog input signal.
3. The analog-to-digital converter of claim 1, wherein the addition and subtraction of the digital signals generated by the digital pseudo-random signal generator are at the same time and at different locations.
4. The successive approximation analog-to-digital converter of claim 1, wherein said digital pseudo-random signal generator is a linear feedback shift register comprised of at least three D flip-flops and at least one xor gate.
5. The successive approximation analog-to-digital converter of claim 1 wherein the digital signal generated by the digital pseudorandom signal generator has only one bit and is applied to the most significant bit.
6. The successive approximation analog-to-digital converter of claim 1, further comprising a pre-comparator and a multiplier, wherein inputs of said pre-comparator are respectively connected to a reference voltage and an input voltage signal, inputs of said multiplier are respectively connected to an output of said comparator and said digital pseudo-random signal generator, and an output of said multiplier is connected to an input of said adder.
7. The successive approximation analog-to-digital converter of claim 6, wherein the pre-comparator is implemented by a most significant bit comparison of a comparator.
8. A calibration method of a successive approximation type analog-to-digital converter is characterized by comprising the following steps:
s1: the input analog signal is sampled and kept stable by a sampling/holding circuit;
s2: the output of the sampling/holding circuit is compared by a comparator, and the comparison result is transmitted to a successive approximation logic circuit;
s3: adding a digital signal generated by a digital pseudo-random signal generator and a digital signal generated by the successive approximation logic circuit to obtain a sum signal;
s4: the sum signal is transmitted to a digital-analog converter to obtain an analog signal;
s5: the comparator compares the analog signal generated by the digital-analog converter with the input analog signal to obtain a conversion result of the next bit, and then transmits the conversion result to the successive approximation logic circuit;
s6: repeating the steps S3 to S5 until all bit conversion is completed;
s7: the successive approximation logic circuit obtains a digital output result, and subtracts a digital signal generated by the digital pseudo-random signal generator from the digital output result to obtain a difference signal, namely the output result.
9. A calibration method of a successive approximation type analog-to-digital converter is characterized by comprising the following steps:
t1: the input analog signal is sampled and kept stable by a sampling/holding circuit;
t2: the output of the sampling/holding circuit is compared by a comparator, and the comparison result is transmitted to a successive approximation logic circuit;
t3: the analog input signal and the reference signal are compared through the pre-comparator to obtain a pre-comparison output result;
t4: multiplying the pre-comparison output result by a digital signal generated by a digital pseudo-random signal generator to obtain a product signal;
t5: the product signal and a digital signal generated by the successive approximation logic circuit are added to obtain a sum signal;
t6: the sum signal is transmitted to a digital-analog converter to obtain an analog signal;
t7: the comparator compares the analog signal generated by the digital-analog converter with the input analog signal to obtain a conversion result of the next bit, and then transmits the conversion result to the successive approximation logic circuit;
t8: repeating the steps from T5 to T7 until all bit conversions are completed;
t9: the successive approximation logic circuit obtains a digital output result, and subtracts a product signal from the digital output result to obtain a difference signal, namely an output result.
10. The method of calibrating a successive approximation analog-to-digital converter according to claim 9, wherein the step T3 is: and obtaining a pre-comparison output result according to the most significant bit comparison result of the comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911242441.1A CN110880934B (en) | 2019-12-06 | 2019-12-06 | Successive approximation type analog-to-digital converter and calibration method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911242441.1A CN110880934B (en) | 2019-12-06 | 2019-12-06 | Successive approximation type analog-to-digital converter and calibration method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110880934A true CN110880934A (en) | 2020-03-13 |
| CN110880934B CN110880934B (en) | 2023-05-26 |
Family
ID=69730199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911242441.1A Active CN110880934B (en) | 2019-12-06 | 2019-12-06 | Successive approximation type analog-to-digital converter and calibration method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110880934B (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111478707A (en) * | 2020-04-14 | 2020-07-31 | 广东工业大学 | Random scrambling deterministic compressed sensing measurement device and method |
| CN111740740A (en) * | 2020-06-22 | 2020-10-02 | 同济大学 | Pipeline successive approximation analog-digital converter background gain calibration circuit and method |
| CN112104370A (en) * | 2020-09-25 | 2020-12-18 | 无锡英诺赛思科技有限公司 | High-precision analog-to-digital converter conversion speed improving circuit |
| CN112383311A (en) * | 2020-11-19 | 2021-02-19 | 珠海零边界集成电路有限公司 | Successive approximation type analog-digital converter and data conversion method thereof |
| CN112422130A (en) * | 2020-11-26 | 2021-02-26 | 重庆邮电大学 | Low-power-consumption Binary-Search ADC system based on full dynamic structure |
| CN112994699A (en) * | 2021-03-04 | 2021-06-18 | 北京大学（天津滨海）新一代信息技术研究院 | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method |
| CN113595550A (en) * | 2021-07-13 | 2021-11-02 | 上海交通大学 | Successive approximation analog-digital converter with digital calibration |
| CN113659984A (en) * | 2021-07-12 | 2021-11-16 | 清华大学深圳国际研究生院 | Capacitance mismatch calibration method and system for successive approximation type analog-to-digital converter |
| CN115016243A (en) * | 2022-05-12 | 2022-09-06 | 北京大学 | Method for enhancing linearity of random time-to-digital converter |
| CN115208403A (en) * | 2022-09-13 | 2022-10-18 | 杭州米芯微电子有限公司 | Successive approximation type ADC circuit, ADC converter and chip |
| CN116073829A (en) * | 2023-03-07 | 2023-05-05 | 南京航空航天大学 | LMS foreground calibration method and system of successive approximation type ADC |
| CN116366066A (en) * | 2021-12-27 | 2023-06-30 | 圣邦微电子（北京）股份有限公司 | Arithmetic circuit |
| CN116938250A (en) * | 2023-09-18 | 2023-10-24 | 成都芯盟微科技有限公司 | Successive difference comparison analog-to-digital conversion circuit and conversion method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103152049A (en) * | 2013-02-26 | 2013-06-12 | 上海宏力半导体制造有限公司 | Successive approximation register type ADC (analog-digital converter) |
| CN103888141A (en) * | 2014-04-09 | 2014-06-25 | 华为技术有限公司 | Assembly line successive approximation type analog-digital converter self-calibration method and device |
| CN106027050A (en) * | 2016-04-19 | 2016-10-12 | 灵芯微电子科技（苏州）有限公司 | Pipelined-successive approximation register analog-to-digital converter applying open-loop gain stage |
| US9985640B1 (en) * | 2016-12-23 | 2018-05-29 | Avnera Corporation | Programmable sequence controller for successive approximation register analog to digital converter |
| CN109981107A (en) * | 2017-12-05 | 2019-07-05 | 恩智浦有限公司 | Analog-digital converter, radar cell and the method for improving harmonic distortion performance |
-
2019
- 2019-12-06 CN CN201911242441.1A patent/CN110880934B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103152049A (en) * | 2013-02-26 | 2013-06-12 | 上海宏力半导体制造有限公司 | Successive approximation register type ADC (analog-digital converter) |
| CN103888141A (en) * | 2014-04-09 | 2014-06-25 | 华为技术有限公司 | Assembly line successive approximation type analog-digital converter self-calibration method and device |
| CN106027050A (en) * | 2016-04-19 | 2016-10-12 | 灵芯微电子科技（苏州）有限公司 | Pipelined-successive approximation register analog-to-digital converter applying open-loop gain stage |
| US9985640B1 (en) * | 2016-12-23 | 2018-05-29 | Avnera Corporation | Programmable sequence controller for successive approximation register analog to digital converter |
| CN109981107A (en) * | 2017-12-05 | 2019-07-05 | 恩智浦有限公司 | Analog-digital converter, radar cell and the method for improving harmonic distortion performance |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111478707A (en) * | 2020-04-14 | 2020-07-31 | 广东工业大学 | Random scrambling deterministic compressed sensing measurement device and method |
| CN111478707B (en) * | 2020-04-14 | 2023-05-05 | 广东工业大学 | Random scrambling certainty compressed sensing measurement device and method |
| CN111740740A (en) * | 2020-06-22 | 2020-10-02 | 同济大学 | Pipeline successive approximation analog-digital converter background gain calibration circuit and method |
| CN111740740B (en) * | 2020-06-22 | 2022-06-21 | 同济大学 | Pipeline successive approximation analog-digital converter background gain calibration circuit and method |
| CN112104370A (en) * | 2020-09-25 | 2020-12-18 | 无锡英诺赛思科技有限公司 | High-precision analog-to-digital converter conversion speed improving circuit |
| CN112104370B (en) * | 2020-09-25 | 2022-05-03 | 无锡英诺赛思科技有限公司 | High-precision analog-to-digital converter conversion speed improving circuit |
| CN112383311A (en) * | 2020-11-19 | 2021-02-19 | 珠海零边界集成电路有限公司 | Successive approximation type analog-digital converter and data conversion method thereof |
| CN112383311B (en) * | 2020-11-19 | 2024-06-07 | 珠海零边界集成电路有限公司 | Successive approximation type analog-digital converter and data conversion method thereof |
| CN112422130B (en) * | 2020-11-26 | 2022-07-01 | 重庆邮电大学 | Low-power-consumption Binary-Search ADC system based on full dynamic structure |
| CN112422130A (en) * | 2020-11-26 | 2021-02-26 | 重庆邮电大学 | Low-power-consumption Binary-Search ADC system based on full dynamic structure |
| CN112994699A (en) * | 2021-03-04 | 2021-06-18 | 北京大学（天津滨海）新一代信息技术研究院 | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method |
| CN113659984A (en) * | 2021-07-12 | 2021-11-16 | 清华大学深圳国际研究生院 | Capacitance mismatch calibration method and system for successive approximation type analog-to-digital converter |
| CN113659984B (en) * | 2021-07-12 | 2023-06-09 | 清华大学深圳国际研究生院 | Capacitance mismatch calibration method and system of successive approximation type analog-to-digital converter |
| CN113595550B (en) * | 2021-07-13 | 2023-07-25 | 上海交通大学 | Successive approximation analog-to-digital converter with digital calibration |
| CN113595550A (en) * | 2021-07-13 | 2021-11-02 | 上海交通大学 | Successive approximation analog-digital converter with digital calibration |
| CN116366066A (en) * | 2021-12-27 | 2023-06-30 | 圣邦微电子（北京）股份有限公司 | Arithmetic circuit |
| CN115016243A (en) * | 2022-05-12 | 2022-09-06 | 北京大学 | Method for enhancing linearity of random time-to-digital converter |
| CN115208403A (en) * | 2022-09-13 | 2022-10-18 | 杭州米芯微电子有限公司 | Successive approximation type ADC circuit, ADC converter and chip |
| CN115208403B (en) * | 2022-09-13 | 2022-12-27 | 杭州米芯微电子有限公司 | Successive approximation type ADC circuit, ADC converter and chip |
| CN116073829A (en) * | 2023-03-07 | 2023-05-05 | 南京航空航天大学 | LMS foreground calibration method and system of successive approximation type ADC |
| CN116938250A (en) * | 2023-09-18 | 2023-10-24 | 成都芯盟微科技有限公司 | Successive difference comparison analog-to-digital conversion circuit and conversion method |
| CN116938250B (en) * | 2023-09-18 | 2023-11-24 | 成都芯盟微科技有限公司 | Successive difference comparison analog-to-digital conversion circuit and conversion method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110880934B (en) | 2023-05-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110880934B (en) | Successive approximation type analog-to-digital converter and calibration method | |
| US6369744B1 (en) | Digitally self-calibrating circuit and method for pipeline ADC | |
| US7142138B2 (en) | Multi-step analog/digital converter and on-line calibration method thereof | |
| US8599059B1 (en) | Successive approximation register analog-digital converter and method for operating the same | |
| US7205921B1 (en) | Hybrid analog-to-digital converter | |
| US9148166B2 (en) | Adding predefined offset to coarse ADC residue output to SAR | |
| CN109150183B (en) | Metastable state detection-based capacitance mismatch calibration method for SAR-ADC | |
| EP1519491A1 (en) | Increasing the SNR of successive approximation type ADCs without compromising throughput performance substantially | |
| EP1614219B1 (en) | Comparator offset calibration for a/d converters | |
| Yousefi et al. | An energy-efficient DAC switching method for SAR ADCs | |
| EP3567720B1 (en) | Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage | |
| CN113659984B (en) | Capacitance mismatch calibration method and system of successive approximation type analog-to-digital converter | |
| Matsuura | Recent progress on CMOS successive approximation ADCs | |
| JP2015171087A (en) | Analog/digital conversion circuit | |
| Ahmadi et al. | Comparator power reduction in low-frequency SAR ADC using optimized vote allocation | |
| Li et al. | A 7b 2.6 mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration | |
| Liu et al. | An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters | |
| Murmann et al. | Digital domain measurement and cancellation of residue amplifier nonlinearity in pipelined ADCs | |
| Krishna et al. | VLSI DESIGN OF 12-BIT ADC WITH 1GSPS IN 180NM CMOS INTEGRATING WITH SAR AND TWO-STEP FLASH ADC. | |
| CN116155285A (en) | Digital-to-analog converter calibration method based on digital domain coding remapping | |
| Ha et al. | A 0.5-V, 1.47-$\mu\hbox {W} $40-kS/s 13-bit SAR ADC With Capacitor Error Compensation | |
| Samadpoor Rikan et al. | A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE | |
| US11711089B2 (en) | SAR ADC with alternating low and high precision comparators and uneven allocation of redundancy | |
| CN114553226A (en) | Calibration method and calibration system for analog-to-digital converter | |
| Valet et al. | Comparative study on pre-distortion/calibration methods for current-steering digital-to-analog converters |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |