CN114553226A - Calibration method and calibration system for analog-to-digital converter - Google Patents

Calibration method and calibration system for analog-to-digital converter Download PDF

Info

Publication number
CN114553226A
CN114553226A CN202011337674.2A CN202011337674A CN114553226A CN 114553226 A CN114553226 A CN 114553226A CN 202011337674 A CN202011337674 A CN 202011337674A CN 114553226 A CN114553226 A CN 114553226A
Authority
CN
China
Prior art keywords
adc
output code
calibrated
transfer function
weight
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011337674.2A
Other languages
Chinese (zh)
Inventor
许�鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Shenlian Microelectronics Technology Co ltd
Original Assignee
Hangzhou Shenlian Microelectronics Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Shenlian Microelectronics Technology Co ltd filed Critical Hangzhou Shenlian Microelectronics Technology Co ltd
Priority to CN202011337674.2A priority Critical patent/CN114553226A/en
Publication of CN114553226A publication Critical patent/CN114553226A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention discloses a calibration method and a calibration system of an analog-to-digital converter. The calibration method is used for inputting a sine wave signal to an ADC to be calibrated, then collecting a plurality of output code values of the ADC to be calibrated, obtaining a transfer function according to the statistical characteristics of the output code values, and finally obtaining the actual weight of the ADC to be calibrated based on the transfer function and a weight expression of the ADC to be calibrated, so that the purpose of high-precision analog-to-digital conversion is achieved. The calibration method of the embodiment of the invention has simple algorithm and is easy to implement.

Description

Calibration method and calibration system for analog-to-digital converter
Technical Field
The present invention relates to the field of semiconductor integrated circuit technology, and more particularly, to a calibration method and a calibration system for an analog-to-digital converter.
Background
Analog-to-Digital Converter (ADC) is a device capable of converting continuous Analog signals into discrete Digital signals that can be processed by a computer, is a key component of an interface between an Analog system and a Digital system, and has been widely used in the fields of radar, communication, measurement and control, medical treatment, instruments, images, audio, and the like for a long time. The rapid development of digital signal processing technology and communication industry has pushed the development of ADCs gradually towards high speed, high precision and low power consumption.
A Successive Approximation Analog-to-Digital Converter (sar ADC) continuously generates a new Analog voltage quantity to approximate to an originally input Analog signal through an internally integrated Digital-to-Analog Converter (DAC) array by using a binary search method, and finally, a Digital input corresponding to a DAC is used as an output of the ADC. The sar ADC has the advantages of medium speed, medium accuracy, low power consumption, low cost, etc. compared to other types of ADCs, and therefore has a wide application field.
The sar adc is mainly composed of a DAC array, successive approximation control logic and a latching comparator. The sar adc may be classified into a resistance division type, a current superposition type, a charge redistribution type, and the like according to a structure of a DAC array inside the sar adc. The DAC array has mismatch caused by uncertainty in the manufacturing process, so that the weight corresponding to each bit of ADC digital coding is influenced, system deviation or random deviation is caused, and the precision and the linearity of the SARADC are directly influenced.
Disclosure of Invention
In view of the above, the present invention provides a calibration method and a calibration system for an analog-to-digital converter, which can reduce the influence of weight mismatch on the linearity and the signal-to-noise ratio of the analog-to-digital converter.
According to an aspect of the present invention, there is provided a calibration method of an analog-to-digital converter, including: inputting a sine wave signal to an ADC to be calibrated; acquiring a plurality of output code values of the ADC to be calibrated, and obtaining a transfer function according to the plurality of output code values; and obtaining the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated.
Optionally, the obtaining a transfer function according to the plurality of output code values includes: obtaining a differential nonlinear error and an integral nonlinear error corresponding to each output code value; and constructing the transfer function from the plurality of output code values and the corresponding integrated nonlinear error for each output code value.
Optionally, the obtaining the differential nonlinear error and the integral nonlinear error corresponding to each output code value includes: and calculating by adopting a histogram method to obtain a differential nonlinear error and an integral nonlinear error corresponding to each output code value.
Optionally, the output code values are sequentially arranged from low to high as 0,1, 2, … …, 2N-1, N representing the number of bits of said ADC to be calibrated, N being largeAt an integer of zero, said deriving a transfer function from said plurality of output code values further comprises: a first normalization process is performed on the differential nonlinear error and the integral nonlinear error corresponding to the lowest and highest output code values of the plurality of output code values such that the differential nonlinear error and the integral nonlinear error corresponding to the lowest and highest output code values are equal to zero.
Optionally, the constructing the transfer function according to the plurality of output code values and the corresponding integrated nonlinear error of each output code value includes: summing each output code value of the plurality of output code values with a corresponding integrated nonlinear error to construct the transfer function.
Optionally, the transfer function is obtained by the following formula:
f(i)＝INL(i)+i
wherein i is 1, 2, … …, 2N-1, inl (i) represents the integrated nonlinear error for output code value i.
Optionally, each output code value i is composed of N-bit binary numbers, and the N-bit binary numbers are sequentially arranged from high order to low order as bN-1，bN-2，……，b1，b0The actual weight of each bit of the N-bit binary number is arranged as w from high bit to low bit in sequenceN-1，wN-2，……，w1，w0The weight expression is obtained by the following formula:
Figure BDA0002797737500000021
wherein, bN-1，bN-2，……，b1，b0Each bit of the binary number, w, representing a corresponding output code value i, respectivelyN-1，wN-2，……，w1，w0Representing the actual weight of each bit separately.
Optionally, the obtaining the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated includes: and enabling the transfer function and the weight expression to be equal, and performing matrix operation solving on the expression to obtain the actual weight of the ADC to be calibrated.
Optionally, the obtaining the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated further includes: performing a second normalization process on the weight expression so that an actual weight w of the lowest bit in the N-bit binary number0＝1。
Optionally, the calibration method is implemented by a chip internal logic device and/or by a chip external software.
Optionally, the calibration method further includes: and writing the actual weight into a weight register of the ADC to be calibrated so as to finish calibration.
According to another aspect of the present invention, there is provided a calibration system for an analog-to-digital converter, which is implemented based on the above calibration method, and includes: the signal source is used for providing a sine wave signal to the ADC to be calibrated; the acquisition module acquires a plurality of output code values of the ADC to be calibrated; the calibration module is used for obtaining a transfer function according to the output code values and obtaining the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated; and the control module is used for writing the actual weight into a weight register of the ADC to be calibrated so as to finish calibration.
The calibration method and the calibration system of the analog-to-digital converter of the embodiment of the invention input a sine wave signal to the ADC to be calibrated, then obtain a transfer function according to the statistical characteristics of a plurality of output code values after the ADC to be calibrated is converted, and calculate the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated, so that the purpose of high-precision analog-to-digital conversion is achieved. The calibration method of the embodiment of the invention has simple algorithm and easy implementation, and the calibration process can be carried out outside the chip without the design and realization of additional on-chip circuits, thereby saving the circuit area and reducing the manufacturing cost. In addition, the transfer function in the calibration method is obtained through a large number of sampling points, the noise interference is avoided, and the calibration precision is higher. The calibration method and the calibration system are mainly used for high-precision SARADC, and particularly used for SARADC with more than 12 bits.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a successive approximation analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 shows a schematic diagram of a calibration system according to a first embodiment of the invention;
FIG. 3 shows a schematic flow chart of a calibration method according to a second embodiment of the invention;
fig. 4a and 4b show schematic diagrams of sine wave spectrum comparison of ADCs before and after calibration, respectively.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected" or "coupled" to another element, or being "connected" or "coupled" between two nodes, it may be directly coupled or connected to the other element or intervening elements may also be present, and the connection or coupling between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Fig. 1 shows a schematic structure of a conventional successive approximation type analog-to-digital converter. As shown in fig. 1, the sar adc100 includes a sample-and-hold circuit 110, a comparator 120, a logic control circuit 130, and a digital-to-analog converter 140. The sample-and-hold circuit 110 samples and holds the analog input signal according to the sampling clock and provides the sampled and held analog input signal to the comparator 120, the comparator 120 compares the analog input signal with the reference voltage generated by the digital-to-analog converter 140, and the logic control circuit 130 generates a logic control signal according to the comparison result of the comparator 120, wherein the logic control signal is used for feedback controlling the digital-to-analog converter 140 to generate a new reference voltage to approximate the analog input signal until the reference voltage is approximately equal to the analog input signal. The logic control circuit 130 is configured to perform switching control on an array in the digital-to-analog converter 140, and obtain an original code value according to a comparison result of the comparator 120, where the original code value is calibrated by a correct weight to obtain a final correct code value. The calibration method provided by the embodiment of the invention mainly completes calibration through the weight register in the trimming logic control circuit 130.
In the embodiment of the present invention, the digital-to-analog converter 140 is selected from a capacitive digital-to-analog converter in a digital CMOS process, and the capacitor array thereof should have N capacitors, where N is greater than 12, for example. For an N-bit digital-to-analog converter, the capacitors in the capacitor array are sequentially arranged as C from high order to low orderN-1，CN-2，……，C0The capacitance value ratio between the capacitors satisfies the binary weight, i.e. the lowest order capacitor is a unit capacitance value 1C, the second lowest order capacitor is a capacitance value 2C of twice size, and so on, the highest order capacitor 230 is 2N-1C. The capacitive digital-to-analog converter is specifically realized by controlling the conducting direction of a bottom plate switch of a capacitor corresponding to the weight according to digital input, so that analog output corresponding to the digital input is generated on a top plate of a capacitor array.
At present, due to the deviation of the integrated circuit manufacturing process, random mismatch often occurs between capacitors in a capacitor array, so that a certain non-linear error exists in the ADC. The nonlinearity is mainly reflected in the fact that after a sine wave signal is input to an ADC, a certain degree of harmonic waves exist in sine wave digital codes converted by the ADC.
It will be appreciated by those skilled in the art that the calibration method of the present invention can be applied to, but is not limited to, resistive voltage division type sar adc, current superposition type sar adc, charge redistribution type sar adc, etc.
Fig. 2 shows a schematic structural diagram of a calibration system according to a first embodiment of the present invention. The ADC100 to be calibrated is implemented, for example, by sar ADC shown in fig. 1.
As shown in fig. 2, the calibration system 200 includes an acquisition module 210, a control module 220, and a calibration module 230. After a sine wave signal is input to the ADC100 to be calibrated, the collecting module 210 is mainly used for collecting an output code value of the ADC to be calibrated during the conversion of the ADC to be calibrated, and providing the output code value to the calibrating module 230. The calibration module 230 calculates a transfer function according to the received output code values, obtains an actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated 100, and provides the actual weight to the control module 220. The control module 220 is used to configure the ADC internal register and configure its operating mode, and is used to write the actual weight obtained by the calibration module 230 into the weight register inside the ADC100 to be calibrated, so as to complete the calibration process.
In this embodiment, the calibration system 200 further includes a signal source for outputting a sine wave signal to the ADC100 to be calibrated, where the frequency of the sine wave signal and the sampling frequency of the ADC to be calibrated satisfy the relationship of coherent sampling, and the amplitude of the sine wave signal is greater than the maximum measurement range of the ADC100 to be calibrated.
Fig. 3 shows a schematic flow chart of a calibration method according to a second embodiment of the invention. The calibration method is for example implemented by hardware inside the chip and/or by software outside the chip. For example, the calibration method may be implemented by the calibration system shown in fig. 2 to implement calibration of the ADC100 to be calibrated. As shown in fig. 3, the calibration method includes steps S101-S104.
In step S101, a sine wave signal is input to the ADC to be calibrated. For example, a sine wave signal may be input to the ADC to be calibrated through the signal source, the frequency of the sine wave signal and the sampling frequency of the ADC to be calibrated satisfy the relationship of coherent sampling, and the amplitude of the sine wave signal is greater than the maximum range of the ADC100 to be calibrated.
In step S102, a plurality of output code values of the ADC to be calibrated are collected, and a transfer function is obtained according to the plurality of output code values.
For the ADC to be calibrated with N bits, the output code value obtained by converting the ADC to be calibrated 100 is 2 in totalNAre arranged in a sequence from low to high as 0,1, 2, … …, 2N-1, N representing the number of bits of the ADC to be calibrated, N being an integer greater than zero. Step S102 specifically includes obtaining a Differential nonlinear error (DNL) and an Integral nonlinear error (INL) corresponding to each output code value, where DNL (i) is the Differential nonlinear error of the corresponding output code value i, and INL (i) is the corresponding output code value i (i ═ 1, 2, … …, 2)N-1) integral non-linearity error. The integrated nonlinear error and the differential nonlinear error corresponding to the lowest and highest of the plurality of output code values are then normalized so that the integrated nonlinear error and the differential nonlinear error corresponding to the lowest and highest output code values are equal to zero. And finally, constructing the transfer function according to the plurality of normalized output code values and the integral nonlinear error corresponding to each output code value.
Further, the method for obtaining the differential nonlinear error and the integral nonlinear error corresponding to each output code value in step S102 includes, but is not limited to, a voltage dithering method, a code averaging method, or a histogram method, preferably a histogram method.
Further, the transfer function is obtained by the following formula:
f(i)＝INL(i)+i
wherein i is 1, 2, … …, 2N-1, INL (i) represents the integrated nonlinear error for output code value i, f (i) represents the quasi-phase for output code value iAnd (4) determining the value.
In step S103, an actual weight of the ADC to be calibrated is obtained based on the transfer function and the weight expression of the ADC to be calibrated.
Further, step S103 specifically includes making the transfer function and the weight expression equal, and performing matrix operation on the equation to solve, so as to obtain the actual weight of the ADC to be calibrated.
Wherein each output code value i is composed of N-bit binary numbers which are sequentially arranged from high bit to low bit as bN-1，bN-2，……，b1，b0The actual weight of each bit of the N-bit binary number is arranged as w from high bit to low bit in sequenceN-1，wN-2，……，w1，w0The weight expression is obtained by the following formula:
Figure BDA0002797737500000071
wherein, bN-1，bN-2，……，b1，b0Each bit of the binary number, w, representing a corresponding output code value i, respectivelyN-1，wN-2，……，w1，w0Representing the actual weight of each bit separately.
The above weight expressions g (i) are then normalized so that the actual weight w of the lowest bit of the N-bit binary number is0By making the transfer function f (i) equal to g (i), the equation can be obtained:
Figure BDA0002797737500000072
wherein, bi,jCorresponding to the output code value i (i ═ 1, 2, … …, 2)N-1) of N-bit binary numbers, wherein the j-th bit (j ═ 0,1, 2, … …, N-1) is solved by matrix operation on the above formula to obtain wN-1，wN-2，……，w1Value of (a), in combination with w0The actual weight for each bit of the ADC to be calibrated can be obtained as 1. The equation number of the matrix expression is 2N-1, the unknowns are N-1, and INL therein is obtained by a large number of sampling points, so that the interference of noise can be reduced and more accurate weight can be obtained.
In step S104, the actual weight is written into the weight register of the ADC to be calibrated to complete calibration, and the original binary code obtained by analog-to-digital conversion is calibrated by weighting and summing with the correct weight in the weight register to obtain an accurate output code value.
Fig. 4a and 4b show schematic diagrams of sine wave spectrum comparison of ADCs before and after calibration, respectively. In fig. 4a and 4b, SNR (Signal Noise Ratio) represents the Ratio Of the output Signal Of the ADC to Noise, SNDR (Signal Noise Distortion Ratio) represents the Ratio Of the output Signal Of the ADC to the sum Of Noise and Harmonic Distortion energy, SFDR (spread free Dynamic Range) represents the Ratio Of the root mean square value Of the output spectrum fundamental wave Of the ADC to the root mean square value Of the next largest component, the larger the values Of SNR, SNDR and SFDR, THD (Total Harmonic Distortion) represents the Ratio Of the root mean square value Of all harmonics to the root mean square value Of the fundamental wave Signal, ENOB (Effective Number Bits) represents the highest Effective Number Of Bits Of precision that the ADC can achieve, and numbers 2 to 10 represent the Harmonic order Of harmonics in the output Signal, respectively. As shown in FIG. 4a, the effective number of bits (ENOB) of the ADC before calibration is 10.08bits, the signal-to-noise ratio (SNR) is 64dB, the Spurious Free Dynamic Range (SFDR) is 71.25dB, and the Total Harmonic Distortion (THD) is-67.61 dB. As shown in fig. 4b, the Effective Number (ENOB) of the ADC after calibration by the calibration method according to the embodiment of the present invention is 11.22bits, the signal-to-noise ratio (SNR) is 69.8dB, the Spurious Free Dynamic Range (SFDR) is 81.27dB, and the Total Harmonic Distortion (THD) is-78.95 dB, and it can be seen that the effective number, the signal-to-noise ratio, and the spurious free dynamic range of the ADC after calibration by the calibration method according to the embodiment of the present invention are all significantly increased, the total harmonic distortion is significantly reduced, the signal harmonic component is significantly suppressed, and the performance of the ADC is significantly improved.
In summary, the calibration method and the calibration system for the analog-to-digital converter according to the embodiments of the present invention input a sine wave signal to the ADC to be calibrated, then obtain a transfer function according to the statistical characteristics of the plurality of output code values after the ADC to be calibrated is converted, and calculate the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated, so that the purpose of high-precision analog-to-digital conversion is achieved. The calibration method of the embodiment of the invention has simple algorithm and easy implementation, and the calibration process can be carried out outside the chip without the design and realization of additional on-chip circuits, thereby saving the circuit area and reducing the manufacturing cost. In addition, the transfer function in the calibration method is obtained through a large number of sampling points, the noise interference is avoided, and the calibration precision is higher. The calibration method and the calibration system are mainly used for high-precision SARADC, and particularly used for SARADC with more than 12 bits.
It will be understood by those of ordinary skill in the art that the words "during", "when" and "when … …" as used herein in relation to the operation of a circuit are not strict terms referring to actions occurring immediately upon initiation of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between them and the reactive action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (12)

1. A method of calibrating an analog-to-digital converter, comprising:
inputting a sine wave signal to an ADC to be calibrated;
collecting a plurality of output code values of the ADC to be calibrated, and obtaining a transfer function according to the output code values; and
and obtaining the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated.
2. The calibration method of claim 1, wherein said deriving a transfer function from said plurality of output code values comprises:
obtaining a differential nonlinear error and an integral nonlinear error corresponding to each output code value; and
and constructing the transfer function according to the plurality of output code values and the integral nonlinear error corresponding to each output code value.
3. The calibration method of claim 2, wherein said obtaining the differential nonlinear error and the integral nonlinear error for each output code value comprises:
and calculating by adopting a histogram method to obtain a differential nonlinear error and an integral nonlinear error corresponding to each output code value.
4. The calibration method of claim 2, wherein the plurality of output code values are arranged in a low-to-high order as 0,1, 2, … …, 2N-1, N representing the number of bits of the ADC to be calibrated, N being an integer greater than zero, said deriving a transfer function from the plurality of output code values further comprising:
a first normalization process is performed on the differential nonlinear error and the integral nonlinear error corresponding to the lowest and highest output code values of the plurality of output code values such that the differential nonlinear error and the integral nonlinear error corresponding to the lowest and highest output code values are equal to zero.
5. The calibration method of claim 4, wherein said constructing the transfer function from the plurality of output code values and the corresponding integrated nonlinear error for each output code value comprises:
summing each output code value of the plurality of output code values with a corresponding integrated nonlinear error to construct the transfer function.
6. The calibration method of claim 5, wherein the transfer function is obtained by the following equation:
f(i)＝INL(i)+i
wherein i is 1, 2, … …, 2N-1, inl (i) represents the integrated nonlinear error for output code value i.
7. The calibration method of claim 6, wherein each output code value i consists of an N-bit binary number consisting ofHigh order to low orderN-1，bN-2，……，b1，b0The actual weight of each bit of the N-bit binary number is arranged as w from high bit to low bit in sequenceN-1，wN-2，……，w1，w0The weight expression is obtained by the following formula:
Figure FDA0002797737490000021
wherein, bN-1，bN-2，……，b1，b0Each bit of the binary number, w, representing a corresponding output code value i, respectivelyN-1，wN-2，……，w1，w0Representing the actual weight of each bit separately.
8. The calibration method according to claim 7, wherein the deriving the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated comprises:
and enabling the transfer function and the weight expression to be equal, and performing matrix operation solving on the expression to obtain the actual weight of the ADC to be calibrated.
9. The calibration method according to claim 8, wherein the deriving the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated further comprises:
performing a second normalization process on the weight expression so that an actual weight w of the lowest bit in the N-bit binary number0＝1。
10. The calibration method of claim 1, wherein the calibration method is implemented by an on-chip logic device and/or by an off-chip software.
11. The calibration method of claim 10, further comprising:
and writing the actual weight into a weight register of the ADC to be calibrated so as to finish calibration.
12. A calibration system for an analog-to-digital converter based on the calibration method of any one of claims 1 to 11, comprising:
the signal source is used for providing a sine wave signal to the ADC to be calibrated;
the acquisition module acquires a plurality of output code values of the ADC to be calibrated;
the calibration module is used for obtaining a transfer function according to the output code values and obtaining the actual weight of the ADC to be calibrated based on the transfer function and the weight expression of the ADC to be calibrated; and
and the control module is used for writing the actual weight into a weight register of the ADC to be calibrated so as to finish calibration.
CN202011337674.2A 2020-11-25 2020-11-25 Calibration method and calibration system for analog-to-digital converter Pending CN114553226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011337674.2A CN114553226A (en) 2020-11-25 2020-11-25 Calibration method and calibration system for analog-to-digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011337674.2A CN114553226A (en) 2020-11-25 2020-11-25 Calibration method and calibration system for analog-to-digital converter

Publications (1)

Publication Number Publication Date
CN114553226A true CN114553226A (en) 2022-05-27

Family

ID=81660538

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011337674.2A Pending CN114553226A (en) 2020-11-25 2020-11-25 Calibration method and calibration system for analog-to-digital converter

Country Status (1)

Country Link
CN (1) CN114553226A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116318142A (en) * 2023-02-08 2023-06-23 北京士模微电子有限责任公司 Analog-to-digital converter calibration method and analog-to-digital converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116318142A (en) * 2023-02-08 2023-06-23 北京士模微电子有限责任公司 Analog-to-digital converter calibration method and analog-to-digital converter
CN116318142B (en) * 2023-02-08 2024-05-03 北京士模微电子有限责任公司 Analog-to-digital converter calibration method and analog-to-digital converter

Similar Documents

Publication Publication Date Title
CN109347477B (en) Successive approximation type analog-to-digital converter weight calibration method
CN110086468B (en) Weight calibration method of non-binary successive approximation type analog-to-digital converter
Chen et al. A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu {\hbox {m}} $ CMOS
TWI467924B (en) Successive approximation register analog to digital converter and conversion method thereof
CN102045067B (en) Conversion and calibration algorithm for improving output signal-to-noise ratio of successive approximation (SAR) analog-to-digital converter (ADC) and ADC
CN109150183B (en) Metastable state detection-based capacitance mismatch calibration method for SAR-ADC
CN110880934A (en) Successive approximation type analog-to-digital converter and calibration method
CN109361392B (en) Successive approximation type analog-to-digital converter and weight calibration method thereof
CN111934688A (en) Successive approximation type analog-to-digital converter and method
CN107579740B (en) Method for improving output precision of pipeline analog-to-digital converter and analog-to-digital converter
US20230198535A1 (en) Calibration method of capacitor array type successive approximation register analog-to-digital converter
Fan et al. A 12-bit self-calibrating SAR ADC achieving a Nyquist 90.4-dB SFDR
CN110768671B (en) Off-chip calibration method and system for successive approximation type analog-to-digital converter
Yuan et al. An interpolation-based calibration architecture for pipeline ADC with nonlinear error
CN114050827A (en) Digital calibration method applied to capacitance three-section successive approximation type analog-to-digital converter
CN114553226A (en) Calibration method and calibration system for analog-to-digital converter
Liu et al. An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters
Waho Non-binary successive approximation analog-to-digital converters: A survey
CN114024550B (en) Analog-to-digital converter and automatic power distribution equipment
TWI745977B (en) Analog digital converting system and method with offset and bit-weighting correction mechanism
KR101586407B1 (en) Method for Calibrating Capacitor Mismatch in SAR ADC
Li et al. An Ultra-fast ADC Linearity Test and Calibration Method
CN207427126U (en) A kind of circuit for improving analog-digital converter conversion speed
Lee et al. Single-bin DFT-based digital calibration technique for CDAC in SAR ADCs
Sumanen et al. A digital self-calibration method for pipeline A/D converters

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination