CN110828564A - 具有半导体性栅极的场效应晶体管 - Google Patents

具有半导体性栅极的场效应晶体管 Download PDF

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CN110828564A
CN110828564A CN201910730782.7A CN201910730782A CN110828564A CN 110828564 A CN110828564 A CN 110828564A CN 201910730782 A CN201910730782 A CN 201910730782A CN 110828564 A CN110828564 A CN 110828564A
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layer
gate
substrate
channel
semiconducting
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CN110828564B (zh
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陈敬
钱庆凯
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Hong Kong University of Science and Technology HKUST
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Hong Kong University of Science and Technology HKUST
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Abstract

提供了一种场效应晶体管，包括：衬底；源极层，其位于所述衬底上；漏极层，其位于所述衬底上；沟道层，其电连接所述源极层和所述漏极层；栅极介电层，其位于所述沟道层的远离所述衬底的一侧；半导体性栅极层，其位于所述栅极介电层的远离所述沟道层的一侧；栅电极，其与所述半导体性栅极层电连接，所述栅电极在所述衬底上的正投影在所述沟道层在所述衬底上的正投影之外。所述半导体性栅极层具有与所述沟道层在场效应晶体管导通状态下的导电沟道相同的载流子，并且所述半导体性栅极层的厚度和掺杂度设置为使得在向所述栅电极施加的电压大于预定电压时所述半导体性栅极被耗尽，同时所述沟道层的沟道完全导通。

Description

具有半导体性栅极的场效应晶体管
技术领域
本发明涉及半导体技术领域，尤其涉及具有半导体性栅极的场效应晶体管。
背景技术
场效应晶体管(FET)作为电压驱动器件，是现代半导体技术(例如CMOS、TFT、复合半导体HEMT等)的核心。它具有输入阻抗大、栅极控制和沟道电流之间隔离良好的优点，并已经支持大范围的现有和新兴应用。例如，低功耗FET用于高速计算和物联网(IoT)的逻辑和模拟IC。特别是，互补金属氧化物半导体(CMOS)FET由于其静态功耗低，已成为超大规模集成电路(VLSI)的基础。除了低功率FET之外，功率FET是FET的另一个重要分支。功率FET包括基于宽禁带半导体(即GaN或SiC)的MISFET/MOSFET或HEMT。这些功率器件可以在高电压和高温下以高速和大电流工作。它们在能量转换和电源方面具有广泛的应用，是建设现代节能型社会的重要组成部分。
尽管具有上述优点和广泛的应用，但电压驱动的FET具有易受过载栅极电压影响(特别是在正向栅极偏压下)的缺点。在图1(a)中示意性地示出了常规FET的一般结构。如图1(a)所示，FET 10包括源极层11、漏极层12、沟道层13、栅极介电层14和栅极层15。栅极层15通常由金属或厚的重掺杂的多晶硅制成。栅极介电层14包括一个或多个绝缘层、或者一个或多个半导体层，以提供栅极层15和沟道层13之间的电容耦合。当向栅极层15施加大电压时，可以向栅极介电层14上施加大电场。结果，栅极介电层14将经历击穿或导致阈值电压不稳定。虽然功率FET设计用于承受较大的漏极偏压，但它们同样容易受到正向栅极过压的影响。为了实现具有良好栅极稳健性的FET，栅极过压保护不仅对于防止栅极介电击穿，还对于提高器件可靠性和阈值电压稳定性都至关重要。长期以来已经为场效应晶体管开发了各种栅极过压保护方案。这些保护方案可以分为两类：电流限制和电压限制，例如如图1(b)所示。所有这些解决方案都需要外部***组件，诸如自举FET、齐纳二极管等。然而，这些额外的组件不仅会由于栅极电容或栅极电阻的增加而降低器件性能，还会带来额外的困难，并浪费用于单片集成的器件区域。
发明内容
对于现有技术中的FET，金属或重掺杂多晶硅用作导电栅极(CG)，其具有非常高的载流子密度。例如，薄至10nm的Ni薄膜至少具有约1.8×1017cm-2的载流子密度，这远远大于沟道已被视为完全导通时有源沟道的薄片载流子密度(～1×1013cm-2)。由于导电栅极的极高载流子密度，可以通过金属/多晶硅栅极在栅极介电层上施加过高的栅极偏压而没有任何限制。在本发明中，代替使用基于金属或重掺杂多晶硅的传统导电栅极，公开了一种用于FET的基于适度掺杂半导体薄层的半导体性栅极(SG)。与现有技术中的金属或多晶硅栅极相反，可以通过栅极电场有效地调节SG的导电性，并且大的栅极偏压将耗尽SG并使SG与下面的介电层和沟道层去耦。结果，SG能够为FET提供固有的过压保护，而不需要任何额外的***电路或元件，并且可以实现正向和反向栅极电压的抗扰性。
根据本公开的实施例，提供了一种场效应晶体管，包括：衬底；源极层，其位于所述衬底上；漏极层，其位于所述衬底上；沟道层，其电连接所述源极层和所述漏极层；栅极介电层，其位于所述沟道层的远离所述衬底的一侧；半导体性栅极层，其位于所述栅极介电层的远离所述沟道层的一侧；栅电极，其与所述半导体性栅极层电连接，所述栅电极在所述衬底上的正投影在所述沟道层在所述衬底上的正投影之外。即，可以将场效应晶体管构造为顶栅极器件。或者，该场效应晶体管包括：衬底；半导体性栅极层，其位于所述衬底上；栅电极，其位于所述衬底上并与所述半导体性栅极层电连接；栅极介电层，其位于所述半导体性栅极层的远离所述衬底的一侧；源极层；漏极层；沟道层，其位于所述栅极介电层的远离所述衬底的一侧并且电连接所述源极层和所述漏极层，所述沟道层在所述衬底上的正投影在所述栅电极在所述衬底上的正投影之外。即，可以将场效应晶体管构造为背栅极器件。在上述的顶栅极和背栅极器件中，所述半导体性栅极层具有与所述沟道层在场效应晶体管导通状态下的导电沟道相同类型的载流子，并且所述半导体性栅极层的厚度和掺杂度设置为使得在向所述栅电极施加的电压大于预定电压时所述半导体性栅极被耗尽，同时所述沟道层的沟道完全导通。
根据本公开的实施例，施加在所述栅电极上的电压间接地通过所述半导体性栅极层影响所述沟道层的导电性。
根据本公开的实施例，所述半导体性栅极层的材料包括Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷或CNT。
根据本公开的实施例，所述场效应晶体管还包括位于所述半导体性栅极层的远离所述衬底的一侧的第一半导体层，其中，所述半导体性栅极层的载流子类型与所述第一半导体层的载流子类型相反，所述半导体性栅极层和所述第一半导体层均与所述栅电极连接。
根据本公开的实施例，所述半导体性栅极层沿平行于所述衬底的方向延伸超出所述沟道层。
根据本公开的实施例，所述场效应晶体管还包括导电栅极层，其中，所述导电栅极层位于所述栅极介电层的远离所述沟道层的一侧并且通过所述半导体性栅极层电连接至所述栅电极。
根据本公开的实施例，所述半导体性栅极层沿垂直于所述衬底的方向覆盖所述沟道层的一部分，所述导电栅极层沿垂直于所述衬底的方向覆盖所述沟道层的另一部分。
根据本公开的实施例，所述场效应晶体管还包括第二半导体层，所述第二半导体层与所述源极层连接并且与所述沟道层间隔开，所述半导体性栅极层沿垂直于所述衬底的方向覆盖所述第二半导体层，所述导电栅极层沿垂直于所述衬底的方向覆盖所述沟道层。
根据本公开的实施例，所述沟道层包括在平面图中观察时朝向所述栅电极且位于所述源极层和所述漏极层之间的区域之外的突出部分，所述半导体性栅极层在平面图中观察时位于所述源极层和所述漏极层之间的区域之外并且与所述突出部分至少部分重叠。
根据本公开的实施例，所述场效应晶体管还包括与所述源极层连接的第三半导体层，其中，在平面图中观察时，所述第三半导体层在所述源极层和所述漏极层之间的区域之外并且与所述沟道层间隔开，所述半导体性栅极层位于所述源极层和所述漏极层之间的区域之外并且与所述第三半导体层至少部分重叠。
根据本公开的实施例，所述的场效应晶体管，其中，所述沟道层的材料包括Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷或CNT。
根据本公开的实施例，所述栅电极的材料包括金属，重掺杂的Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷或CNT和其他的半导体。
根据本公开的实施例，所述导电栅极层的材料包括金属，重掺杂的Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷或CNT和其他的半导体。
还提供了一种场效应晶体管，包括：衬底；源极层，其位于所述衬底上；漏极层，其位于所述衬底上；沟道层，其电连接所述源极层和所述漏极层；半导体性栅极层，其在所述衬底上的正投影在所述沟道层在所述衬底上的正投影之外；第一栅极介电层，其位于所述沟道层的远离所述衬底的一侧；第二栅极介电层，其位于所述半导体性栅极层的远离所述衬底的一侧；导电耦合层，其位于所述第一栅极介电层和所述第二栅极介电层的远离所述衬底的一侧；以及栅电极，其电连接所述半导体性栅极层，所述栅电极在所述衬底上的正投影在所述沟道层在所述衬底上的正投影之外。所述半导体性栅极层具有与所述沟道层在场效应晶体管导通状态下的导电沟道相同的载流子，并且所述半导体性栅极层的厚度和掺杂度设置为使得在向所述栅电极施加的电压大于预定电压时所述半导体性栅极被耗尽，同时所述沟道层的沟道完全导通。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1(a)示出了常规场效应晶体管的一般结构。
图1(b)示出了用于保护场效应晶体管的典型技术。
图2(a)是根据本发明的第一实施例的场效应晶体管的侧视图。
图2(b)是根据本发明的第一实施例的场效应晶体管的顶视图。
图2(c)是沿图2(b)中的虚线截取的场效应晶体管的剖视图。
图3(a)是根据本发明的第二实施例的场效应晶体管的顶视图。
图3(b)是沿图3(a)中的虚线截取的场效应晶体管的剖视图。
图4(a)是根据本发明的第三实施例的场效应晶体管的顶视图。
图4(b)是沿图4(a)中的虚线截取的场效应晶体管的剖视图。
图5(a)是根据本发明的第四实施例的场效应晶体管的顶视图。
图5(b)是沿图5(a)中的虚线截取的场效应晶体管的剖视图。
图6(a)是根据本发明的第五实施例的场效应晶体管的顶视图。
图6(b)是沿图6(a)中的虚线截取的场效应晶体管的剖视图。
图7(a)是根据本发明的第六实施例的场效应晶体管的顶视图。
图7(b)是沿图7(a)中的虚线截取的场效应晶体管的剖视图。
图8(a)是根据本发明的第一实施例的场效应晶体管的第一示例的侧视图。
图8(b)是图8(a)中的场效应晶体管的顶视图。
图8(c)是沿图8(b)中的虚线截取的场效应晶体管的剖视图。
图9(a)是根据本发明的第一实施例的场效应晶体管的第二示例的侧视图。
图9(b)是图9(a)中的场效应晶体管的顶视图。
图9(c)是沿图9(b)中的虚线截取的场效应晶体管的剖视图。
图10是根据本发明的第一实施例的场效应晶体管的第三示例的侧视图。
图11(a)是根据本发明的第一实施例的场效应晶体管的第四示例的侧视图。
图11(b)是根据本发明的第一实施例的场效应晶体管的第四示例的顶视图。
图12(a)示出了沿以单层MoS2作为半导体性栅极的AlGaN/GaN HEMT的栅极宽度方向的模拟电子密度分布。
图12(b)示出了沿以单层MoS2作为半导体性栅极的AlGaN/GaN HEMT的栅极宽度方向的模拟电位分布。
图13(a)示出了以Ni/Au作为栅极的AlGaN/GaN HEMT的转移曲线和栅极泄漏。
图13(b)示出了以单层MoS2作为半导体性栅极的AlGaN/GaNHEMT的转移曲线和栅极泄漏。
图14(a)示出了以Ni/Au作为栅极的AlGaN/GaN HEMT的输出特性。
图14(b)示出了以单层MoS2作为半导体性栅极的AlGaN/GaNHEMT的输出特性。
图15(a)比较了具有Ni/Au金属栅极的AlGaN/GaN HEMT和具有MoS2半导体性栅极的AlGaN/GaN HEMT的亚阈值摆幅(SS)。
图15(b)比较了具有Ni/Au金属栅极的AlGaN/GaN HEMT和具有MoS2半导体性栅极的AlGaN/GaN HEMT的断开状态击穿。
图16(a)是根据本发明的第七实施例的场效应晶体管的侧视图。
图16(b)是根据本发明的第七实施例的场效应晶体管的顶视图。
图16(c)是沿图16(b)中的虚线截取的场效应晶体管的剖视图。
具体实施方式
本发明描述了若干实施例和示例，并且下面的陈述均不应被视为一般地限制权利要求。将特别参考目前优选的实施例(作为示例而非限制)来描述本申请的众多创新技术。为了说明的简单和清楚，附图示出了一般的构造方式，并且可以省略公知特征和技术的描述和细节以避免不必要地模糊本发明。另外，附图中的元件不一定按比例绘制，可以扩展一些区域或元件以帮助改进对本发明实施例的理解。
说明书和权利要求书中的术语“第一”、“第二”、“第三”、“第四”等(如果有的话)可以用于区分相似的元件，而不一定用于描述特定的连续或时间顺序。应理解，如此使用的术语是可互换的。此外，术语“包括”、“包含”、“具有”及其任何变型旨在涵盖非排他性内含物，使得包括元素列表的过程、方法、物品、装置或组合物不一定限于这些元件，而是可以包括未明确列出的或者这种过程、方法、物品、装置或组合物固有的其他元件。
为了便于描述，本文可以使用空间相对术语，例如“下方”、“之下”、“低于”、“之上”、“上方”等，以描述如图中所示的特征与另一元素与特征之间的关系。应当理解，空间相对术语旨在包括装置在使用或操作中的除了图中所示的方向之外的不同方向。装置可以以其他方式定向(旋转90度或在其他方向上观察或参考)，并且应当相应地解释本文使用的空间相对描述符。
预期并且旨在将本申请中的控制部分的设计应用于所有半导体器件，如基于Si、SiC和GaAs或者如InAlN/GaN的异质结构的半导体器件；为清楚起见，一些示例优选地基于Si上AlGaN/GaN平台。然而，本领域普通技术人员将知道对设计进行修改以制作设计的其他组合和形式的变型。
图2(a)是根据本发明的第一实施例的场效应晶体管的侧视图；图2(b)是根据本发明的第一实施例的场效应晶体管的顶视图；图2(c)是沿图2(b)中的虚线截取的场效应晶体管的剖视图。如图2(a)至图2(c)所示，具有半导体性栅极的场效应晶体管(SG-FET)20包括形成在衬底(未示出)上的源极层21、漏极层22、沟道层23、栅极介电层24、半导体性栅极层25和栅电极26。
在一些实施例中，衬底可以包括硅、蓝宝石、金刚石、SiC、AlN、GaN等。半导体性栅极层25包括适度掺杂的半导体薄层，其掺杂浓度和厚度使其能被耗尽，并在被耗尽时，导电沟道载流子达到期望的载流子面密度，通常在1×1012cm-2至1×1014cm-2范围内。在一些实施例中，源极层21和漏极层22的材料可以包括掺杂半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。在一些实施例中，源极层21和漏极层22的材料可以包括金属，诸如Ni、Au、Al、Cr等。沟道层23的材料包括半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。沟道层23包括的半导体材料可以与源极层21或漏极层22(如果它们包括半导体材料)的半导体材料相同，但也可以是其他半导体材料。沟道层23可以是掺杂的或未掺杂的，这将影响FET的阈值电压并确定FET是耗尽型器件还是增强型器件。沟道层23电连接到源极层21和漏极层22。栅极介电层24可以是单层绝缘材料或半导体材料，但也可以是绝缘层和/或半导体层的组合。半导体性栅极层25位于沟道层23和栅极介电层24的顶部。如图2(b)和图2(c)所示，半导体性栅极层25从沟道层23在y方向上的两侧延伸超过沟道层23。半导体性栅极层25还可以包括具有相反载流子类型的附加半导体层，该附加半导体层在单个适度掺杂的半导体薄层的顶部(参见图9(a))。半导体性栅极层25的材料可以与沟道层23相同，但也可以是其他半导体材料，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体性栅极层25电连接到栅电极26。栅电极26的材料可以是金属、重掺杂的多晶硅或其他重掺杂的半导体。栅电极26位于沟道层23的区域之外(具体地，栅电极26在衬底上的正投影与沟道层23在衬底上的正投影不重叠)，使得栅电极26不通过电场效应直接耦合到沟道层23。施加在栅电极26上的电压应通过半导体性栅极层25间接地影响沟道层23的导电性。为了提供过压保护，半导体性栅极层25具有与沟道层23的有源沟道相同类型的载流子，即当沟道层23导通允许电流沿源极层21、沟道层23和漏极层22流动时沟道层23中的载流子类型。对于FET 20是n沟道器件的情况，半导体性栅极层25是n型，因此施加在栅电极26上的大的正栅极偏压将倾向于耗尽沟道层23上方的半导体性栅极层25。如果仔细调整半导体性栅极层25的掺杂，使其在下面的沟道层23完全导通时被完全耗尽，则在栅电极26处出现的任何附加电压将与栅极介电层24和下面的沟道层23去耦合，导致固有的栅极过压保护并抑制SG-FET20的栅极泄漏，而无需任何额外的保护电路或组件。
图16(a)是根据本发明的第七实施例的场效应晶体管的侧视图；图16(b)是根据本发明的第七实施例的场效应晶体管的顶视图；图16(c)是沿图16(b)中的虚线截取的场效应晶体管的剖视图。图2(a)-图2(c)为顶栅结构的场效应晶体管，图16(a)-图16(c)是与图2(a)-图2(c)的顶栅结构的场效应晶体管对应的背栅结构的场效应晶体管，两者结构类似，此处不加赘述。
图3(a)是根据本发明的第二实施例的场效应晶体管的顶视图；图3(b)是沿图3(a)中的虚线截取的场效应晶体管的剖视图。如图3(a)和图3(b)所示，SG-FET 30包括形成在衬底(未示出)上的源极层31、漏极层32、沟道层33、栅极介电层34、半导体性栅极层35、栅电极36和导电栅极层37。
与第一实施例中的SG-FET 20不同，在本实施例中的SG-FET 30中包括的半导体性栅极层35仅覆盖沟道层33的一部分，沟道层33的一部分被导电栅极层37覆盖。如图3(a)和图3(b)所示，半导体性栅极层35仅覆盖沟道层33在y方向上的一侧边缘。导电栅极层37通过半导体性栅极层35间接地电连接到栅电极36。结果，半导体性栅极层35对沟道层33的部分覆盖将保持固有的栅极过压保护能力，同时减小SG-FET 30的栅极电阻。衬底可以包括硅、蓝宝石、金刚石、SiC、AlN、GaN等。源极层31和漏极层32的材料可以包括掺杂半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等，但也可以包括金属，诸如Ni、Au、Al、Cr等。沟道层33的材料可以包括半导体，其可以与源极层31和漏极层32(如果它们包括半导体材料)包括的半导体相同，但也可以包括其他种类的半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。沟道层33可以是掺杂的或未掺杂的，这将影响FET的阈值电压并确定FET是耗尽型器件还是增强型器件。沟道层33电连接到源极层31和漏极层32。栅极介电层34可以是单层绝缘材料或半导体材料，但也可以是绝缘层和/或半导体层的组合。半导体性栅极层35包括适度掺杂的半导体薄层，其位于沟道层33和栅极介电层34的顶部。半导体性栅极层35的材料可以与沟道层33相同，也可以包括其他半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体性栅极层35电连接到栅电极36。栅电极36可以是金属、重掺杂多晶硅或其他重掺杂半导体。导电栅极层37的材料可以与栅电极36相同，但也可以是其他金属、重掺杂多晶硅或其他重掺杂半导体。栅电极36位于沟道层33的外部，使得栅电极36不通过电场效应直接与沟道层33耦合。施加在栅电极36上的电压通过半导体性栅极层35和导电栅极层37间接地影响沟道层33的导电性。为了提供过电压保护，半导体性栅极层35具有与沟道层33的有源沟道相同类型的载流子，即在沟道层33导通以允许电流沿源极层31、沟道层33和漏极层32流动时的载流子类型。
图4(a)是根据本发明的第三实施例的场效应晶体管的顶视图；图4(b)是沿图4(a)中的虚线截取的场效应晶体管的剖视图。如图4(a)和图4(b)所示，SG-FET 40包括形成在衬底(未示出)上的源极层41、漏极层42、沟道层43、栅介电层44、半导体性栅极层45、栅电极46、导电栅极层47和半导体层48。
在根据第二实施例SG-FET 30中，半导体性栅极层35和导电栅极层37下方的沟道层33是单个连续层。与第二实施例中的SG-FET 30不同，在根据第三实施例的SG-FET 40中，如图4(a)和图4(b)所示，半导体性栅极层45下方的半导体层48和导电栅极层47下方的沟道层43是两个彼此间隔开的层，并且独立地连接到源极层41。在一些实施例中，在从平面图中观察时，半导体性栅极层45完全覆盖半导体层48，导电栅极层47完全覆盖沟道层43。导电栅极层47通过半导体性栅极层45间接电连接到栅电极46。从栅电极46到导电栅极层47的所有可能的电路径应该至少包括在半导体层48上方的半导体性栅极层45的一部分。衬底可以包括硅、蓝宝石、金刚石、SiC、AlN、GaN等。源极层41和漏极层42可以是掺杂半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等，但也可以是金属，诸如Ni、Au、Al、Cr等。沟道层43的材料包括半导体，其可以与源极层41和漏极层42(如果它们包括半导体材料)包括的半导体相同，但也可以包括其他种类的半导体，例如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。沟道层43可以是掺杂的或未掺杂的，其仅影响FET的阈值电压并确定FET是耗尽型器件还是增强型器件。沟道层43电连接到源极层41和漏极层42。栅极介电层44可以是绝缘体或半导体的同质层，但也可以是绝缘层和/或半导体层的组合。半导体层48的材料可以与沟道层43相同，但也可以是其他种类的半导体，例如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体性栅极层45包括适度掺杂的半导体薄层，其位于半导体层48和栅极介电层44的顶部。半导体性栅极层45的材料可以与沟道层43相同，但也可以包括其他半导体，如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体性栅极层45电连接到栅电极46。栅电极46可以是金属、重掺杂多晶硅或其他重掺杂半导体。导电栅极层47的材料可以与栅电极46相同，但也可以是其他金属、重掺杂多晶硅或其他重掺杂半导体。半导体层48的材料可以与沟道层43相同，但也可以包括其他半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体层48可以是掺杂的或未掺杂的，这将仅影响钳位的栅极电压。栅电极46位于沟道层43和半导体层48的外部，使得栅电极46不通过电场效应直接与沟道层43和半导体层48耦合。施加在栅电极46上的电压通过半导体性栅极层45和导电栅极层47间接地影响沟道层43和半导体层48的导电性。为了提供过压保护，半导体性栅极层45具有与沟道层43的有源沟道相同的载流子类型，即当沟道层43导通以允许电流沿源极层41、沟道层43和漏极层42流动时的载流子类型。
图5(a)是根据本发明的第四实施例的场效应晶体管的顶视图；图5(b)是沿图5(a)中的虚线截取的场效应晶体管的剖视图。如
图5(a)和图5(b)所示，SG-FET 50包括形成在衬底(未示出)上的源极层51、漏极层52、沟道层53、栅极介电层54、半导体性栅极层55、栅电极56和导电栅极层57。
与根据第二实施例的SG-FET 30不同，SG-FET 50中的半导体性栅极层55完全位于源极层51和漏极层52之间的区域之外。沟道层53还具有在源极层51和漏极层52之间的区域之外的部分。沟道层53的该部分位于半导体性栅极层55之下。导电栅极层57位于沟道层53的位于源极层51和漏极层52之间的部分之上。导电栅极层57通过半导体性栅极层电连接到栅电极56。因为图5中的半导体性栅极层55位于源极层51和漏极层52之间的区域之外，半导体性栅极层可以具有比栅电极56和导电栅极层57更宽且可调整的接触长度。结果，SG-FET50具有进一步降低栅极电阻的优点。衬底可以是硅、蓝宝石、金刚石、SiC、AlN、GaN等。源极层51和漏极层52可以包括掺杂半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等，但也可以包括金属，诸如Ni、Au、Al、Cr等。沟道层53的材料可以包括半导体，其可以与源极层51和漏极层52(如果它们包括半导体材料)包括的半导体相同，但也可以包括其他类型的半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。沟道层53可以是掺杂的或未掺杂的，其仅影响FET的阈值电压并确定FET是耗尽型器件还是增强型器件。沟道层53电连接到源极层51和漏极层52。栅极介电层54可以是单层绝缘材料或半导体，但也可以是绝缘层和/或半导体层的组合。半导体性栅极层55包括适度掺杂的半导体薄层，其位于沟道层53和栅极介电层54的顶部。半导体性栅极层55的材料可以与沟道层53相同，但也可以是其他半导体材料，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体性栅极层55电连接到栅电极56。栅电极56可以是金属、重掺杂多晶硅或其他重掺杂半导体。导电栅极层57的材料可以与栅电极56相同，但也可以是其他金属、重掺杂多晶硅或其他重掺杂半导体。栅电极56位于沟道层53的区域之外，使得栅电极56不通过电场效应直接与沟道层53耦合。施加在栅电极56上的电压通过半导体性栅极层55和导电栅极层57间接地影响沟道层53的导电性。为了提供过压保护，半导体性栅极层55具有与沟道层53的有源沟道相同类型的载流子，即当沟道层53导通以允许电流沿源极层51、沟道层53和漏极层52流动时的载流子类型。
图6(a)是根据本发明的第五实施例的场效应晶体管的顶视图；图6(b)是沿图6(a)中的虚线截取的场效应晶体管的剖视图。如图6(a)和图6(b)所示，SG-FET 60包括形成在衬底(未示出)上的源极层61、漏极层62、沟道层63、栅极介电层64、半导体性栅极层65、栅电极66、导电栅极层67和半导体层68。
在根据第四实施例SG-FET 50中，半导体性栅极层55下方的沟道层53和导电栅极层57下方的沟道层53形成连续层。与第四实施例中的SG-FET 50不同，在根据第五实施例的SG-FET 60中，如图6(a)和图6(b)所示，彼此间隔开的半导体层68和沟道层63独立地连接到源极层61。半导体层68位于半导体性栅极层65下方。沟道层63位于导电栅极层67下方。从栅电极66到导电栅极层67的所有可能的电路径应至少包括半导体层68上方的半导体性栅极层65的一部分。导电栅极层67通过半导体性栅极层65电连接到栅电极66。衬底可以是硅、蓝宝石、金刚石、SiC、AlN、GaN等。源极层61和漏极层62可以是掺杂半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等，但也可以是金属，诸如Ni、Au、Al、Cr等。沟道层63的材料可以是半导体，其可以与源极层61和漏极层62(如果它们是半导体)的半导体相同，但也可以是其他类型的半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。沟道层63可以是掺杂的或未掺杂的，其仅影响FET的阈值电压并确定FET是耗尽型器件还是增强型器件。沟道层63与源极层61和漏极层62电连接。栅极介电层64可以是单层绝缘材料或半导体材料，但也可以是绝缘层和/或半导体层的组合。半导体层68的材料可以与沟道层63相同，但也可以是其他种类的半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体性栅极层65包括适度掺杂的半导体薄层，其位于半导体层68和栅极介电层64的顶部。半导体性栅极层65的材料可以与沟道层63相同，但也可以是其他薄层半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体性栅极层65电连接到栅电极66。栅极电极66可以是金属、重掺杂多晶硅或其他重掺杂半导体。导电栅极层67的材料可以与栅电极66相同，但也可以是其他金属、重掺杂多晶硅或其他重掺杂半导体。半导体层68的材料可以与沟道层63相同，但也可以是其他半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体层68可以是掺杂的或未掺杂的，这将仅影响钳位的栅极电压。栅电极66应位于沟道层63和半导体层68的外部，使得栅电极66不应通过电场效应直接与沟道层63和半导体层68耦合。施加在栅电极66上的电压通过半导体性栅极层65和导电栅极层67间接地影响沟道层63和半导体层68的导电性。为了提供过压保护，半导体性栅极层65具有与沟道层63的有源沟道相同的载流子类型，即在沟道层63导通以允许电流沿源极层61、沟道层63和漏极层62流动时的载流子类型。
图7(a)是根据本发明的第六实施例的场效应晶体管的顶视图；图7(b)是沿图7(a)中的虚线截取的场效应晶体管的剖视图。如图7(a)和图7(b)所示，SG-FET 70包括形成在衬底(未示出)上的源极层71、漏极层72、沟道层73、第一栅极介电层74、半导体性栅极层75、栅电极76、导电耦合层77和第二栅极介电层78。
与上述实施例中的SG-FET不同，SG-FET 70中的半导体性栅极层75不直接设置在沟道层73上方，而是通过导电耦合层77和第二栅极介电层78与沟道层73电容耦合。衬底可以是硅、蓝宝石、金刚石、SiC、AlN、GaN等。源极层71和漏极层72的材料可以是掺杂半导体，例如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等，但也可以是金属，诸如Ni、Au、Al、Cr等。沟道层73的材料可以是半导体，其可以与源极层71和漏极层72(如果它们的材料是半导体)的半导体相同，但也可以是其他种类的半导体，例如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。沟道层73可以是掺杂的或未掺杂的，其仅影响FET的阈值电压并确定FET是耗尽型器件还是增强型器件。沟道层73电连接到源极层71和漏极层72。第一栅极介电层74可以是单层绝缘材料或半导体材料，但也可以是绝缘层和/或半导体层的组合。半导体性栅极层75包括适度掺杂的半导体薄层。半导体性栅极层75的材料可以与沟道层73相同，但也可以是其他半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。半导体性栅极层75电连接到栅电极76。栅电极76可以是金属、重掺杂多晶硅或其他重掺杂半导体。导电耦合层77的材料可以与栅电极76相同，但也可以是其他金属、重掺杂多晶硅或其他重掺杂半导体。第二栅极介电层78的材料可以与第一栅极介电层74相同，但也可以是单层的其他绝缘材料或半导体材料，或其他绝缘层和/或半导体层的组合。施加在栅电极76上的电压通过半导体性栅极层75间接影响沟道层73的导电性，半导体性栅极层75进一步通过导电耦合层77耦合到沟道层73。为了提供过压保护，半导体性栅极层75具有与沟道层73的有源沟道相同类型的载流子，即当沟道层73导通以允许电流沿源极层71、沟道层73和漏极层72流动时的载流子类型。
图8(a)是根据本发明的第一实施例的场效应晶体管的第一示例的侧视图；图8(b)是图8(a)中的场效应晶体管的顶视图；图8(c)是沿图8(b)中的虚线截取的场效应晶体管的剖视图。如图8(a)至图8(c)所示，场效应晶体管80是基于Si CMOS技术的增强型n沟道FET。N型掺杂硅用作源极层81和漏极层82。P型掺杂硅用作沟道层83。栅极介电层84的材料是通过热氧化的二氧化硅和/或诸如HfO2、ZrO2、HfZrO2等的高k介质。使用n型硅薄层作为半导体性栅极层85。可替代地，可以使用其他n型半导体作为半导体性栅极层85，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、CNT等。n型半导体性栅极层85连接到栅电极86。栅电极86可以是重掺杂的n型硅或其他重掺杂的n型半导体或金属。尽管在图中示出了n型场效应晶体管，通过将图中的所有半导体的掺杂类型在n型和p型之间切换，场效应晶体管80可以成为具有半导体性栅极的p型场效应晶体管，其还具有固有的过压保护能力。
图9(a)是根据本发明的第一实施例的场效应晶体管的第二示例的侧视图；图9(b)是图9(a)中的场效应晶体管的顶视图；图9(c)是沿图9(b)中的虚线截取的场效应晶体管的剖视图。如图9(a)至图9(c)所示，场效应晶体管90是增强型FET。n型掺杂硅用作源极层91和漏极层92。p型掺杂硅用作沟道层93。栅极介电层94的材料是通过热氧化的二氧化硅和/或诸如HfO2、ZrO2、HfZrO2等的高k介质。使用n型硅薄层作为半导体性栅极层95。可替代地，可以使用其他n型半导体作为半导体性栅极层95，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。在n型半导体层95上方设有p型半导体层96。p型半导体层96的材料可以与半导体性栅极层95相同，这有助于减少半导体性栅极层95内部的载流子的表面散射。半导体层96的材料也可以是其他半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷、CNT等。n型半导体性栅极层95和p型半导体层96连接到栅电极97。栅电极97可以是重掺杂的n型硅或其他重掺杂的n型半导体或金属。尽管在图中场效应晶体管90是n型场效应晶体管，但是通过将图中的所有半导体的掺杂类型在n型和p型之间切换，场效应晶体管90可以变为具有半导体性栅极的p型场效应晶体管，其还具有固有的过压保护能力。
图10是根据本发明的第一实施例的场效应晶体管的第三示例的侧视图。场效应晶体管100是基于AlGaN/GaN HEMT技术的增强型n型HEMT。场效应晶体管100包括源极层101、漏极层102、沟道层103、栅极介电层104、半导体性栅极层105、势垒层107、成核/缓冲层108和钝化层109。源极层101和漏极层102可以为Ti/Al/Ni/Au，其可以与沟道层103形成欧姆接触。沟道层103可以是GaN。栅极介电层104可以是AlN、SiNx、Al2O3等。半导体性栅极层105是n型半导体，诸如Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、CNT等。势垒层107可以是AlGaN，其还可以包括AlN间隔层和GaN盖层。成核/缓冲层108可以是AlN、GaN、AlGaN等。钝化层109可以是AlN或SiNx。由于沟道层103和势垒层107的自发极化，在沟道层103和势垒层107之间的界面附近的沟道层103中形成二维电子气(2DEG)。在半导体性栅极层105下方，势垒层107的一部分凹陷以制造增强型器件。
图11(a)是根据本发明的第一实施例的场效应晶体管的第四示例的侧视图；图11(b)是根据本发明的第一实施例的场效应晶体管的第四示例的顶视图。如图图11(a)和图11(b)所示，场效应晶体管110是基于AlGaN/GaN HEMT技术的耗尽型n型HEMT。场效应晶体管110包括源极层111、漏极层112、沟道层113、半导体性栅极层115、势垒层117和成核/缓冲层118。源极层111和漏极层112可以为Ti/Al/Ni/Au，可以与沟道层113形成欧姆接触。沟道层113可以是GaN。半导体性栅极层115可以为层状二维半导体，诸如MoS2、WSe2、WS2、黑磷等。势垒层117可以是AlGaN，势垒层117还可以包括AlN间隔层和GaN盖层。成核/缓冲层118可以是AlN、GaN、AlGaN等。
图12(a)示出了沿以单层MoS2作为半导体性栅极的AlGaN/GaN HEMT 110的栅极宽度方向的模拟电子密度分布。图12(b)示出了沿以单层MoS2作为半导体性栅极的AlGaN/GaNHEMT 110的栅极宽度方向的模拟电位分布。半导体性栅极具有2V的耗尽阈值电压，并且半导体性栅极电极偏置为10V。根据模拟，在大的正向栅极偏压下，半导体性栅极被耗尽。有效栅极电压被钳位到SG的耗尽阈值电压，过大的栅极偏压由沟道边缘处的半导体性栅极承受。
图13(a)示出了以Ni/Au金属为栅极制造的AlGaN/GaN HEMT的转移曲线和栅极泄漏。图13(b)示出了以单层MoS2作为半导体性栅极的AlGaN/GaN HEMT的转移曲线和栅极泄漏。在4英寸(111)的Si衬底上生长的AlGaN/GaN异质结构上制造AlGaN/GaN HEMT。外延结构由4μm的GaN缓冲/过渡层和23.5nm的势垒层(包括1.5nm的AlN、20nm的AlGaN和2nm的GaN盖)构成。然后通过改进的湿转移方法将生长在蓝宝石衬底上的单层MoS2膜转移到样品上。在实现SG时，诸如所采用的MoS2的层状二维材料具有几个重要的益处，诸如在不同栅介质上转移高质量二维材料晶体的可行性以及二维材料层厚对SG耗尽阈值电压的良好可控性。
图14(a)示出了以Ni/Au为栅极的AlGaN/GaN HEMT的输出特性。图14(b)示出以单层MoS2作为半导体性栅极的AlGaN/GaN HEMT的输出特性。MG-HEMT和SG-HEMT之间的比较表明SG-HEMT的驱动电流没有损失。
图15(a)将具有Ni/Au金属栅极的AlGaN/GaN HEMT的亚阈值摆幅与具有MoS2半导体性栅极的AlGaN/GaN HEMT的亚阈值摆幅进行比较。图15(b)将具有Ni/Au金属栅极的AlGaN/GaN HEMT的断开状态击穿与具有MoS2半导体性栅极的AlGaN/GaN HEMT的断开状态击穿进行比较。具有MoS2半导体性栅极的AlGaN/GaN HEMT可以在不牺牲亚阈值摆幅的情况下有效地导通和断开HEMT。对于SG-HEMT，可以获得低至63mV/dec的亚阈值摆幅和109的高开关电流比。此外，SG不影响击穿电压。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (15)

1.一种场效应晶体管，包括：
衬底；
源极层，其位于所述衬底上；
漏极层，其位于所述衬底上；
沟道层，其电连接所述源极层和所述漏极层；
栅极介电层，其位于所述沟道层的远离所述衬底的一侧；
半导体性栅极层，其位于所述栅极介电层的远离所述沟道层的一侧；
栅电极，其与所述半导体性栅极层电连接，所述栅电极在所述衬底上的正投影在所述沟道层在所述衬底上的正投影之外，
其中，所述半导体性栅极层具有与所述沟道层在所述场效应晶体管导通状态下的导电沟道相同的载流子类型，并且所述半导体性栅极层的厚度和掺杂度设置为使得在向所述栅电极施加的电压大于预定电压时所述半导体性栅极被耗尽，同时所述沟道层的沟道完全导通。
2.根据权利要求1所述的场效应晶体管，其中，施加在所述栅电极上的电压间接地通过所述半导体性栅极层影响所述沟道层的导电性。
3.根据权利要求2所述的场效应晶体管，其中，所述半导体性栅极层的材料包括Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷或CNT。
4.根据权利要求1所述的场效应晶体管，还包括位于所述半导体性栅极层的远离所述衬底的一侧的第一半导体层，其中，所述半导体性栅极层的载流子类型与所述第一半导体层的载流子类型相反，所述半导体性栅极层和所述第一半导体层均与所述栅电极连接。
5.根据权利要求1-4中任一项所述的场效应晶体管，其中，所述半导体性栅极层沿平行于所述衬底的方向延伸超出所述沟道层。
6.根据权利要求1-4中任一项所述的场效应晶体管，还包括导电栅极层，其中，所述导电栅极层位于所述栅极介电层的远离所述沟道层的一侧并且通过所述半导体性栅极层电连接至所述栅电极。
7.根据权利要求6所述的场效应晶体管，其中，所述半导体性栅极层沿垂直于所述衬底的方向覆盖所述沟道层的一部分，所述导电栅极层沿垂直于所述衬底的方向覆盖所述沟道层的另一部分。
8.根据权利要求6所述的场效应晶体管，其中，还包括第二半导体层，所述第二半导体层与所述源极层连接并且与所述沟道层间隔开，所述半导体性栅极层沿垂直于所述衬底的方向覆盖所述第二半导体层，所述导电栅极层沿垂直于所述衬底的方向覆盖所述沟道层。
9.根据权利要求6所述的场效应晶体管，其中，所述沟道层包括在平面图中观察时朝向所述栅电极且位于所述源极层和所述漏极层之间的区域之外的突出部分，所述半导体性栅极层在平面图中观察时位于所述源极层和所述漏极层之间的区域之外并且与所述突出部分至少部分重叠。
10.根据权利要求6所述的场效应晶体管，还包括与所述源极层连接的第三半导体层，其中，在平面图中观察时，所述第三半导体层在所述源极层和所述漏极层之间的区域之外并且与所述沟道层间隔开，所述半导体性栅极层位于所述源极层和所述漏极层之间的区域之外并且与所述第三半导体层至少部分重叠。
11.根据权利要求1所述的场效应晶体管，其中所述沟道层的材料包括Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷或CNT。
12.根据权利要求1所述的场效应晶体管，其中，所述栅电极的材料包括金属，重掺杂的Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷或CNT。
13.根据权利要求6所述的场效应晶体管，其中，所述导电栅极层的材料包括金属，重掺杂的Si、Ge、SiGe、ZnO、IGZO、GaAs、GaN、SiC、MoS2、WSe2、WS2、黑磷或CNT。
14.一种场效应晶体管，包括：
衬底；
半导体性栅极层，其位于所述衬底上；
栅电极，其位于所述衬底上并与所述半导体性栅极层电连接；
栅极介电层，其位于所述半导体性栅极层的远离所述衬底的一侧；
源极层；
漏极层；
沟道层，其位于所述栅极介电层的远离所述衬底的一侧并且电连接所述源极层和所述漏极层，所述沟道层在所述衬底上的正投影在所述栅电极在所述衬底上的正投影之外，
其中，所述半导体性栅极层具有与所述沟道层在所述场效应晶体管导通状态下的导电沟道相同的载流子类型，并且所述半导体性栅极层的厚度和掺杂度设置为使得在向所述栅电极施加的电压大于预定电压时所述半导体性栅极被耗尽，同时所述沟道层的沟道完全导通。
15.一种场效应晶体管，包括：
衬底；
源极层，其位于所述衬底上；
漏极层，其位于所述衬底上；
沟道层，其电连接所述源极层和所述漏极层；
半导体性栅极层，其在所述衬底上的正投影在所述沟道层在所述衬底上的正投影之外；
第一栅极介电层，其位于所述沟道层的远离所述衬底的一侧；
第二栅极介电层，其位于所述半导体性栅极层的远离所述衬底的一侧；
导电耦合层，其位于所述第一栅极介电层和所述第二栅极介电层的远离所述衬底的一侧；以及
栅电极，其电连接所述半导体性栅极层，所述栅电极在所述衬底上的正投影在所述沟道层在所述衬底上的正投影之外，
其中，所述半导体性栅极层具有与所述沟道层在所述场效应晶体管导通状态下的导电沟道相同的载流子类型，并且所述半导体性栅极层的厚度和掺杂度设置为使得在向所述栅电极施加的电压大于预定电压时所述半导体性栅极被耗尽，同时所述沟道层的沟道完全导通。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111786564A (zh) * 2020-07-15 2020-10-16 江苏能华微电子科技发展有限公司 一种高效率紧凑型快充电源
CN111969398A (zh) * 2020-08-06 2020-11-20 南京信息工程大学 一种基于石墨烯可饱和吸收器件的电压可控全固态被动调q激光器
CN115274834A (zh) * 2021-04-30 2022-11-01 长鑫存储技术有限公司 栅极结构及其制造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7115637B2 (ja) * 2019-05-16 2022-08-09 富士電機株式会社 半導体集積回路
US20220352340A1 (en) * 2021-04-30 2022-11-03 Changxin Memory Technologies, Inc. Gate structure and manufacturing method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965645A (en) * 1987-03-20 1990-10-23 International Business Machines Corp. Saturable charge FET
US20010009785A1 (en) * 1999-12-30 2001-07-26 Mohamed Arafa Method of fabricating a supply decoupling capacitor
CN101361192A (zh) * 2006-12-18 2009-02-04 松下电器产业株式会社 半导体设备
CN101789445A (zh) * 2008-12-22 2010-07-28 三垦电气株式会社 半导体装置
CN102365727A (zh) * 2009-03-27 2012-02-29 国家半导体公司 具有带着经裁制垂直氮浓度轮廓的氮化栅极介电层的场效应晶体管的结构和制造
CN102651388A (zh) * 2011-02-25 2012-08-29 富士通株式会社 化合物半导体器件及其制造方法
CN103325843A (zh) * 2012-03-23 2013-09-25 株式会社东芝 结型场效应晶体管及其制造方法
US20130256699A1 (en) * 2012-03-30 2013-10-03 Infineon Technologies Austria Ag Gate Overvoltage Protection for Compound Semiconductor Transistors

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3407339A (en) 1966-05-02 1968-10-22 North American Rockwell Voltage protection device utilizing a field effect transistor
US3712995A (en) 1972-03-27 1973-01-23 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
US4066918A (en) 1976-09-30 1978-01-03 Rca Corporation Protection circuitry for insulated-gate field-effect transistor (IGFET) circuits
US4364072A (en) * 1978-03-17 1982-12-14 Zaidan Hojin Handotai Kenkyu Shinkokai Static induction type semiconductor device with multiple doped layers for potential modification
US4583105A (en) * 1982-12-30 1986-04-15 International Business Machines Corporation Double heterojunction FET with ohmic semiconductor gate and controllable low threshold voltage
US6175394B1 (en) 1996-12-03 2001-01-16 Chung-Cheng Wu Capacitively coupled field effect transistors for electrostatic discharge protection in flat panel displays
US20020064946A1 (en) * 2000-11-30 2002-05-30 Christoph Wasshuber Field effect transistor with silicide gate
US6864537B1 (en) * 2003-01-03 2005-03-08 Micrel, Incorporated Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
US7307319B1 (en) * 2004-04-30 2007-12-11 Lattice Semiconductor Corporation High-voltage protection device and process
US7473626B2 (en) * 2006-04-11 2009-01-06 International Business Machines Corporation Control of poly-Si depletion in CMOS via gas phase doping
US8390063B2 (en) 2010-01-29 2013-03-05 Broadcom Corporation Semiconductor device having a lightly doped semiconductor gate and method for fabricating same
US9160326B2 (en) 2012-07-10 2015-10-13 The Hong Kong University Of Science And Technology Gate protected semiconductor devices
US9735147B2 (en) * 2014-09-15 2017-08-15 Fairchild Semiconductor Corporation Fast and stable ultra low drop-out (LDO) voltage clamp device
US9276092B1 (en) * 2014-10-16 2016-03-01 Micron Technology, Inc. Transistors and methods of forming transistors
US9882553B2 (en) 2015-12-18 2018-01-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and circuit protecting method
CN108314677B (zh) * 2017-01-17 2020-06-30 安徽中科拓苒药物科学研究有限公司 一种ezh2抑制剂及其用途

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965645A (en) * 1987-03-20 1990-10-23 International Business Machines Corp. Saturable charge FET
US20010009785A1 (en) * 1999-12-30 2001-07-26 Mohamed Arafa Method of fabricating a supply decoupling capacitor
CN101361192A (zh) * 2006-12-18 2009-02-04 松下电器产业株式会社 半导体设备
CN101789445A (zh) * 2008-12-22 2010-07-28 三垦电气株式会社 半导体装置
CN102365727A (zh) * 2009-03-27 2012-02-29 国家半导体公司 具有带着经裁制垂直氮浓度轮廓的氮化栅极介电层的场效应晶体管的结构和制造
CN102651388A (zh) * 2011-02-25 2012-08-29 富士通株式会社 化合物半导体器件及其制造方法
CN103325843A (zh) * 2012-03-23 2013-09-25 株式会社东芝 结型场效应晶体管及其制造方法
US20130256699A1 (en) * 2012-03-30 2013-10-03 Infineon Technologies Austria Ag Gate Overvoltage Protection for Compound Semiconductor Transistors

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111786564A (zh) * 2020-07-15 2020-10-16 江苏能华微电子科技发展有限公司 一种高效率紧凑型快充电源
CN111969398A (zh) * 2020-08-06 2020-11-20 南京信息工程大学 一种基于石墨烯可饱和吸收器件的电压可控全固态被动调q激光器
CN115274834A (zh) * 2021-04-30 2022-11-01 长鑫存储技术有限公司 栅极结构及其制造方法
WO2022227337A1 (zh) * 2021-04-30 2022-11-03 长鑫存储技术有限公司 栅极结构及其制造方法

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