CN115966563A - 电子装置 - Google Patents

电子装置 Download PDF

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Publication number
CN115966563A
CN115966563A CN202211196530.9A CN202211196530A CN115966563A CN 115966563 A CN115966563 A CN 115966563A CN 202211196530 A CN202211196530 A CN 202211196530A CN 115966563 A CN115966563 A CN 115966563A
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China
Prior art keywords
electronic device
substrate
pcb
semiconductor die
die
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CN202211196530.9A
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English (en)
Inventor
杨亚伦
吴文洲
郭哲宏
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MediaTek Inc
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MediaTek Inc
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Publication of CN115966563A publication Critical patent/CN115966563A/zh
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Abstract

本发明公开一种电子装置，包括：主印刷电路板(PCB)组件，包括底部PCB和安装在该底部PCB的上表面上的半导体封装，其中该半导体封装包括基板和安装在该基板的上表面上的半导体晶粒，其中该半导体晶粒和该基板的该上表面由模塑料封装；以及顶部PCB，通过第一连接元件安装在该半导体封装上。本发明实施例中通过在半导体封装的上表面也安装顶部PCB，可以大大提高电子装置的设计弹性，例如可以通过顶部PCB为电子装置提供更多的电子元器件，而不占用半导体封装的下表面的空间，避免或减少增加电子装置的平面面积。

Description

电子装置
技术领域
本发明涉及半导体技术领域，尤其涉及一种电子装置。
背景技术
部件(component)的小型化、集成电路(integrated circuit，IC)的更高封装密度、更高的性能和更低的成本是计算器行业的持续目标。为了支持具有更高功能和更好性能的电子装置，越来越多的信号焊球(signal ball)被集成到一个单个芯片封装中，这导致了整体封装尺寸的增加。
PCB设计师面临同样的问题。如本领域已知的，PCB是在表面上具有接合焊盘以固定电路元件的平面结构。PCB的扁平结构对电子装置的形状施加了限制。
发明内容
有鉴于此，本发明提供一种电子装置，电子装置具有堆叠印刷电路板(PCB)，以解决上述问题。
根据本发明的第一方面，公开一种电子装置，包括：
主印刷电路板(PCB)组件，包括底部PCB和安装在该底部PCB的上表面上的半导体封装，其中该半导体封装包括基板和安装在该基板的上表面上的半导体晶粒，其中该半导体晶粒和该基板的该上表面由模塑料封装；以及
顶部PCB，通过第一连接元件安装在该半导体封装上。
根据本发明的第二方面，公开一种形成电子装置，包括：
主印刷电路板(PCB)组件，包括底部PCB和安装在该底部PCB上表面上的半导体封装，其中该半导体封装包括基板、安装在该基板的上表面上的半导体晶粒和安装在该半导体晶粒上的存储器部件；和
顶部PCB，通过第一连接元件安装在该半导体封装上。
本发明的电子装置由于包括：主印刷电路板(PCB)组件，包括底部PCB和安装在该底部PCB的上表面上的半导体封装，其中该半导体封装包括基板和安装在该基板的上表面上的半导体晶粒，其中该半导体晶粒和该基板的该上表面由模塑料封装；以及顶部PCB，通过第一连接元件安装在该半导体封装上。本发明实施例中通过在半导体封装的上表面也安装顶部PCB，可以大大提高电子装置的设计弹性，例如可以通过顶部PCB为电子装置提供更多的电子元器件，而不占用半导体封装的下表面的空间，避免或减少增加电子装置的平面面积；也可以利用顶部PCB将多个半导体封装进行电性连接；或者利用顶部PCB实现例如更多的散热路径，更高的部件整合度(集成度)等等。因此本发明可以显著的提升电子装置的设计灵活性和设计弹性，并且使本发明的电子装置的布局更加合理，电子装置及半导体封装的运行更加稳定可靠。
附图说明
图1是显示根据本发明的一个实施例的具有堆叠印刷电路板(PCB)的示例性电子装置的示意性截面图；
图2是显示根据本发明另一实施例的具有堆叠PCB的示例性电子装置的示意性截面图；
图3为本发明另一实施例的具有堆叠PCB的电子装置的剖面示意图；
图4是显示根据本发明另一实施例的具有堆叠PCB的示例性电子装置的示意性截面图；
图5是显示根据本发明另一实施例的具有堆叠PCB的示例性电子装置的示意性截面图；以及
图6是示出根据本发明的另一个实施例的具有堆叠PCB的示例性电子装置的示意性截面图。
具体实施方式
在下面对本发明的实施例的详细描述中，参考了附图，这些附图构成了本发明的一部分，并且在附图中通过图示的方式示出了可以实践本发明的特定的优选实施例。对这些实施例进行了足够详细的描述，以使本领域技术人员能够实践它们，并且应当理解，在不脱离本发明的精神和范围的情况下，可以利用其他实施例，并且可以进行机械，结构和程序上的改变。本发明。因此，以下详细描述不应被理解为限制性的，并且本发明的实施例的范围仅由所附权利要求限定。
将理解的是，尽管术语“第一”、“第二”、“第三”、“主要”、“次要”等在本文中可用于描述各种组件、组件、区域、层和/或部分，但是这些组件、组件、区域、这些层和/或部分不应受到这些术语的限制。这些术语仅用于区分一个组件、组件、区域、层或部分与另一区域、层或部分。因此，在不脱离本发明构思的教导的情况下，下面讨论的第一或主要组件、组件、区域、层或部分可以称为第二或次要组件、组件、区域、层或部分。
此外，为了便于描述，本文中可以使用诸如“在...下方”、“在...之下”、“在...下”、“在...上方”、“在...之上”之类的空间相对术语，以便于描述一个组件或特征与之的关系。如图所示的另一组件或特征。除了在图中描述的方位之外，空间相对术语还意图涵盖设备在使用或运行中的不同方位。该设备可以以其他方式定向(旋转90度或以其他定向)，并且在此使用的空间相对描述语可以同样地被相应地解释。另外，还将理解的是，当“层”被称为在两层“之间”时，它可以是两层之间的唯一层，或者也可以存在一个或多个中间层。
术语“大约”、“大致”和“约”通常表示规定值的±20％、或所述规定值的±10％、或所述规定值的±5％、或所述规定值的±3％、或规定值的±2％、或规定值的±1％、或规定值的±0.5％的范围内。本发明的规定值是近似值。当没有具体描述时，所述规定值包括“大约”、“大致”和“约”的含义。本文所使用的术语仅出于描述特定实施例的目的，并不旨在限制本发明。如本文所使用的，单数术语“一”，“一个”和“该”也旨在包括复数形式，除非上下文另外明确指出。本文所使用的术语仅出于描述特定实施例的目的，并不旨在限制本发明构思。如本文所使用的，单数形式“一个”、“一种”和“该”也旨在包括复数形式，除非上下文另外明确指出。
将理解的是，当将“组件”或“层”称为在另一组件或层“上”、“连接至”、“耦接至”或“邻近”时，它可以直接在其他组件或层上、与其连接、耦接或相邻、或者可以存在中间组件或层。相反，当组件称为“直接在”另一组件或层“上”、“直接连接至”、“直接耦接至”或“紧邻”另一组件或层时，则不存在中间组件或层。
注意：(i)在整个附图中相同的特征将由相同的附图标记表示，并且不一定在它们出现的每个附图中都进行详细描述，并且(ii)一系列附图可能显示单个项目的不同方面，每个方面都与各种参考标签相关联，这些参考标签可能会出现在整个序列中，或者可能只出现在序列的选定图中。
集成电路(integrated circuit，IC)芯片的封装可以涉及将IC芯片附接到基板(例如，封装基板)，其中，基板在芯片和设备的其他电子元件之间提供机械支撑和电连接。基板类型包括例如有芯基板(包括薄芯、厚芯(层压双马来酰亚胺-三嗪树脂((bismaleimide-triazine resin，BT树脂)或FR-4型纤维板材料)和层压芯)，以及无芯基板。例如，有芯封装基板可以围绕中心核心逐层构建，导电材料层(通常是铜)由绝缘电介质层隔开，层间连接由穿孔或微通孔(或通孔)形成。
高带宽存储器(High Bandwidth Memory，HBM)是用于3D堆叠(3D-stacked)同步动态随机存取存储器(synchronous dynamic random-access memory，SDRAM)的高速计算机存储器接口。HBM以比DDR4或GDDR5小得多的外形尺寸实现更高的带宽，同时使用更少的功率。这是通过堆叠多达八个DRAM晶粒和一个可选的基础晶粒来实现的，该基础晶粒可以包括缓冲电路和测试逻辑。堆叠通常通过基板(例如硅中介层)连接到GPU或CPU上的存储器控制器。或者，存储器芯片(或晶粒)可以直接堆叠在CPU或GPU芯片上。在堆叠中，芯片通过硅通孔(through-silicon via，TSV)和微凸块垂直互连。HBM DRAM使用宽接口架构(wide-interface architecture)来实现高速、低功耗运行。
图1是示出根据本发明的一个实施例的具有堆叠印刷电路板(printed circuitboard，PCB)的示例性电子装置1的示意性截面图。在一些实施例中，电子装置1可以用作三维(three-dimensional，3D)组件，电子装置1包括分别安装在半导体封装的相对侧上的至少两个垂直堆叠的PCB。如图1所示，电子装置1包括主PCB组件10，包括但不限于底部PCB PB和安装在底部PCB PB的上表面S1上的半导体封装CP。在一些实施例中，例如，半导体封装CP可以包括基板100和安装在基板100的上表面(晶粒附接表面)100a上的半导体晶粒101，例如逻辑晶粒。半导体晶粒101可以包括倒装芯片晶粒、引线接合晶粒或扇出晶粒。半导体晶粒101可以通过诸如凸块或金属柱的(多个)连接元件111连接到基板100的上表面100a，但不限于此。半导体晶粒101和基板100的上表面100a可以由诸如环氧树脂的模塑料120封装。此外，本发明实施例中“(多个)”可以表示该部件可以是多个或者是一个，本发明并未对该部件的数量作出具体的限制，读者可以根据本实施例的描述自行调整该部件的数量，并且不会或几乎不会影响本发明实施例所揭示的发明思想和技术方案。
根据一个实施例，例如，附加部件103和105可以安装在底部PCB PB的表面上。附加部件103和105可以包括有源或无源组件，例如IC芯片、电容器、电阻器或电感器。尽管半导体晶粒101被示为以倒装芯片方式安装在基板100的上表面100a上，但是应当理解，在一些实施例中，半导体晶粒101可以通过使用引线接合技术安装在基板100上.在一些实施例中，半导体封装CP可以包括扇出(fan-out)晶粒。
在一些实施例中，半导体封装CP可以包括一个或多个逻辑晶粒，包括但不限于中央处理单元(central processing unit，CPU)、图形处理单元(graphics processingunit，GPU)、***单芯片(system-on-a-chip，SOC)、现场可程序设计门阵列(field-programmable gate array，FPGA)、微控制器单元(microcontroller unit，MCU)、电源管理集成电路(power management integrated circuit，PMIC)晶粒、射频(radio frequency，RF)晶粒、传感器晶粒、微机电***(micro-electro-mechanical-system，MEMS)晶粒或信号处理晶粒(例如，数字信号处理(digital signal processing，DSP)芯片)等，或它们的任何组合。
根据一个实施例，例如，基板100可以是布线基板并且可以由聚合物材料形成，，例如本领域已知的双马来酰亚胺三嗪(bismaleimide triazine，BT)层压板和/或积层膜(build-up film)。在一些实施例中，基板100可以是包括介电层和导电层的重分布层(re-distribution layer，RDL)基板，并且与传统封装基板相比可以具有更薄的厚度。应当理解，基板100可以是单层或多层结构。
例如，根据一个实施例，基板100可以包括设置在基板100的上表面100a上或在基板100的上表面100a附近的(多个)连接焊盘100p。根据一个实施例，例如，基板100可以包括(多个)导电迹线100t将(多个)连接垫100p与分布在基板100的底表面100b上或在基板100的底表面100b附近的(多个)球垫100s互连。焊球SB分别设置在球垫(或焊球垫、焊球焊盘)100s上。在一些实施例中，至少一种被动装置PE可以使用表面安装技术(surface mounttechnique，SMT)安装在基板100的底表面100b上。
根据一个实施例，可以在模塑料120中设置(多个)穿模通孔(through mold via，TMV)122。TMV 122穿透模塑料120的整个厚度，从而在半导体封装CP的上表面S2上形成端子122t。根据一个实施例，例如，PCB组件50和PCB 60可以分别通过连接元件502和602安装在半导体封装CP的上表面S2上的对应端子122t上，直接连接的方式可以使PCB到半导体封装CP具有更短的连接路径。根据一个实施例，例如，连接元件502和602可以包括焊球或本领域已知的任何合适的导电接头。根据一个实施例，例如，PCB组件50可以包括PCB 52和组件503和505，例如安装在PCB 52相对侧的存储器装置、天线器件(或装置)或射频(radio-frequency，RF)器件(或装置)。在实施例中，印刷电路板组件50与印刷电路板60物理分离并且并排设置在半导体封装CP的上表面S2上。本发明实施例中，例如可以安装PCB组件50和PCB 60中的至少一个，并且可称为顶部PCB，也即安装在半导体封装CP之上的顶部PCB可以包括PCB组件50(第一PCB组件)和PCB 60(第一PCB)中的任意一个或者同时包括两者(当然还可以包括其他PCB等部件)，也即顶部PCB包括第一PCB和/或第一PCB组件，第一PCB和/或第一PCB组件可以通过相对应的连接元件(例如相对应的连接元件502和/或602)安装在该半导体封装CP上。因此，PCB组件50也可以称为顶部PCB组件(或者第一PCB组件)。在一个实施例中，PCB 60(第一PCB)和/或PCB 52(第二PCB)也可以是布线基板或者其他线路板等。本实施例中第一连接元件可以包括连接元件502和/或602。
使用本发明是有利的，因为通过将一些信号通过TMV 122连接到PCB组件50和PCB60，可以减少底部焊球数量和半导体封装CP的尺寸。本发明实施例中通过在半导体封装CP的上表面也安装顶部PCB，可以大大提高电子装置的设计弹性，例如可以通过顶部PCB组件50为电子装置提供更多的电子元器件(例如电容器、电感器、天线(天线装置)、RF部件(射频装置)、存储器装置或其他元器件等等)，而不占用半导体封装CP的下表面的空间，避免或减少增加电子装置的平面面积；也可以利用顶部PCB组件50和/或PCB 60将多个半导体封装进行电性连接；或者利用顶部PCB组件50和/或PCB 60实现例如更多的散热路径，更高的部件整合度(集成度)等等。因此本发明的上述方案可以显著的提升电子装置的设计灵活性和设计弹性，并且使本发明的电子装置的布局更加合理，电子装置及半导体封装的运行更加稳定可靠。
图2是示出根据本发明的另一个实施例的具有堆叠PCB的示例性电子装置2的示意性横截面图，其中相似的区域、层或元件由相似的数字编号或卷标表示。在一些实施例中，电子装置2可以用作3D组件，包括分别安装在半导体封装的相对侧上的至少两个垂直堆叠的PCB。如图2所示，同样地，电子装置2包括主PCB组件(main printed circuit board)10，主PCB组件10包括但不限于底部PCB PB和安装在底部PCB PB的上表面S1上的半导体封装CP。在一些实施例中，例如，半导体封装CP可以包括基板100和安装在基板100的上表面(晶粒附接表面)100a上的半导体晶粒101(例如逻辑晶粒)。半导体晶粒101可以通过穿透半导体晶粒101的整个厚度的(多个)硅通孔(TSV)110连接到基板100的上表面100a。半导体晶粒101的***侧壁和基板100的上表面100a可以由诸如环氧树脂的模塑料120封装。
根据一个实施例，例如，附加部件103和105可以安装在底部PCB PB的表面上。附加部件103和105可以包括有源或无源组件(或部件)，例如IC芯片、电容器、电阻器或电感器。
在一些实施例中，半导体封装CP可以包括一个或多个逻辑晶粒，包括但不限于中央处理单元(CPU)、图形处理单元(GPU)、片上***(SOC)、现场可程序设计门阵列(FPGA)、微控制器单元(MCU)、电源管理集成电路(PMIC)芯片、射频(RF)芯片、传感器芯片、微机电***(MEMS))晶粒、信号处理晶粒(例如，数字信号处理(DSP)晶粒)等，或它们的任何组合。
根据一个实施例，例如，基板100可以是布线基板并且可以由聚合物材料形成，例如本领域已知的双马来酰亚胺三嗪(bismaleimide triazine，BT)层压板和/或积层膜(build-up film)。在一些实施例中，基板100可以是包括介电层和导电层的重分布层(re-distribution layer，RDL)基板，并且与传统封装基板相比可以具有更薄的厚度。应当理解，基板100可以是单层或多层结构。
例如，根据一个实施例，基板100可以包括设置在基板100的上表面100a上或在基板100的上表面100a附近的(多个)连接焊盘100p。根据一个实施例，例如，基板100可以包括(多个)导电迹线100t将(多个)连接垫(连接垫或连接焊盘)100p与分布在基板100的底表面100b上或在基板100的底表面100b附近的(多个)球垫(焊球垫或焊球焊盘)100s互连。焊球SB分别设置在球垫(焊球垫或焊球焊盘)100s上。在一些实施例中，可以使用表面安装技术(surface mount technique，SMT)将至少一个无源器件PE安装在基板100的底表面100b上。
根据一个实施例，半导体晶粒101安装在基板100的上表面100a上。根据一个实施例，半导体晶粒101具有上表面(或有源表面)101a和无源后表面101b。诸如晶体管的电路元件被制造在半导体晶粒101的上表面101a上或在半导体晶粒101的上表面101a附近。根据一个实施例，半导体晶粒101的无源后表面101b可以通过使用本领域已知的方法(例如，SMT或粘合)耦接到基板100的上表面100a。即，半导体晶粒101以“面朝上”配置安装在基板100的上表面100a上，也即半导体晶粒101的有源表面101a朝上(朝向存储器部件(或组件)3001)，其中半导体晶粒101的有源表面101a是指靠近半导体晶粒101的主要电路(例如靠近半导体晶粒的二极管、晶体管等)的一面，半导体晶粒101的无源后表面101b是指远离半导体晶粒101的主要电路(例如二极管、晶体管等)的一面(也即无源后表面101b是非主要电路面)。半导体晶粒101的有源表面101a可以设有用于半导体晶粒101输入/输出的焊盘，半导体晶粒101的无源后表面101b也可以设置输入/输出的电性连接结构(例如TSV穿过去形成的连接结构)，半导体晶粒101的无源后表面101b主要是基材，例如硅或硅化物等等。根据一个实施例，半导体晶粒101可以通过TSV 110电连接到基板100和基板100的底表面100b上的焊球SB，TSV 110主要用于半导体晶粒101或HBM的电源/接地连接。根据一个实施例，例如，TSV110可以是用于传输电源或接地信号的电源或接地TSV，这种连接方式大幅缩短了连接到焊球SB的连接路径或连接路程，对传输效率及高速传输具有明显的提升。
根据一个实施例，电子装置2还包括在半导体晶粒101上的中间重分布层(RDL)结构200。根据一个实施例，中间RDL结构200可以包括介电层210和互连结构220。互连结构220可以电连接到(多个)RDL焊盘230。根据一个实施例，半导体晶粒101的上表面101a通过例如微凸块、金属柱之类的连接元件BP电连接到中间RDL结构200。根据一个实施例，中间RDL结构200与半导体晶粒101的上表面101a之间的间隙可以填充有诸如环氧树脂的底部填充材料UF，但不限于此。根据一个实施例，可以在模塑料120中设置(多个)穿模通孔(TMV)122。TMV 122可以电连接到中间RDL结构200的互连结构220。
根据一个实施例，例如，PCB组件50和PCB 60可以安装在中间RDL结构200的对应RDL焊盘230上。根据一个实施例，例如，PCB组件50可以包括PCB 52和元件(部件或组件)503和505分别通过连接元件502和602安装在PCB 52的相对侧。根据一个实施例，例如，连接元件502和602可以包括焊球或本领域已知的任何合适的导电接头。根据一个实施例，PCB组件50与PCB 60物理分离并与PCB 60并排设置在中间RDL结构200上。
根据一个实施例，存储器组件(或部件)300直接安装在中间RDL结构200上并且可以设置在PCB 60和PCB组件50之间。存储器组件(或部件)300可以通过导电结构例如凸块或金属柱或焊球等等电性连接元件连接到RDL结构200(例如互连结构220)。根据一个实施例，存储器组件300可以从PCB 60和PCB组件50的上表面突出。根据一个实施例，存储器组件300可以包括高带宽存储器(High-Bandwidth Memory，HBM)，高带宽存储器包括彼此堆叠的(多个)DRAM晶粒301，并且堆叠的DRAM晶粒301通过硅通孔(TSV)310和微凸块BT垂直互连。根据一个实施例，存储器组件300还可以包括DRAM基座302，DRAM基座302可以包括缓冲电路和测试逻辑。在一些实施例中，DRAM基座302可以包括DRAM控制器。
根据一个实施例，当从上面看时(俯视时)，存储器组件300可以与下面的半导体晶粒101对齐并且设置在半导体晶粒101的中心处或附近。也就是说，存储器组件300的中心可以与半导体晶粒101的中心对齐。当从上面看时(俯视时)，存储器组件300与下面的半导体晶粒101完全重叠，其中完全重叠可以是指，俯视时存储器部件300的投影完全落入半导体晶粒101的范围内、或者俯视时存储器部件300的投影完全覆盖半导体晶粒101。根据一个实施例，DRAM基底302是电耦接到中间RDL结构200，并且诸如电源或接地的信号可以通过较短的导电路径传输到基板100的底表面100b上的焊球SB，该较短的导电路径至少包括中间RDL结构的互连结构220、连接元件BP、半导体晶粒101的TSV 110、以及基板100的导电迹线100t。可选地，一些电源或接地信号可以经由连接元件BP、中间RDL结构200的互连结构220、TMV 122和基板100的导电迹线100t传输到位于基板100的底表面100b上的焊球SB。此外，存储器组件(或部件)300与RDL结构200之间的电性连接元件可以是多个，该多个电性连接元件的数组或该多个电性连接元件的群组的中心位置可以与存储器部件300的中心(沿图1竖直方向的中心)重合，以使HBM的应用中传输效率最大化。本实施例可以适用于高带宽存储器(HBM)的应用中，TSV 110的设计可以使得存储器部件300与半导体晶粒101、焊球SB之间的电性连接路径更短，传输效率更高，并且电子装置的整合度(集成度)也更高，电子装置的功能更加强大。此外本实施例中连接元件502和/或602通过中间RDL结构200电性连接到半导体封装CP(例如TMV 122、端子122t)，因此连接元件502和/或602的布置位置可以更加灵活，无需必须对准半导体封装CP的导电结构(例如TMV122、端子122t)布置，提高了设计的灵活性和设计弹性。另外本实施例中将存储器组件300设置于PCB组件50与PCB 60之间的设计可以使得电子装置整体的结构完整性更佳，减少不平衡应力，从而提高电子装置的结构稳定性，保证电子装置稳定、可靠的运行。此外，本发明实施例TSV 110的设计还显著增加了存储器部件300与半导体晶粒101和/或焊球SB之间的传输信道，使得传输信道的数量及横截面积大大提高，因此进一步提高了传输效率。
图3是显示根据本发明的又一实施例的具有堆叠PCB的示例性电子装置3的示意性横截面图，其中相同的区域、层或元件由相同的数字编号或卷标表示。图3中的电子装置3与图2中的电子装置2的一个不同之处在于，在存储器部件(或组件)300周围的中间RDL结构200上安装了散热片80，以提高电子装置3的热性能和鲁棒性(robustness)。散热片80例如可以是金属或者非金属材料。根据一个实施例，散热器80可以存储器部件(或组件)300具有环形形状并围绕存储器组件300，但不限于此。散热片80的设置不仅可以提高散热效率，帮助存储器部件(或组件)300、半导体封装CP等部件进行散热，而且增加散热片80之后可以使得电子装置整体的结构完整性更佳，减少不平衡应力，从而提高电子装置的结构稳定性，保证电子装置稳定、可靠的运行。
图4是示出根据本发明的又一实施例的具有堆叠PCB的示例性电子装置4的示意性横截面图，其中相似的区域、层或元件由相似的数字编号或卷标表示。在一些实施例中，电子装置(或装置)4可以用作3D组件，包括分别安装在半导体封装的相对侧上的至少两个垂直堆叠的PCB。如图4所示，同样地，电子装置4包括主PCB组件10，主PCB组件10包括但不限于底部PCB PB和安装在底部PCB PB的上表面S1上的半导体封装CP。在一些实施例中，例如，半导体封装CP可以包括基板100和安装在基板100的上表面100a上的半导体晶粒101(例如逻辑晶粒)。半导体晶粒101可以通过穿透半导体晶粒101的整个厚度的(多个)TSV 110连接到基板100的上表面100a。半导体晶粒101的***侧壁和基板100的上表面100a可以由诸如环氧树脂的模塑料120封装。
根据一个实施例，例如，附加部件103和105可以安装在底部PCB PB的表面上。附加部件103和105可以包括有源或无源组件(或部件)，例如IC芯片、电容器、电阻器或电感器。
在一些实施例中，半导体封装CP可以包括一个或多个逻辑晶粒，包括但不限于中央处理单元(CPU)、图形处理单元(GPU)、片上***(SOC)、现场可程序设计门阵列(FPGA)、微控制器单元(MCU)、电源管理集成电路(PMIC)芯片、射频(RF)芯片、传感器芯片、微机电***(MEMS))晶粒、信号处理晶粒(例如，数字信号处理(DSP)晶粒)等，或它们的任何组合。
根据一个实施例，例如，基板100可以是布线基板并且可以由本领域已知的诸如BT层压板和/或积层膜的聚合物材料形成。在一些实施例中，基板100可以是包括介电层和导电层的RDL基板，其与传统封装基板相比具有更薄的厚度。应当理解，基板100可以是单层或多层结构。
例如，根据一个实施例，基板100可以包括设置在基板100的上表面100a上或在基板100的上表面100a附近的(多个)连接焊盘100p。根据一个实施例，例如，基板100可以包括(多个)导电迹线100t将(多个)连接垫(或连接焊盘)100p与分布在基板100的底表面100b上或在基板100的底表面100b附近的(多个)球垫(或焊球焊盘、焊球垫)100s互连。焊球SB分别设置在球垫100s上。在一些实施例中，可以使用SMT将至少一个无源器件PE安装在基板100的底表面100b上。
根据一个实施例，半导体晶粒101安装在基板100的上表面100a上。根据一个实施例，半导体晶粒101具有上表面(或有源表面)101a和无源后表面101b。诸如晶体管的电路元件被制造在半导体晶粒101的上表面101a上或在半导体晶粒101的上表面101a附近。根据一个实施例，半导体晶粒101的无源后表面101b可以通过使用本领域已知的方法(例如，SMT或粘附)耦接到基板100的上表面100a。即，半导体晶粒101以“面朝上”配置安装在基板100的上表面100a上。根据一个实施例，半导体晶粒101可以通过TSV 110电连接到基板100和基板100的底表面100b上的焊球SB，TSV 110主要用于半导体晶粒101或HBM的电源/接地连接。根据一个实施例，例如，TSV 110可以是用于传输电源或接地信号的电源或接地TSV。
根据一个实施例，同样地，电子装置4包括在半导体晶粒101上的中间RDL结构200。根据一个实施例，中间RDL结构200可以包括介电层210和互连结构220。互连结构220可以是电学的。连接到(多个)RDL焊盘230。根据一个实施例，半导体晶粒101的上表面101a通过诸如微凸块、金属柱等的连接元件BP电连接到中间RDL结构200。根据一个实施例，中间RDL结构200和半导体晶粒101的上表面101a之间的间隙可以用h底部填充材料UF，例如环氧树脂，但不限于此。根据一个实施例，(多个)TMV 122可以设置在模塑料120中。TMV 122可以电连接到中间RDL结构200的互连结构220。
根据一个实施例，存储器封装30直接安装在中间RDL结构200上。存储器组件(或部件)300可以通过导电结构例如凸块或金属柱或焊球等等电性连接元件连接到RDL结构200(例如互连结构220)。根据一个实施例，存储器封装30包括存储器组件(或部件)300，该存储器组件(或部件)300包括HBM，该HBM包括彼此堆叠的(多个)DRAM晶粒301，并且堆叠的DRAM晶粒301通过TSV 310和微凸块BT垂直互连。根据一个实施例，存储器组件300还可以包括DRAM基座302，DRAM基座302可以包括缓冲电路和测试逻辑。在一些实施例中，DRAM基座302可以包括DRAM控制器。根据一个实施例，存储器组件300由模塑料320封装。
根据一个实施例，当从上面看时(俯视时)，存储器组件(或部件)300可以与下面的半导体晶粒101对齐并且设置在半导体晶粒101的中心处或附近。也就是说，存储器组件(或部件)300的中心可以与半导体晶粒101的中心对齐。当从上方观察时(俯视时)，存储器组件(或部件)300与下面的半导体晶粒101完全重叠。根据一些实施例，存储器组件(或部件)300可以不与下面的半导体晶粒101对齐。
根据一个实施例，DRAM基座302电耦接到中间RDL结构200，并且诸如电源或接地的信号可以通过较短的导电路径传输到基板100的底表面100b上的焊球SB，该较短的导电路径至少包括中间RDL结构200的互连结构220、连接元件BP、半导体晶粒101的TSV 110和基板100的导电迹线100t。可选地，一些电源或接地信号可以通过连接元件BP、中间RDL结构200的互连结构220、TMV 122和基板100的导电迹线100t传输到位于基板100的底表面100b上的焊球SB。
根据一个实施例，例如，PCB组件50和PCB 60可以并排方式安装在存储器封装30上。根据一个实施例，例如，PCB组件50和PCB 60可以通过模塑料320中的TMV 322电连接到中间RDL结构200的对应RDL焊盘230。根据一个实施例，例如，PCB组件50可以包括PCB 52和分别安装在PCB52相对侧的部件503和505。本发明实施例中TMV 322例如可以是金属柱、金属通孔、焊球、凸块等等电性连接结构。本实施例提供了不同的电子装置的结构设计，可以满足更多样的设计需求，并且使用模塑料320封装之后电子装置的结构稳定性更好。
图5是示出了根据本发明的又一实施例的具有堆叠PCB的示例性电子装置5的示意性截面图，其中相同的区域、层或元件由相同的数字编号或卷标表示。在一些实施例中，电子装置5可以用作3D组件，包括分别安装在半导体封装的相对侧上的至少两个垂直堆叠的PCB。如图5所示，同样地，电子装置5包括主PCB组件10，主PCB组件10包括但不限于底部PCBPB和安装在底部PCB PB的上表面S1上的半导体封装CP。在一些实施例中，例如，半导体封装CP可以包括基板100和安装在基板100的上表面100a上的半导体晶粒101，例如逻辑晶粒。半导体晶粒101可以经由穿透半导体晶粒101的整个厚度的(多个)TSV 110连接到基板100的上表面100a。半导体晶粒101的***侧壁和基板100的上表面100a可以由诸如环氧树脂的模塑料120封装。
根据一个实施例，例如，附加部件103和105可以安装在底部PCB PB的表面上。附加部件103和105可以包括有源或无源组件(或部件)，例如IC芯片、电容器、电阻器或电感器。
在一些实施例中，半导体封装CP可以包括一个或多个逻辑晶粒，包括但不限于中央处理单元(CPU)、图形处理单元(GPU)、片上***(SOC)、现场可程序设计门阵列(FPGA)、微控制器单元(MCU)、电源管理集成电路(PMIC)芯片、射频(RF)芯片、传感器芯片、微机电***(MEMS))晶粒、信号处理晶粒(例如，数字信号处理(DSP)晶粒)等，或它们的任何组合。
根据一个实施例，例如，基板100可以是布线基板并且可以由本领域已知的诸如BT层压板和/或积层膜的聚合物材料形成。在一些实施例中，基板100可以是包括介电层和导电层的RDL基板，与传统封装基板相比，基板100具有更薄的厚度。应当理解，基板100可以是单层或多层结构。
例如，根据一个实施例，基板100可以包括设置在基板100的上表面100a上或在基板100的上表面100a附近的(多个)连接焊盘100p。根据一个实施例，例如，基板100可以包括(多个)导电迹线100t将(多个)连接垫100p与分布在基板100的底表面100b上或在基板100的底表面100b附近的(多个)球垫100s互连。焊球SB分别设置在球垫100s上。在一些实施例中，可以使用SMT将至少一个无源器件PE安装在基板100的底表面100b上。
根据一个实施例，半导体晶粒101以“面朝下”配置安装在基板100的上表面100a上，半导体晶粒101的上表面(或有源表面)101a直接面向基板100。根据一个实施例，半导体晶粒101可以通过TSV 110电连接到基板100和基板100的底表面100b上的焊球SB，TSV 110主要用于半导体晶粒101或HBM的电源/接地连接。根据一个实施例，例如，TSV 110可以是用于传输电源或接地信号的电源或接地TSV。
根据一个实施例，诸如HBM的存储器组件(或部件)300直接安装在半导体晶粒101上。根据一个实施例，存储器组件(或部件)300可以通过诸如微凸块或金属柱的连接元件BM电连接到半导体晶粒101。根据一个实施例，存储器组件(或部件)300可以包括彼此堆叠的(多个)DRAM晶粒301，堆叠的DRAM晶粒301通过TSV 310和微凸块BT垂直互连。根据一个实施例，存储器组件(或部件)300还可以包括DRAM基座302，DRAM基座302可以包括缓冲电路和测试逻辑。在一些实施例中，DRAM基座302可以包括DRAM控制器。根据一个实施例，半导体晶粒101和存储器组件300可以封装在一个统一的模塑料320中。
根据一个实施例，存储器组件300可以从下面的半导体晶粒101的中心偏移，即，存储器组件300的中心不与半导体晶粒101的中心对齐并且偏离半导体晶粒101的中心。在一个实施例中，诸如电源或地的信号可以通过较短的导电路径传输到基板100的底表面100b上的焊球SB，该较短的导电路径包括连接元件BM、半导体晶粒101的TSV 110和基板100的迹线100t。此外，存储器组件(或部件)300与半导体晶粒101之间的电性连接元件BM的数组(或该连接元件BM的群组)的中心位置可以与存储器部件300的中心(沿图1竖直方向的中心)重合，以使HBM的应用中传输效率最大化。而存储器部件300的中心不与半导体晶粒101的中心对齐并且偏离半导体晶粒101的中心可以让半导体晶粒101的无源后表面101b(在其他实施例中(例如“面朝上”的实施例中)可以是半导体晶粒101的有源表面101a)至少部分未由存储器部件(或组件)300遮挡而露出(在俯视方向上)，以避免遮挡半导体晶粒101的散热，避免或减小对半导体晶粒101散热的负面影响，从而提升半导体晶粒101及整个半导体封装及电子装置的散热能力。
根据一个实施例，例如，PCB组件50和PCB 60可以并排方式安装在存储器封装30上。根据一个实施例，例如，PCB组件50和PCB 60可以通过模塑料320中的TMV 322电连接到基板100。根据一个实施例，例如，PCB组件50可以包括PCB 52和分别安装在PCB 52的相对侧的部件503和505。本实施例中存储器组件300与半导体晶粒101直接连接，从而进一步缩短了两者之间的电性连接路径，从而适用于HBM的应用中。此外本实施例中半导体晶粒101和存储器组件300可以封装在一个统一的模塑料320中，不仅制造上更加方便简单，而且可以显著的增加电子装置的结构稳定性，保证电子装置的机械强度，和电子装置稳定可靠的运行。
图6是示出根据本发明的又一实施例的具有堆叠PCB的示例性电子装置6的示意性横截面图，其中相似的区域、层或元件由相似的数字编号或卷标表示。在一些实施例中，电子装置6可以用作3D组件，包括分别安装在半导体封装的相对侧上的至少两个垂直堆叠的PCB。
如图6所示，电子装置6包括主PCB组件10，主PCB组件10包括但不限于底部PCB PB和安装在底部PCB PB的上表面S1上的半导体封装CP。在一些实施例中，例如，半导体封装CP可以包括基板100和安装在基板100的上表面(晶粒附接表面)100a上的半导体晶粒101，例如逻辑晶粒。半导体晶粒101可以包括倒装芯片晶粒、引线接合晶粒或扇出晶粒。半导体晶粒101可以通过诸如凸块或金属柱的(多个)连接元件111连接到基板100的上表面100a，但不限于此。半导体晶粒101和基板100的上表面100a可以由诸如环氧树脂的模塑料120封装。
根据一个实施例，例如，附加部件103和105可以安装在底部PCB PB的表面上。附加部件103和105可以包括有源或无源组件(部件)，例如IC芯片、电容器、电阻器或电感器。尽管半导体晶粒101被显示为尽管以倒装芯片(flip-chip)方式安装在基板100的上表面100a上，但是应当理解，在一些实施例中，半导体晶粒101可以通过使用引线接合(wire-bonding)技术安装在基板100上。在一些实施例中，半导体封装CP可以包括扇出(fan-out)晶粒。
在一些实施例中，半导体封装CP可以包括一个或多个逻辑晶粒，包括但不限于中央处理单元(CPU)、图形处理单元(GPU)、片上***(SOC)、现场可程序设计门阵列(FPGA)、微控制器单元(MCU)、电源管理集成电路(PMIC)芯片、射频(RF)芯片、传感器芯片、微机电***(MEMS))晶粒、信号处理晶粒(例如，数字信号处理(DSP)晶粒)等，或它们的任何组合。
根据一个实施例，例如，基板100可以是布线基板并且可以由聚合物材料形成，例如本领域已知的双马来酰亚胺三嗪(BT)层压板和/或积层膜。在一些实施例中，基板100可以是包括介电层和导电层的重分布层(RDL)基板，并且与传统封装基板相比可以具有更薄的厚度。应当理解，基板100可以是单层或多层结构。
例如，根据一个实施例，基板100可以包括设置在基板100的上表面100a上或在基板100的上表面100a附近的(多个)连接焊盘100p。根据一个实施例，例如，基板100可以包括(多个)导电迹线100t以将(多个)连接垫100p与分布在基板100的底表面100b上或在基板100的底表面100b附近的多个球垫100s互连。焊球SB分别设置在球垫100s上。在一些实施例中，可以使用表面安装技术(SMT)将至少一个无源器件PE安装在基板100的底表面100b上。
根据一个实施例，电子装置6还可以包括在半导体晶粒101上的中间重分布层(RDL)结构200。根据一个实施例，中间RDL结构200可以包括介电层210和互连结构220。互连结构220可以电连接到(多个)RDL焊盘230。根据一个实施例，可以在模塑料120中设置(多个)贯穿模具通孔或穿模通孔(TMV)122。TMV 122可以电连接到互连结构中间RDL结构200的220。
根据一个实施例，例如，PCB组件50和PCB 60可以分别通过连接元件502和602安装在中间RDL结构200的对应RDL焊盘230上。根据一个实施例，例如，PCB组件50可以包括PCB52以及安装在PCB 52的相对侧上的部件503和505。根据一个实施例，例如，部件503和505可以包括存储器设备(或装置)、天线设备(或装置)或射频(radio-frequency，RF)设备(或装置)。根据一个实施例，例如，连接元件502和602可以包括焊球或本领域已知的任何合适的导电接头。根据一个实施例，PCB组件50与PCB 60物理分离并与PCB 60并排设置在中间RDL结构200上。本实施例中连接元件502和/或602通过中间RDL结构200电性连接到半导体封装CP(例如TMV 122、端子122t)，因此连接元件502和/或602的布置位置可以更加灵活，无需必须对准半导体封装CP的导电结构(例如TMV 122、端子122t)布置，提高了设计的灵活性和设计弹性。
本领域的技术人员将容易地观察到，在保持本发明教导的同时，可以做出许多该设备和方法的修改和改变。因此，上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。

Claims (19)

1.一种电子装置，其特征在于，包括：
主印刷电路板(PCB)组件，包括底部PCB和安装在该底部PCB的上表面上的半导体封装，其中该半导体封装包括基板和安装在该基板的上表面上的半导体晶粒，其中该半导体晶粒和该基板的该上表面由模塑料封装；以及
顶部PCB，通过第一连接元件安装在该半导体封装上。
2.如权利要求1所述的电子装置，其特征在于，该半导体晶粒包括倒装芯片晶粒、引线接合晶粒或扇出晶粒。
3.如权利要求1所述的电子装置，其特征在于，该半导体晶粒具有有源表面和耦接到该基板的该上表面的后表面，其中该半导体晶粒包括硅通孔。
4.如权利要求3所述的电子装置，其特征在于，还包括：
中间重分布层(RDL)结构，设置在该半导体晶粒和该顶部PCB之间，其中该半导体晶粒的该有源表面通过第二连接元件直接连接到该中间RDL结构，其中该中间RDL结构包括介电层和互连结构。
5.如权利要求4所述的电子装置，其特征在于，还包括：
存储器部件，安装在该中间RDL结构上并通过该中间RDL结构的该互连结构和该半导体晶粒的该硅通孔电连接到该基板。
6.如权利要求5所述的电子装置，其特征在于，还包括：
散热器，安装在该存储器部件周围的该中间RDL结构上。
7.如权利要求5所述的电子装置，其特征在于，该存储器部件是高带宽存储器(HBM)，包括彼此堆叠的动态随机存取存储器(DRAM)晶粒，该DRAM晶粒通过硅通孔垂直互连。
8.如权利要求1所述的电子装置，其特征在于，还包括：
穿模通孔(TMV)，设置在该模塑料中，其中该TMV穿透该模塑料的整个厚度，从而在该半导体封装的上表面上形成端子。
9.如权利要求8所述的电子装置，其特征在于，该顶部PCB安装在该端子上。
10.如权利要求1所述的电子装置，其特征在于，该基板为重分布层(RDL)基板。
11.如权利要求1所述的电子装置，其特征在于，该顶部PCB包括：
第一PCB和/或第一PCB组件，通过相对应的连接元件安装在该半导体封装上。
12.如权利要求11所述的电子装置，其特征在于，该第一PCB组件包括第二PCB和安装在该第二PCB上的组件。
13.如权利要求12所述的电子装置，其特征在于，该组件包括存储器装置、天线装置或射频装置。
14.一种电子装置，其特征在于，包括：
主印刷电路板(PCB)组件，包括底部PCB和安装在该底部PCB上表面上的半导体封装，其中该半导体封装包括基板、安装在该基板的上表面上的半导体晶粒和安装在该半导体晶粒上的存储器部件；和
顶部PCB，通过第一连接元件安装在该半导体封装上。
15.如权利要求14所述的电子装置，其特征在于，该有源表面直接面对该存储器部件；或者该有源表面直接面对该基板。
16.如权利要求14所述的电子装置，其特征在于，该半导体晶粒和该基板的上表面由第一模塑料封装，并且其中该存储器部件由第二模塑料封装。
17.如权利要求16所述的电子装置，其特征在于，还包括：
第一穿模通孔(TMV)，设置在该第一模塑料中，其中该第一TMV贯穿该第一模塑料的整个厚度。
18.如权利要求17所述的电子装置，其特征在于，还包括：
第二穿模通孔(TMV)，设置在该第二模塑料中，其中该第二TMV贯穿该第二模塑料的整个厚度。
19.如权利要求14所述的电子装置，其特征在于，该半导体晶粒、该存储器部件和该基板的上表面由统一的模塑料封装。
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