CN110783349A - TVS device based on SOI substrate and manufacturing method thereof - Google Patents

TVS device based on SOI substrate and manufacturing method thereof Download PDF

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Publication number
CN110783349A
CN110783349A CN201911234851.1A CN201911234851A CN110783349A CN 110783349 A CN110783349 A CN 110783349A CN 201911234851 A CN201911234851 A CN 201911234851A CN 110783349 A CN110783349 A CN 110783349A
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silicon dioxide
soi substrate
tvs device
groove
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蒋骞苑
苏海伟
赵德益
赵志方
吕海凤
张啸
王允
张彩霞
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Shanghai Wei'an Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes

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Abstract

A TVS device based on SOI substrate and its manufacturing method, the said TVS device basic unit is by the silicon dioxide buried layer and silicon dioxide depth, shallow slot form the isolating layer, the said silicon dioxide buried layer surface has the first silicon dioxide deep groove, the first N-area, N + area, the second silicon dioxide deep groove, the second N-area, NW area and the third silicon dioxide deep groove sequentially, include two structure the same and fall the capacitance diode one, two composed of P +/P-/N-area, and the first, two P + area both sides have silicon dioxide groove to separate; one TVS tube is composed of NW/P + regions. The invention also provides a manufacturing method of the TVS device. The TVS device product greatly reduces the leakage loss of the TVS device during working, has ultra-low capacitance, lower clamping voltage and reduces the internal parasitic resistance, so the clamping voltage is correspondingly low. About 20 percent lower than the conventional product.

Description

TVS device based on SOI substrate and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor device process manufacturing, in particular to a TVS device based on an SOI substrate and a manufacturing method thereof.
Background
The TVS (transient voltage suppressor) device is a clamping overvoltage protection device, and can fix surge voltage at a lower voltage level in a short time, so that a back-end integrated circuit is prevented from being impacted by over-surge voltage and damaged. The TVS device is mainly applied to various interface circuits, such as mobile phones, flat panels, televisions and computer hosts, and is provided with a large number of TVS protection devices. At present, as the integrated circuit IC is continuously developed toward miniaturization, low voltage and low power consumption, the corresponding performance requirements are also provided for the TVS protection device, that is, the clamping voltage of the TVS is required to be as low as possible, and the leakage current and the capacitance cannot be obviously increased.
As in the patent numbers of the applicant: 201510886621.9 relates to a low-leakage low-capacitance TVS array based on SOI substrate and its preparation method, the low-leakage low-capacitance TVS array based on SOI substrate includes: n-type SOI substrate, p + region, n + region, p region, silicon nitride isolation and electrode, wherein the n-type SOI substrate comprises Si substrate and SiO 2The structure comprises three layers of layers and N-type Si, and a highly doped PN junction is formed on a P-type and/or N-type Si substrate through diffusion or ion implantation to form a PN junction region and a TVS region at the center. Compared with the TVS device in the prior art, the low-leakage low-capacitance TVS array based on the SOI substrate effectively reduces the parasitic capacitance and the leakage current of the device, reduces the power consumption of the device and further improves the performance of the device.
Application No.: 201910053040.5 the invention discloses a TVS device chip in the technical field of TVS devices, comprising a package housing, a TVS chip layer, an overcurrent chip layer, a first pin and a second pin, a TVS chip layer and an overcurrent chip layer are arranged in the inner cavity of the packaging shell, the bottom of the TVS chip layer is connected with one end of a first pin through a wiring, the top of the overcurrent chip layer is connected with one end of a second pin through a wiring, through the design of two channels of chips in the novel TVS, one channel of chip can meet the transient voltage clamping protection effect, and when the other channel of chip is in continuous overcurrent, self-disconnection, and through resetting the high molecular polymer in the overcurrent filler, after power failure and fault elimination, the temperature collection is reduced, the state density is increased, the phase change is recovered, and the nano crystal is reduced into a chain-shaped conductive path, so that the TVS device is recovered to a normal state, thereby ensuring that the short circuit of a circuit can not be caused and the fire of the circuit can not be caused.
The TVS device manufactured by the prior art cannot well balance all parameters of the TVS, when clamping voltage is low, leakage current and capacitance are large, power consumption of the whole circuit is increased due to increase of the leakage current, and high-frequency signals are easy to lose in a transmission process due to large capacitance.
Disclosure of Invention
The present invention is to solve the above problems, and the object of the invention is to: a TVS device based on an SOI substrate is provided, which not only has ultra-small leakage and ultra-low capacitance, but also has lower clamping voltage.
Yet another object of the present invention is to: a method for preparing a TVS device based on an SOI substrate is provided.
The invention can be realized by the following technical scheme: a TVS device based on an SOI substrate adopts the SOI substrate, and is characterized in that a basic unit comprises an isolation layer formed by a silicon dioxide buried layer and a silicon dioxide groove, wherein the surface of the silicon dioxide buried layer is provided with a first silicon dioxide deep groove, a first N-region, an N + region, a second silicon dioxide deep groove, a second N-region, an NW region and a third silicon dioxide deep groove in sequence,
the first P-region, the first silicon dioxide shallow groove, the second P-region and the second silicon dioxide shallow groove are doped on the surfaces of the first N-region and the second N-region in parallel, and the first P + region and the second P + region are doped on the surfaces of the first P-region and the second P-region respectively to form a first capacitance reducing diode and a second capacitance reducing diode which have the same structure and are composed of P +/P-/N-regions, and the two sides of the first P + region and the two P + regions are isolated by the silicon dioxide grooves;
a doped third P + region is formed on the surface of the NW region, the NW/third P + region forms a TVS (transient voltage suppressor) tube, the section of the third P + region is larger than the sections of the first and second P + regions, and two sides of the third P + region are isolated by a second silicon dioxide deep groove and a third silicon dioxide shallow groove;
and metal grounding ends are arranged on the upper surfaces of the first P + region and the third P + region, metal IO ends are arranged on the upper surfaces of the N + region and the second P + region, and other parts of the upper surfaces are covered and isolated by a passivation layer.
The invention adopts the SOI substrate, and because of the existence of the isolation layers of the silicon dioxide buried layer, the silicon dioxide deep groove and the shallow groove, the leakage current of the substrate can be thoroughly eliminated, and the leakage loss of the TVS device during the operation is greatly reduced; the two capacitance-reducing diodes I and II have the same structure and are respectively formed by P +/P-/N-forming PN structures, silicon dioxide grooves are arranged on two sides of a P + region for isolation, so that transverse side junctions of the P + region are eliminated, and only a longitudinal junction interface is arranged, so that the capacitance-reducing diodes I and II have small junction areas and small capacitance; the area of the P + region of the TVS tube is larger, and the corresponding area of a junction formed by the TVS tube and the NW region is also larger, so that the TVS tube has strong capability of preventing surge voltage current. On the other hand, the part below the NW region of the TVS tube is isolated by the buried oxide layer, so that the current scattering path is reduced, the internal parasitic resistance is reduced, and therefore, the clamping voltage is correspondingly low.
On the basis of the scheme, the resistivity of the N-region is preferably 50-100 omega cm, and the thickness of the N-layer is 2-8 mu m.
On the basis of the scheme, the depth of the silicon dioxide deep groove is 2-8 mu m, and the width of the silicon dioxide deep groove is 1-2 mu m.
On the basis of the scheme, the depth of the silicon dioxide shallow groove is 0.5-1 mu m, and the width of the silicon dioxide shallow groove is 1-3 mu m.
Based on the scheme, the implantation element of the NW area is phosphorus, and the implantation dosage is 1E 12-1E 13cm -2The implantation energy is 80-120 Ke. .
On the basis of the scheme, the N + region is implanted with elementsPhosphorus or arsenic with an implant dose of 1E 15-1E 16cm -2The implantation energy is 80 to 120 KeV.
On the basis of the scheme, the P-region implantation element is boron, and the implantation dosage is 5E 12-5E 13cm -2The implantation energy is 80-100 KeV, and the depth of the P-junction is less than or equal to that of the silicon dioxide shallow groove.
On the basis of the scheme, the implantation element of the P + region is boron or boron difluoride, and the implantation dosage is 1E 15-1E 16cm -2The implantation energy is 40-50 KeV, and the depth of the P + junction is smaller than that of the silicon dioxide shallow groove.
Meanwhile, the P-region and the N-region are doped lightly, so that the device has a wider space charge region, the capacitance is further reduced, and finally the whole device has the characteristic of ultra-low capacitance.
The invention also provides a preparation method of the TVS device based on the SOI substrate, which comprises the following steps:
step one, using an SOI substrate silicon wafer, preferably selecting N-type resistivity of 50-100 ohm CM, wherein the thickness of a silicon dioxide buried layer is more than 6000 Å, and the thickness of a surface N-layer is 2-8 μm;
coating glue on the front surface of the silicon wafer, photoetching and defining a deep groove area window, etching a deep groove until the deep groove is connected with the silicon dioxide buried layer, enabling the width of the silicon dioxide deep groove to be 1-2 mu m, carrying out silicon dioxide deposition in the deep groove, and removing redundant silicon dioxide on the surface;
etching a shallow groove on the front side of the silicon wafer prepared in the step two, filling silicon dioxide in the shallow groove, and removing redundant silicon dioxide on the surface, wherein the depth of the silicon dioxide shallow groove is 0.5-1 μm, and the width of the silicon dioxide shallow groove is 1-3 μm;
step four, performing NW region implantation on the front surface of the silicon wafer prepared in the step three, wherein the element is phosphorus, and the implantation dosage is 1E 12-1E 13CM -2The injection energy is 80-120 KeV;
fifthly, implanting the N + region into the front surface of the silicon wafer prepared in the fourth step, wherein the element is phosphorus or arsenic, and the implantation dosage is 1E 15-1E 16CM -2The injection energy is 80-120 KeV;
step six, feeding the silicon wafer prepared in the step five into a furnace tube, and carrying out thermal process propulsion, wherein the propulsion time is 30-60 minutes at 1100-1150 ℃, so that an NW region and an N + region are communicated with a silicon dioxide buried layer;
seventhly, the P-implantation element on the front surface of the silicon wafer prepared in the sixth step is boron, and the implantation dosage is 5E 12-5E 13CM -2The injection energy is 80-100 KeV, so that the depth of the P-junction is less than or equal to that of the silicon dioxide shallow groove;
step eight, preparing a P + region on the surface of the silicon wafer prepared in the step seven through photoetching, injection and photoresist removal processes, then performing rapid thermal annealing, activating and injecting impurity ions, wherein the P + injection element is boron or boron difluoride, and the injection dosage is 1E 15-1E 16CM -2The implantation energy is 40-50 KeV, and the depth of the P + region is smaller than that of the silicon dioxide shallow groove;
depositing a metal layer on the silicon wafer prepared in the step eight, etching to form metal IO ends on the surfaces of the N + region and the second P + region, and forming metal grounding ends on the surfaces of the first P + region and the third P + region;
and step ten, carrying out passivation layer deposition on the surface of the silicon chip prepared in the step eight, and forming passivation protection layers on the surfaces of the silicon dioxide deep groove and the silicon dioxide shallow groove after etching to obtain the TVS device based on the SOI substrate.
In the eighth step, the rapid thermal annealing temperature is 920-1020 ℃ and the time is 20-30 seconds.
In the ninth step, the metal is aluminum, and the thickness is 4 μm.
In the step ten, the passivation layer is a silicon dioxide and silicon nitride double-layer structure.
The invention has the advantages that
(1) The invention adopts SOI substrate material, and can thoroughly eliminate substrate leakage current due to the existence of the buried oxide layer and the isolation oxide layer, thereby greatly reducing the leakage loss of the TVS device during operation.
(2) The two capacitance-reducing diodes have the same structure and are composed of P +/P-/N-, silicon dioxide grooves are arranged on two sides of the P + to isolate, so that the side junction is eliminated, and only the bottom surface has a junction interface, so that the capacitance is small, and the capacitance is small. Meanwhile, the P-region and the N-region are doped lightly, so that the device has a wider space charge region, the capacitance is further reduced, and finally the whole device has the characteristic of ultra-low capacitance.
(3) The device structure of the invention has a NW area and an N + area which are contacted with the silicon dioxide buried layer, thereby having larger cross section area, and simultaneously the doping concentration of the NW area and the N + area is far higher than that of the N-area, thereby greatly reducing the transverse on-resistance.
(4) The area of the P + region of the TVS tube is larger, and the corresponding junction area formed by the P + region and the N-region is also larger, so that the TVS tube still has strong capability of preventing surge voltage and current. On the other hand, the buried oxide layer is arranged below the N-region of the TVS tube for isolation, so that the current scattering path is reduced, the internal parasitic resistance is reduced, and the clamping voltage is correspondingly low. About 20 percent lower than the conventional product.
Drawings
FIG. 1 is the smallest basic unit of the present invention;
FIG. 2 is an equivalent circuit of the product of the present invention;
FIG. 3 is a schematic structural diagram of step one;
FIG. 4 is a schematic structural diagram of step two, in which glue coating and photoetching are performed on the front surface of the silicon wafer, namely the N-layer on the surface, a deep groove region is defined, and silicon dioxide deposition is performed in the deep groove;
FIG. 5 is a schematic structural diagram of etching shallow grooves between deep grooves on the front surface of a silicon wafer and filling silicon dioxide in the shallow grooves;
FIG. 6 is a schematic diagram of a structure of an NW region formed on the front surface of the silicon wafer in the fourth step by photolithography, implantation and photoresist removal;
in the fifth step of fig. 7, in another silicon dioxide deep groove region on the front surface of the silicon wafer, an N + region is formed between the silicon dioxide shallow groove and the deep groove by the processes of photoetching, injection, photoresist removal and the like;
fig. 8 is a schematic structural diagram of a sixth step of making the NW region and the N + region communicate with the buried silicon dioxide layer by high-temperature baking;
fig. 9 is a schematic structural diagram of a P-region formed between the silicon dioxide deep trench and the silicon dioxide shallow trench by the processes of photoetching, injection, photoresist removal and the like;
fig. 10, step eight, forming a P + region structure on the surfaces of the P-region and the NW region by photolithography, implantation, photoresist removal, and the like;
in step nine of FIG. 11, a metal is deposited on the P + region on the surface of the N-region and the NW region to form a ground terminal, and a metal is deposited on the surface of the N +, silicon oxide deep trench and the P + region to form an IO terminal.
Detailed Description
A TVS device based on an SOI substrate is disclosed, as shown in figure 1, an SOI substrate 1 is adopted, the basic unit of which is an isolation layer composed of a silicon dioxide buried layer 2 and deep groove silicon dioxide, the surface of the silicon dioxide buried layer is sequentially provided with a first silicon dioxide deep groove 3, a first N-region 4, an N + region 5, a second silicon dioxide deep groove 6, a second N-region 7, an NW region 8 and a third silicon dioxide deep groove 9, wherein,
the thickness of the silicon dioxide buried layer is not less than 6000 Å;
a doped first P-area 41 and a doped first silicon dioxide shallow groove 42 are sequentially arranged on the surface of the first N-area 4, a doped second P-area 71 and a doped second silicon dioxide shallow groove 72 are sequentially arranged on the surface of the second N-area 7, and a doped first P + area 43 and a doped second P + area 73 are respectively formed on the surfaces of the doped first P-area 41 and the doped second P-area 71 to form a first capacitance reducing diode D1 and a second capacitance reducing diode D2 which are formed by PN junctions formed by P +/P-/N-areas, and two sides of the first P + area 43 in the first capacitance reducing diode D1 are isolated by a first silicon dioxide deep groove 3 and a first silicon dioxide groove shallow groove 42; two sides of the second P + region two 73 in the capacitance reducing diode two D2 are isolated by the second silicon dioxide groove deep groove 72 and the second silicon dioxide shallow groove 72;
a doped third P + region 81 is formed on the surface of the NW region 8, the NW/P + region forms a TVS tube, the section of the third P + region 81 is larger than the sections of the first and second P + regions 41 and 71, two sides of the third P + region 81 are isolated by the second shallow silicon dioxide trench 72 and the third deep silicon dioxide trench 9, and the depth of the third P + region 81 is smaller than the depth of the second shallow silicon dioxide trench 72;
the upper surfaces of the first P + region and the third P + region are provided with a first metal grounding end, a second metal grounding end and a third metal grounding end, 44 and 83, and the upper surfaces of the N + region and the second P + region are provided with a metal IO end; a passivation layer is formed on the upper surfaces of the first, second and third silicon dioxide deep trenches 3, 6 and 9 and the first and second silicon dioxide shallow trenches 42 and 72. The product and equivalent circuit are shown in fig. 2: an IO end 10 is led out from the space between the first capacitor-reducing diode, the second capacitor-reducing diode D1 and the D2, the anode of the first capacitor-reducing diode D1 is grounded, and the cathode of the first capacitor-reducing diode D3526 is connected with the anode of the second capacitor-reducing diode D2; the positive electrode of the TVS tube is grounded, and the negative electrode of the TVS tube is connected with the negative electrode of the second capacitance-reducing diode D2.
The product of this example was prepared as follows:
step 1, as shown in FIG. 3, using an SOI substrate 1 with a high surface silicon resistivity, preferably an N-type resistivity of 50-100 ohm CM, and a buried silicon dioxide layer 2 with a thickness of 6000 Å or more to obtain a better isolation effect, wherein the thickness of the surface N-layer is 2-8 μm;
step 2, as shown in fig. 4: gluing and photoetching the front surface of a silicon wafer, defining a deep groove area window, then etching by a dry method to form a deep groove, depositing silicon dioxide in the deep groove, and then removing redundant silicon dioxide on the surface to prepare first, second and third silicon dioxide deep grooves 3, 6 and 9 which are connected with a silicon dioxide buried layer 2 in depth and have groove widths of 1-2 mu m;
step 3, as shown in fig. 5: gluing and photoetching the front side of a silicon wafer, defining a shallow groove area window, then etching by a dry method to form a shallow groove, filling silicon dioxide in the shallow groove, and then removing redundant silicon dioxide on the surface to obtain first and second silicon dioxide shallow grooves 42 and 72 with the depth of 0.5-1 mu m and the width of 1-3 mu m;
step 4, as shown in fig. 6: selectively implanting NW region into the front surface of the silicon wafer by photolithography, implantation, and photoresist removal, wherein the implant element in the NW region is phosphorus, and the implant dose is 1E 12-1E 13CM -2The injection energy is 80-120 KeV;
step 5, as shown in fig. 7: selectively injecting an N + region into the front surface of the silicon wafer by photoetching, injecting, removing photoresist and other technological methods, wherein the injection element of the N + region is phosphorus or arsenic, and the injection dosage is 1E 15-1E 16CM -2The injection energy is 80-120 KeV;
step 6, as shown in fig. 8: and (3) feeding the silicon wafer into a furnace tube, and carrying out thermal process propulsion so that the NW region and the N + region are communicated with the silicon dioxide buried layer. The preferable process condition is 1100-1150 ℃, and the advancing time is 30-60 minutes.
Step 7, as shown in fig. 9: performing surface P-selective implantation by photolithography, implantation, and photoresist removalThe process methods are equal, the P-implantation element is boron, and the implantation dosage is 5E 12-5E 13CM -2The implantation energy is 80-100 KeV, and the depth of the first and second P- regions 41 and 71 is less than or equal to the depth of the first and second silicon dioxide shallow grooves 42 and 72.
Step 8, as shown in fig. 10: performing surface P + selective implantation, performing photoetching, implantation, photoresist removal and other technological methods, then performing rapid thermal annealing, activating and implanting impurity ions, wherein the P + implantation element is boron or boron difluoride, and the implantation dosage is 1E 15-1E 16CM -2The implantation energy is 40-50 KeV, the junction depth of the P + region is smaller than the depth of the first silicon dioxide shallow groove 42 and the second silicon dioxide shallow groove 72, the rapid thermal annealing temperature is 920-1020 ℃, and the time is 20-30 seconds, so that the first P + region 43, the second P + region 73 and the third P + region 81 are obtained;
step 9, as shown in fig. 11: cleaning the surface, depositing metal, and then forming a metal IO terminal 10 and metal grounding terminals I, II, 44, 82 through photoetching and metal etching, wherein the thickness is 4 mu m, and the main component is aluminum;
step 10: and depositing a passivation layer, photoetching and etching to form a passivation protection layer covering the first, second and third silicon dioxide deep grooves 3, 6 and 9 and the first and second silicon dioxide shallow grooves 42 and 72, wherein the passivation layer 11 of the embodiment is formed by a silicon dioxide and silicon nitride double-layer structure.
The TVS device based on the SOI substrate as shown in FIG. 1 is manufactured by the above steps, and comprises two capacitance reducing diodes I, II D1, D2 and a TVS tube, wherein the capacitance reducing diodes are composed of P +/P-/N-, and the TVS tube is formed by NW/P +.
The invention has the following characteristics:
(1) the invention adopts SOI substrate material, and because the buried layer of silicon dioxide and the deep and shallow grooves of silicon dioxide exist as the isolation oxide layer, the leakage current of the substrate can be thoroughly eliminated, and the leakage loss of the TVS device during working is greatly reduced.
(2) The first capacitance reducing diode, the second capacitance reducing diode D1 and the D2 have the same structure and are composed of P +/P-/N-, deep silicon dioxide grooves and shallow silicon dioxide grooves are arranged on two sides of the P + for isolation, so that side junctions of the first capacitance reducing diode and the second capacitance reducing diode are eliminated, and only a junction interface exists in the longitudinal direction, so that the first capacitance reducing diode, the second capacitance reducing diode and the D2 have small junction areas and small capacitances. At the same time, the P-and N-regions have wider space charge regions due to their low doping concentration, i.e., lighter doping, which further reduces capacitance. Finally, the whole device is made to have the characteristic of ultra-low capacitance.
(3) The device structure of the embodiment has the NW area and the N + area which are contacted with the silicon dioxide buried layer 2, so the contact cross section area is larger, and the doping concentration of the NW area and the N + area is far higher than that of the N-area, so the transverse on-resistance can be greatly reduced.
(4) The area of the P + region of the TVS tube is larger than the areas of the first and second P + regions of the first, second D1 and D2, and the corresponding area of the junction formed with the NW region is also larger, so that the invention still has strong capability of preventing surge voltage current. On the other hand, the silicon dioxide buried layer is arranged below the NW area of the TVS tube for isolation, so that the current scattering path is reduced, and the internal parasitic resistance is reduced, therefore, the clamping voltage is correspondingly very low and is about 20% lower than that of the conventional product.
The foregoing is illustrative of the present invention only, and it is to be understood that the invention is not limited to the foregoing embodiments, but is capable of numerous changes, modifications, and equivalents within the spirit and scope of the invention as defined by the appended claims.

Claims (11)

1. A TVS device based on an SOI substrate adopts the SOI substrate, and is characterized in that a basic unit forms an isolation layer by a silicon dioxide buried layer and a silicon dioxide groove, the surface of the silicon dioxide buried layer is sequentially provided with a first silicon dioxide deep groove, a first N-region, an N + region, a second silicon dioxide deep groove, a second N-region, an NW region and a third silicon dioxide deep groove, wherein,
the first P-region, the first silicon dioxide shallow groove, the second P-region and the second silicon dioxide shallow groove are doped on the surfaces of the first N-region and the second N-region in parallel, and the first P + region and the second P + region are doped on the surfaces of the first P-region and the second P-region respectively to form a first capacitance reducing diode and a second capacitance reducing diode which have the same structure and are composed of P +/P-/N-regions, and the two sides of the first P + region and the two P + regions are isolated by the silicon dioxide grooves;
a doped third P + region is formed on the surface of the NW region, the NW/third P + region forms a TVS (transient voltage suppressor) tube, the section of the third P + region is larger than the sections of the first and second P + regions, and two sides of the third P + region are isolated by a second silicon dioxide deep groove and a third silicon dioxide shallow groove;
and metal grounding ends are arranged on the upper surfaces of the first P + region and the third P + region, metal IO ends are arranged on the upper surfaces of the N + region and the second P + region, and other parts of the upper surfaces are covered and isolated by a passivation layer.
2. The SOI substrate-based TVS device of claim 1, wherein the N-region has a preferred resistivity of 50-100 Ω cm, and an N-layer thickness of 2-8 μm.
3. The TVS device based on the SOI substrate of claim 1, wherein the silicon dioxide deep trench has a depth of 2-8 μm and a width of 1-2 μm.
4. The SOI substrate-based TVS device of claim 1, wherein the silicon dioxide shallow trench is 0.5-1 μm deep and 1-3 μm wide.
5. The SOI substrate-based TVS device of claim 1, wherein the NW region implant element is phosphorus with an implant dose of 1E 12-1E 13cm -2The implantation energy is 80-120 Ke.
6. The SOI substrate-based TVS device of claim 1, wherein the N + region implant element is P or As with an implant dose of 1E 15-1E 16cm -2The implantation energy is 80 to 120 KeV.
7. The SOI substrate-based TVS device of claim 1, wherein the P-region implant element is boron with an implant dose of 5E 12-5E 13cm -2The implantation energy is 80-100 KeV, and the depth of the P-junction is less than or equal to that of the silicon dioxide shallow groove.
8. The SOI substrate-based TVS device of claim 1, wherein the P + region implant element is boron or boron difluoride with an implant dose of 1E 15-1E 16cm -2The implantation energy is 40-50 KeV, and the depth of the P + junction is smaller than that of the silicon dioxide shallow groove.
9. A method of fabricating the TVS device based on the SOI substrate as claimed in any one of claims 1 to 7, comprising the steps of:
step one, using an SOI substrate silicon wafer, preferably selecting N-type resistivity of 50-100 ohm CM, wherein the thickness of a silicon dioxide buried layer is more than 6000 Å, and the thickness of a surface N-layer is 2-8 μm;
coating glue on the front surface of the silicon wafer, photoetching and defining a deep groove area window, etching a deep groove until the deep groove is connected with the silicon dioxide buried layer, enabling the width of the silicon dioxide deep groove to be 1-2 mu m, carrying out silicon dioxide deposition in the deep groove, and removing redundant silicon dioxide on the surface;
etching a shallow groove on the front side of the silicon wafer prepared in the step two, filling silicon dioxide in the shallow groove, and removing redundant silicon dioxide on the surface, wherein the depth of the silicon dioxide shallow groove is 0.5-1 μm, and the width of the silicon dioxide shallow groove is 1-3 μm;
step four, performing NW region implantation on the front surface of the silicon wafer prepared in the step three, wherein the element is phosphorus, and the implantation dosage is 1E 12-1E 13CM -2The injection energy is 80-120 KeV;
fifthly, implanting the N + region into the front surface of the silicon wafer prepared in the fourth step, wherein the element is phosphorus or arsenic, and the implantation dosage is 1E 15-1E 16CM -2The injection energy is 80-120 KeV;
step six, feeding the silicon wafer prepared in the step five into a furnace tube, and carrying out thermal process propulsion, wherein the propulsion time is 30-60 minutes at 1100-1150 ℃, so that an NW region and an N + region are communicated with a silicon dioxide buried layer;
seventhly, the P-implantation element on the front surface of the silicon wafer prepared in the sixth step is boron, and the implantation dosage is 5E 12-5E 13CM -2The injection energy is 80-100 KeV, so that the depth of the P-junction is less than or equal to that of the silicon dioxide shallow groove;
step eight, preparing a P + region on the surface of the silicon wafer prepared in the step seven through photoetching, injection and photoresist removal processes, then performing rapid thermal annealing, activating and injecting impurity ions, wherein the P + injection element is boron or boron difluoride, and the injection dosage is 1E 15-1E 16CM -2The implantation energy is 40-50 KeV, and the depth of the P + region is smaller than that of the silicon dioxide shallow groove;
depositing a metal layer on the silicon wafer prepared in the step eight, etching the silicon wafer to form metal IO ends on the surfaces of the N + region and the second P + region, and forming a first metal grounding end and a second metal grounding end on the surfaces of the first P + region and the third P + region;
and step ten, carrying out passivation layer deposition on the surface of the silicon chip prepared in the step nine, forming passivation protection layers on the surfaces of the silicon dioxide deep groove and the silicon dioxide shallow groove after etching, and exposing the metal IO end and the metal grounding ends I and II to obtain the TVS device based on the SOI substrate.
10. The method for preparing a TVS device based on an SOI substrate of claim 8, wherein in the eighth step, the rapid thermal annealing temperature is 920-1020 ℃ for 20-30 seconds.
In the ninth step, the metal is aluminum, and the thickness is 4 μm.
11. The method of claim 8, wherein in the step ten, the passivation layer is a silicon dioxide and silicon nitride double layer structure.
CN201911234851.1A 2019-12-05 2019-12-05 TVS device based on SOI substrate and manufacturing method thereof Pending CN110783349A (en)

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