CN110729359A - 一种薄膜晶体管、显示面板及薄膜晶体管的制作方法 - Google Patents

一种薄膜晶体管、显示面板及薄膜晶体管的制作方法 Download PDF

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CN110729359A
CN110729359A CN201911024849.1A CN201911024849A CN110729359A CN 110729359 A CN110729359 A CN 110729359A CN 201911024849 A CN201911024849 A CN 201911024849A CN 110729359 A CN110729359 A CN 110729359A
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active layer
thin film
film transistor
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谢华飞
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/621,250 priority patent/US11233153B2/en
Priority to PCT/CN2019/116296 priority patent/WO2021077470A1/zh
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Abstract

本发明公开了一种薄膜晶体管、显示面板及薄膜晶体管的制作方法。薄膜晶体管包括从下至上依次层叠设置的基板、栅极层、介电层、有源层、源漏极层；所述栅极层上表面设有复数个加强部；其中，所述加强部用于增大栅极层上表面的面积，使所述栅极层与所述有源层的有效对接面积增大，减小所述薄膜晶体管的宽度和长度，减小所述薄膜晶体管的寄生电容。本发明通过设置所述加强部与所述有源层的有效对接面积增大，使得所述栅极层所占面积减少同时又不影响有源层的通电性，提高了显示面板的穿透率，减少了显示面板的寄生电容，提高了薄膜晶体管和显示面板的性能。

Description

一种薄膜晶体管、显示面板及薄膜晶体管的制作方法
技术领域
本发明涉及显示技术领域，尤其涉及一种顶栅薄膜晶体管的薄膜晶体管、显示面板及薄膜晶体管的制作方法。
背景技术
目前，在薄膜晶体管(TFT)器件中，有源层通过栅极电压调节实现源漏极的导通或断开。栅极可以被认为是控制一个物理栅的开关，栅极与半导体材料的有源层对应设置，在栅极施加电压会吸引有源层的参杂半导体中的电子，随着栅极电压增高，会使半导体中的电子骤然增多，在有源层中形成沟道，从而使得位于有源层两端的源极和漏极导通；通过对栅极施加电压控制形成或者消除沟道，从而允许或者阻碍电子流过。在显示应用中，栅极还具有对有源层遮挡光以减少光对有源层影响的作用。但同时，栅极太宽也会降低薄膜晶体管器件的穿透率并且会增大显示面板的寄生电容，从而降低显示性能。
因此，确有必要来开发一种新型的薄膜晶体管、显示面板及薄膜晶体管的制作方法，来克服现有技术中的缺陷。
发明内容
本发明提供一种薄膜晶体管、显示面板及薄膜晶体管的制作方法，通过改变薄膜晶体管的栅极结构，使得在减少栅极所占面积同时又不影响有源层的通电性，提高了显示面板的穿透率，减少了显示面板的寄生电容，提高了薄膜晶体管和显示面板的性能。
为了实现上述目的，本发明提供一种薄膜晶体管，其包括从下至上依次层叠设置的基板、栅极层、介电层、有源层、源漏极层。具体地讲，所述栅极层设于所述基板上；所述栅极层上表面设有复数个加强部；所述介电层设于所述栅极层上且完全包覆所述栅极层；所述有源层设于所述介电层上且完全包覆所述介电层；所述源漏极层设于所述有源层上且与所述有源层电连接；所述源漏极层包括源电极和漏电极，所述源电极设于所述有源层的一端，所述漏电极设于所述有源层的另一端；其中，所述加强部用于增大所述栅极层上表面的面积，使所述栅极层与所述有源层的有效对接面积增大，减小所述薄膜晶体管的宽度和长度，减小所述薄膜晶体管的寄生电容。
进一步地，所述加强部呈阵列式排布于所述栅极层上。
进一步地，所述加强部呈柱形、条形、网格形中的任一种。
进一步地，所述薄膜晶体管还包括阻挡层，所述阻挡层设于所述有源层上；所述源电极设于所述有源层及所述阻挡层的一端，所述漏电极设于所述有源层及所述阻挡层的另一端。
进一步地，所述加强部呈阵列式排布于所述栅极层上。
进一步地，所述薄膜晶体管还包括钝化层、像素电极，所述钝化层设于所述源漏极层上且完全包覆所述钝化层及所述有源层；所述像素电极设于所述钝化层上且与所述漏电极电连接。
本发明还提供一种薄膜晶体管的制作方法，其包括以下步骤：
提供一基板；
在所述基板上制作一层金属膜并图案化处理形成一栅极层；
在所述栅极层上表面制作复数个加强部；
在所述栅极层上制作一介电层，所述介电层完全包覆所述栅极层；
在所述介电层上制作一有源层，所述有源层完全包覆所述介电层；以及
在所述有源层上制作一层金属膜并图案化处理形成一源漏极层，所述源漏极层与所述有源层电连接；所述源漏极层包括源电极和漏电极，所述源电极设于所述有源层的一端，所述漏电极设于所述有源层的另一端。
进一步地，在所述栅极层上表面制作复数个加强部步骤具体包括：将通孔超薄氧化铝膜模板设置在所述栅极层一侧，用电子束蒸发或物理气相沉积方式通过所述超薄氧化铝膜模板制作所述加强部，再用氢氧化钠溶液将所述超薄氧化铝膜模板刻蚀去除。
进一步地，在所述栅极层上表面制作复数个加强部步骤具体包括：在所述栅极层上涂覆一光阻层，通过曝光显影在所述光阻层上形成通孔，用电子束蒸发或物理气相沉积在所述通孔内制作所述加强部，再清洗去除所述光阻层。
进一步地，在制作所述有源层步骤之后以及在制作所述源漏极层步骤之前还包括：在所述有源层上制作一阻挡层；其中，在制作所述源漏极层步骤中，所述源电极设于所述有源层及所述阻挡层的一端，所述漏电极设于所述有源层及所述阻挡层的另一端。
本发明还提供一种显示面板，其特征在于，包括上述薄膜晶体管。
本发明的有益效果在于，提供一种薄膜晶体管、显示面板及薄膜晶体管的制作方法，通过设置所述加强部与所述有源层的有效对接面积增大，使得所述栅极层所占面积减少同时又不影响有源层的通电性，提高了显示面板的穿透率，减少了显示面板的寄生电容，提高了薄膜晶体管和显示面板的性能。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一实施例中一种阵列基板的结构示意图；
图2为本发明第一实施例中一种阵列基板的制作方法的流程图；
图3为图2中在所述栅极层上表面制作复数个加强部步骤的半成品结构示意图；
图4为本发明第二实施例中一种阵列基板的结构示意图；
图5为本发明第二实施例中一种阵列基板的制作方法的流程图。
图中部件标识如下：
1、基板，2、栅极层，3、介电层，4、有源层，5、源漏极层，
6、钝化层，7、像素电极，8、超薄氧化铝膜模板，9、阻挡层，
21、加强部，51、源电极，52、漏电极，81、第一通孔，
100、薄膜晶体管。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
请参阅图1所示，本发明第一实施例中提供一种薄膜晶体管100，为背沟道刻蚀型(BCE)结构，其包括从下至上依次层叠设置的基板1、栅极层2、介电层3、有源层4、源漏极层5。具体地讲，所述基板1优选为玻璃基板或柔性基板；所述栅极层2设于所述基板1上；所述栅极层2上表面设有复数个加强部21；所述介电层3设于所述栅极层2上且完全包覆所述栅极层2，所述介电层3起到对所述栅极层2绝缘的作用，所述介电层3可为HfO2、SiO2、SiNx和Al2O3等材料；所述有源层4设于所述介电层3上且完全包覆所述介电层3；所述源漏极层5设于所述有源层4上且与所述有源层4电连接；所述源漏极层5包括源电极51和漏电极52，所述源电极51设于所述有源层4的一端，所述漏电极52设于所述有源层4的另一端；其中，所述加强部21用于增大所述栅极层2上表面的面积，使所述栅极层2与所述有源层4的有效对接面积增大，减小所述薄膜晶体管100的宽度和长度，减小所述薄膜晶体管100的寄生电容。本实施例通过设置所述加强部21与所述有源层4的有效对接面积增大，使得所述栅极层2所占面积减少同时又不影响有源层4的通电性，提高了显示面板的穿透率，减少了寄生电容，提高了薄膜晶体管100的性能。
本实施例可以通过调节所述加强部21的数量和所述介电层3的厚度，并可控制所述栅极层2的外接电压对所述有源层4调控，有效保证了薄膜晶体管100的性能。同时，本实施例还可以通过控制所述加强部21的高度来调节所述加强部21与所述有源层4的有效对接面积，从而能够进一步减少所述栅极层2所占面积，减小所述薄膜晶体管100的宽度和长度，在不影响所述有源层4的通电性的同时，提高了显示面板的穿透率，减小所述薄膜晶体管100的寄生电容。
所述有源层4的制作材料包括铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、单晶硅(a-Si)、低温多晶硅(Low Temperature Poly-silicon，LTPS)或低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)中的至少一种。因此，本发明的薄膜晶体管100可推广到非晶硅、IGZO、碳纳米管等多种类型器件和背沟道刻蚀型(BCE)、刻蚀阻挡层(ESL)等多种结构中。
本实施例中，所述加强部21呈阵列式排布于所述栅极层2上，从而增大所述栅极层2与所述有源层4的有效对接面积。
所述加强部21呈柱形、条形、网格形中的任一种。所述加强部21优选为柱形，更优选为圆柱体形，从而能够增大所述栅极层2与所述有源层4的有效对接面积，进一步减少所述栅极层2所占面积。
本实施例中，所述薄膜晶体管100还包括钝化层6和像素电极7，所述钝化层6设于所述源漏极层5上且完全包覆所述钝化层6及所述有源层4。所述钝化层6起到绝缘的作用。所述像素电极7设于所述钝化层6上且与所述漏电极52电连接。通过在所述像素电极7上接通电压，可控制所述栅极层2的电压大小进而对所述有源层4调控，可有效保证薄膜晶体管100的性能。
请参阅图2、图3所示，本发明还提供一种薄膜晶体管100的制作方法，包括以下步骤S1-S6。
S1、提供一基板1；所述基板1优选为玻璃基板或柔性基板，所述柔性基板可以由诸如聚酰亚胺(PI)、聚碳酸酯(PC)、聚醚砜(PES)、聚对苯二甲酸乙二醇醋(PET)、聚萘二甲酸乙二醇醋(PEN)、多芳基化合物(PAR)或玻璃纤维增强塑料(FRP)等聚合物材料形成。
S2、在所述基板1上制作一层金属膜并图案化处理形成一栅极层2；优选以物理气相沉积(PVD)或蒸镀的方式在所述基板1上沉积一层金属膜，再通过光刻胶、光罩等涂膜、曝光、显影、酸液湿刻、洗脱等光刻工艺对所述金属膜图形化得到所述栅极层2。
S3、在所述栅极层2上表面制作复数个加强部21；优选所述加强部21呈阵列式排布于所述栅极层2上；所述加强部21呈柱形、条形、网格形中的任一种。所述加强部21优选为柱形，所述加强部21更优选为圆柱体形，所述加强部21用于增大所述栅极层2上表面的面积，从而能够增大所述加强部21与所述有源层4的有效对接面积，进一步减少所述栅极层2所占面积，减小所述薄膜晶体管100的宽度和长度，减小所述薄膜晶体管100的寄生电容。
S4、在所述栅极层2上制作一介电层3，所述介电层3完全包覆所述栅极层2；优选通过原子层沉积(ALD)或化学气相沉积(CVD)或热氧化金属制作所述介电层3，所述介电层3可为HfO2、SiO2、SiNx和Al2O3等材料。
S5、在所述介电层3上制作一有源层4，所述有源层4完全包覆所述介电层3；优选以喷墨打印或化学气相沉积或物理气相沉积方式制作所述有源层4，再通过涂布光刻胶、光罩曝光、显影、等离子体干刻等工艺对所述有源层4进行图形化。所述有源层4的材料包括但不限于单晶硅、铟镓锌氧化物或碳纳米管。
S6、在所述有源层4上制作一层金属膜并图案化处理形成一源漏极层5，所述源漏极层5与所述有源层4电连接；所述源漏极层5包括源电极51和漏电极52，所述源电极51设于所述有源层4的一端，所述漏电极52设于所述有源层4的另一端。优选以物理气相沉积(PVD)或蒸镀的方式沉积所述金属膜，再通过涂布光阻、曝光、显影、酸液湿刻方式对所述金属膜进行图形化处理得到所述源漏极层5，最后清洗去除光阻。
如图3所示，本实施例中，在所述栅极层2上表面制作复数个加强部21步骤S3具体包括：将超薄氧化铝膜模板8(AAO)设置在所述栅极层2一侧，所述超薄氧化铝膜模板8设有第一通孔81，用电子束蒸发或物理气相沉积(PVD)方式在所述超薄氧化铝膜模板8的第一通孔81内制作所述加强部21，控制沉积时间可调节加强部21的高度，再用氢氧化钠溶液将所述超薄氧化铝膜模板8刻蚀去除。
在其他实施例中，提供另一种制作所述加强部21的方式，使用光阻层(未图示)替代所述超薄氧化铝膜模板8。在所述栅极层2上表面制作复数个加强部21步骤S3具体包括：在所述栅极层2上涂覆一光阻层，通过曝光显影在所述光阻层上形成第二通孔(未图示)，用电子束蒸发或物理气相沉积在所述光阻层的第二通孔内制作所述加强部21，控制沉积时间可调节加强部21的高度，再清洗去除所述光阻层。
上述两种制作所述加强部21的方式的区别在于，第一种方式使用超薄氧化铝膜模板8，另一种方式使用光阻层，所述超薄氧化铝膜模板8和所述光阻层的结构形式相同，具体可参考图3所示结构，所述第二通孔与所述第一通孔81的形状尺寸相同，所述加强部21均通过电子束蒸发或物理气相沉积方式制作在所述第一通孔81或所述第二通孔内。第一种方式用氢氧化钠溶液将所述超薄氧化铝膜模板8刻蚀去除,另一种方式用清洗方式去除所述光阻层。两种方式均可通过控制所述加强部21的沉积时间可调节所述加强部21的高度。
实施例2
请参阅图4所示，在第二实施例中包括第一实施例中全部的技术特征，其区别在于，第二实施例中的所述薄膜晶体管100为刻蚀阻挡层(ESL)结构，所述薄膜晶体管100还包括阻挡层9，用于保护下方的所述有源层4，所述阻挡层9设于所述有源层4上；所述源电极51设于所述有源层4及所述阻挡层9的一端，所述漏电极52设于所述有源层4及所述阻挡层9的另一端。
在第二实施例中还提供一种薄膜晶体管100的制作方法，其包括实施例1中的步骤S1-S6，具体请参考实施例1的内容及图2，在此不做赘述。
如图5所示，在第二实施例中的薄膜晶体管100的制作方法，在制作所述有源层4步骤S5之后以及在制作所述源漏极层5步骤S6之前还包括：
S51、在所述有源层4上制作一阻挡层9；
其中，在制作所述源漏极层5步骤S5中，所述源电极51设于所述有源层4及所述阻挡层9的一端，所述漏电极52设于所述有源层4及所述阻挡层9的另一端。
本发明还提供一种显示面板，其特征在于，包括上述薄膜晶体管100。
本发明的有益效果在于，提供一种薄膜晶体管100、显示面板及薄膜晶体管100的制作方法，通过设置所述加强部21与所述有源层4的有效对接面积增大，使得所述栅极层2所占面积减少同时又不影响有源层4的通电性，提高了显示面板的穿透率，减少了显示面板的寄生电容，提高了薄膜晶体管100和显示面板的性能。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

1.一种薄膜晶体管，其特征在于，包括：
基板；
栅极层，设于所述基板上；所述栅极层上表面设有复数个加强部；
介电层，设于所述栅极层上且完全包覆所述栅极层；
有源层，设于所述介电层上且完全包覆所述介电层；以及
源漏极层，设于所述有源层上且与所述有源层电连接；所述源漏极层包括源电极和漏电极，所述源电极设于所述有源层的一端，所述漏电极设于所述有源层的另一端；
其中，所述加强部用于增大所述栅极层上表面的面积，使所述栅极层与所述有源层的有效对接面积增大，减小所述薄膜晶体管的宽度和长度，减小所述薄膜晶体管的寄生电容。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述加强部呈阵列式排布于所述栅极层上。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述加强部呈柱形、条形、网格形中的任一种。
4.根据权利要求1所述的薄膜晶体管，其特征在于，还包括
阻挡层，设于所述有源层上；
所述源电极设于所述有源层及所述阻挡层的一端，所述漏电极设于所述有源层及所述阻挡层的另一端。
5.根据权利要求1所述的薄膜晶体管，其特征在于，还包括
钝化层，设于所述源漏极层上且完全包覆所述钝化层及所述有源层；以及
像素电极，设于所述钝化层上且与所述漏电极电连接。
6.一种薄膜晶体管的制作方法，其特征在于，包括步骤：
提供一基板；
在所述基板上制作一层金属膜并图案化处理形成一栅极层；在所述栅极层上表面制作复数个加强部；
在所述栅极层上制作一介电层，所述介电层完全包覆所述栅极层；
在所述介电层上制作一有源层，所述有源层完全包覆所述介电层；以及
在所述有源层上制作一层金属膜并图案化处理形成一源漏极层，所述源漏极层与所述有源层电连接；所述源漏极层包括源电极和漏电极，所述源电极设于所述有源层的一端，所述漏电极设于所述有源层的另一端。
7.根据权利要求6所述的薄膜晶体管的制作方法，其特征在于，在所述栅极层上表面制作复数个加强部步骤具体包括：
将通孔超薄氧化铝膜模板设置在所述栅极层一侧，用电子束蒸发或物理气相沉积方式通过所述超薄氧化铝膜模板制作所述加强部，再用氢氧化钠溶液将所述超薄氧化铝膜模板刻蚀去除。
8.根据权利要求6所述的薄膜晶体管的制作方法，其特征在于，在所述栅极层上表面制作复数个加强部步骤具体包括：
在所述栅极层上涂覆一光阻层，通过曝光显影在所述光阻层上形成通孔，用电子束蒸发或物理气相沉积在所述通孔内制作所述加强部，再清洗去除所述光阻层。
9.根据权利要求6所述的薄膜晶体管的制作方法，在制作所述有源层步骤之后以及在制作所述源漏极层步骤之前还包括：
在所述有源层上制作一阻挡层；
其中，在制作所述源漏极层步骤中，所述源电极设于所述有源层及所述阻挡层的一端，所述漏电极设于所述有源层及所述阻挡层的另一端。
10.一种显示面板，其特征在于，包括如权利要求1-5中任一项所述的薄膜晶体管。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112397579A (zh) * 2020-10-22 2021-02-23 云谷（固安）科技有限公司 显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020091695A (ko) * 2001-05-31 2002-12-06 주식회사 현대 디스플레이 테크놀로지 박막트랜지스터 제조방법
CN105097475A (zh) * 2014-05-13 2015-11-25 中芯国际集成电路制造(上海)有限公司 栅极结构及其形成方法
WO2016123931A1 (zh) * 2015-02-06 2016-08-11 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示基板和显示装置
CN106549041A (zh) * 2016-11-04 2017-03-29 东莞市联洲知识产权运营管理有限公司 一种有效功率高的薄膜晶体管

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6355532B1 (en) * 1999-10-06 2002-03-12 Lsi Logic Corporation Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET
JP4614652B2 (ja) * 2003-11-27 2011-01-19 株式会社半導体エネルギー研究所 薄膜トランジスタの作製方法、及び表示装置の作製方法
JP5665082B2 (ja) * 2008-02-22 2015-02-04 コロラド ステイト ユニバーシティ リサーチ ファウンデーション リチウムイオンバッテリ
US8766367B2 (en) * 2011-06-30 2014-07-01 Palo Alto Research Center Incorporated Textured gate for high current thin film transistors
CN102437196B (zh) * 2011-12-15 2013-04-03 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管的制造方法
CN103762168A (zh) * 2011-12-31 2014-04-30 广东中显科技有限公司 底栅薄膜晶体管的制造方法
TWI495612B (zh) * 2013-01-04 2015-08-11 Univ Nat Chiao Tung 一維鈦金屬奈米結構及其製造方法
CN103199113B (zh) * 2013-03-20 2018-12-25 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置
CN103303861B (zh) * 2013-05-14 2017-04-12 中国科学院上海硅酸盐研究所 三维有序贵金属纳米管阵列电极及其制备方法
KR20150087617A (ko) * 2014-01-22 2015-07-30 삼성디스플레이 주식회사 표시 기판용 박막 트랜지스터, 표시 기판 및 표시 기판의 제조 방법
CN104900709B (zh) * 2015-06-04 2017-11-17 福州大学 一种高性能底栅型tft器件结构及其制备方法
CN105161542A (zh) * 2015-08-06 2015-12-16 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制备方法、液晶面板
CN105280717B (zh) * 2015-09-23 2018-04-20 京东方科技集团股份有限公司 Tft及其制作方法、阵列基板及显示装置
US9899443B2 (en) * 2016-07-22 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package with an image buffer
CN106024909B (zh) * 2016-07-27 2021-01-26 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
JP2020004860A (ja) * 2018-06-28 2020-01-09 堺ディスプレイプロダクト株式会社 薄膜トランジスタ、表示装置及び薄膜トランジスタの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020091695A (ko) * 2001-05-31 2002-12-06 주식회사 현대 디스플레이 테크놀로지 박막트랜지스터 제조방법
CN105097475A (zh) * 2014-05-13 2015-11-25 中芯国际集成电路制造(上海)有限公司 栅极结构及其形成方法
WO2016123931A1 (zh) * 2015-02-06 2016-08-11 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示基板和显示装置
CN106549041A (zh) * 2016-11-04 2017-03-29 东莞市联洲知识产权运营管理有限公司 一种有效功率高的薄膜晶体管

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112397579A (zh) * 2020-10-22 2021-02-23 云谷（固安）科技有限公司 显示面板

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