WO2016115824A1 - 薄膜晶体管、阵列基板及其制作方法 - Google Patents

薄膜晶体管、阵列基板及其制作方法 Download PDF

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WO2016115824A1
WO2016115824A1 PCT/CN2015/082346 CN2015082346W WO2016115824A1 WO 2016115824 A1 WO2016115824 A1 WO 2016115824A1 CN 2015082346 W CN2015082346 W CN 2015082346W WO 2016115824 A1 WO2016115824 A1 WO 2016115824A1
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thin film
film transistor
drain
array substrate
source
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PCT/CN2015/082346
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English (en)
French (fr)
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史高飞
刘天真
宋洁
王一军
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US14/892,569 priority Critical patent/US9786791B2/en
Publication of WO2016115824A1 publication Critical patent/WO2016115824A1/zh

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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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Definitions

  • Embodiments of the present invention relate to a display device, and more particularly to a thin film transistor, an array substrate, a display device, and a method of fabricating a thin film transistor and an array substrate.
  • TFTs Thin Film Transistors
  • LCDs liquid crystal displays
  • OLED organic light emitting diode
  • AMOLEDs Active Matrix Organic Light Emitting Diodes
  • a metal oxide such as a Ga-In-Zn-O (IGZO) film has been developed as an active layer of a TFT, and the mobility of the metal oxide is several tens of times that of the amorphous silicon layer, and is excellent.
  • the semiconductor characteristics can greatly improve the charge and discharge rate of the TFT electrode, improve the response speed of the pixel, achieve a faster refresh rate, and significantly improve the line scan rate of the pixel.
  • a thin film transistor formed of an active layer by IGZO generally has an etch barrier layer, that is, an insulating layer needs to be deposited thereon after forming an IGZO active layer, in order to protect the metal oxide during subsequent etching of the source and drain metal electrodes.
  • the IGZO layer is not destroyed, thereby improving the performance of the TFT having the metal oxide IGZO, and thus an additional photolithography process is required to form the etch barrier layer, which increases the fabrication process of the TFT.
  • Embodiments of the present invention provide a thin film transistor, an array substrate, a display device, and a method of fabricating a thin film transistor and an array substrate, which can simplify the fabrication process of the thin film transistor, improve the performance of the thin film transistor, and reduce the size of the channel region.
  • a thin film transistor is provided, the active layer of which is made of a metal oxide material, and the source and the drain of the thin film transistor are made of graphite thin or nano silver wire. to make.
  • a thin film transistor has a source and a drain which are both made of graphite thin or nano silver wires by using an inkjet printing process.
  • a gate of the thin film transistor is also made of graphite thin or nano silver wire.
  • an array substrate comprising a plurality of thin film transistors according to various embodiments described above.
  • An array substrate according to an embodiment of the present invention further includes a plurality of electrodes, the electrodes and the drain being made of the same material and integrally connected.
  • the electrode is a pixel electrode
  • the array substrate further includes: a passivation layer disposed on the pixel electrode; and a plurality of layers disposed on the passivation layer Common electrode.
  • a method of fabricating a thin film transistor comprising the steps of:
  • a thin film transistor is formed on the substrate, wherein an active layer of the thin film transistor is made of a metal oxide material, and a source and a drain of the thin film transistor are made of a graphite thin or nano silver wire.
  • a method of fabricating a thin film transistor, the step of forming a source and a drain of a thin film transistor from a graphite thin or nano silver wire includes forming the source and drain using an inkjet printing process.
  • a method of fabricating a thin film transistor the step of forming an active layer of the thin film transistor from a metal oxide material includes: oxidizing to an alumina-based binary metal oxide or a zinc oxide-based binary metal
  • the metal oxide is formed by doping at least one of gallium ions, tin ions, indium ions, and cerium ions in the indium oxide-based binary metal oxide.
  • a method of fabricating an array substrate including the method of fabricating the thin film transistor described in the various embodiments above, is provided.
  • a method of fabricating an array substrate the step of forming a source and a drain of a thin film transistor from a graphite thin or nano silver wire further comprises: forming the source and the drain by an inkjet printing process At the same time, a pixel electrode integrally connected to the drain is also formed.
  • a method of fabricating an array substrate the step of forming a source and a drain of a thin film transistor from a graphite thin or nano silver wire further comprises: depositing a transparent conductive layer by inkjet printing, the transparent The conductive layer includes a source, a drain, and a pixel electrode integrally connected to the drain.
  • a method of fabricating an array substrate, the step of forming a thin film transistor on a substrate includes: forming a gate of the thin film transistor and a gate electrode from a graphite thin or nano silver wire by an inkjet printing process Connected grid lines.
  • a display device comprising the array substrate according to the various embodiments.
  • the thin film transistor fabrication process can be simplified and the performance of the thin film transistor can be improved due to the characteristics of the graphite thin or nano silver wire. , reducing the size of the channel region.
  • the aperture ratio of the array substrate and the display device having such a thin film transistor can be improved.
  • FIG. 1 is a partial cross-sectional view of an array substrate in accordance with a first exemplary embodiment of the present invention
  • FIG. 2a-2d are schematic views showing an operation process of fabricating the array substrate shown in Fig. 1;
  • FIG 3 is a partial cross-sectional view of an array substrate in accordance with a second exemplary embodiment of the present invention.
  • a thin film transistor in which a source and a drain of a thin film transistor are both formed by a graphite thinning or nano silver wire by an inkjet printing process, and an active layer of the thin film transistor is Made of metal oxide material. Due to the characteristics of graphite or nano-silver lines, the source and drain of the thin film transistor can be formed by an inkjet printing process without using a complicated patterning process, which simplifies the fabrication process of the thin film transistor and can improve the film. The performance of the transistor reduces the size of the channel region.
  • an array substrate according to an embodiment of the present invention includes a plurality of thin film transistors.
  • the source 40 and the drain 41 of each thin film transistor are both made of graphite or silver nanowire (SNW), which is active Layer 30 is made of a metal oxide material.
  • graphene As a kind of nano material, graphene has good light transmittance and is almost completely transparent; the moving speed of electrons in graphite is much faster than that of electrons in general conductors, and its electron mobility is very high at normal temperature; The resistivity of graphite is very small.
  • the nano silver wire material has good light transmittance, has excellent electrical conductivity of silver, and has a small rate of change in resistance when bent.
  • the graphite thin or nano silver wire can be formed into nanometer-sized fine particles, and can be mixed with deionized water, ethanol or the like as a solvent to form a nano conductive ink, thereby forming a conductive wire having a very small line width by an inkjet printing process. .
  • the source 40 and the drain 41 are both made of graphene or nano silver wire, the graphene or the nano silver wire has good conductivity and light transmittance and can be formed by an inkjet printing process, so that a thin line can be realized.
  • the length of the channel region can be reduced. According to the following on-current (I on ) formula of the thin film transistor:
  • ⁇ is the carrier mobility
  • C i is the parallel plate capacitance per unit area
  • W is the width of the channel region
  • L is the length of the channel region
  • V G is the voltage applied to the gate
  • V th is the threshold Voltage.
  • the gate of the thin film transistor is made of graphite thin or nano silver wire to further improve the performance of the thin film transistor.
  • the active layer of the thin film transistor is made of a metal oxide material such as indium gallium zinc oxide (IGZO) or aluminum gallium tin oxide (AGTO).
  • IGZO indium gallium zinc oxide
  • AGTO aluminum gallium tin oxide
  • the formation of the active layer by using the metal oxide can increase the charge and discharge rate of the pixel electrode in the pixel structure of the thin film transistor, improve the response speed of the pixel, and improve the line scan rate of the pixel.
  • embodiments of the invention are not limited to the active layer being made of a metal oxide.
  • the active layer can be made of a polysilicon film.
  • an array substrate including a plurality of thin film transistors as described in the above embodiments is provided.
  • the size of the display area can be increased, thereby increasing the aperture ratio of the array substrate.
  • the array substrate according to an embodiment of the present invention further includes an electrode 42 which is made of the same material and integrally connected to the drain electrode 41. Since the electrode 42 and the drain 41 are integrally connected, they can be formed in the same inkjet printing process, which can further simplify the manufacturing process and reduce the manufacturing cost.
  • the electrode 42 is a pixel electrode, and the pixel structure further includes: a passivation layer 50 disposed on the pixel electrode; and a common electrode 60 disposed on the passivation layer 50.
  • the pixel electrode may be formed as a plate electrode, and the common electrode may include a plurality of strip electrodes.
  • electrode 42 can be a plate of storage capacitors.
  • the electrode 42 may be a cathode or an anode in the light emitting device.
  • the thin film transistor is a bottom gate thin film transistor, that is, the gate 10 is closer to the substrate 1 with respect to the source 40 and the drain 41.
  • the thin film transistor is a top gate thin film transistor, that is, the gate 10 is further away from the substrate 1 with respect to the source 40 and the drain 41.
  • a display device including the array substrate described in the above embodiments.
  • the array substrate and the color filter substrate may be paired with a liquid crystal material between the array substrate and the color filter substrate to form a liquid crystal display device.
  • the array substrate of the embodiment of the invention may be applied to an OLED display device or an AMOLED display device.
  • These display devices can be any products or components having display functions such as mobile phones, tablets, televisions, displays, notebook computers, digital photo frames, navigators, electronic papers, and the like.
  • a method of fabricating a thin film transistor comprising the steps of: forming a thin film transistor on a substrate 1 wherein the graphite thin or nano silver wire is formed
  • the source 40 and the drain 41 of the thin film transistor, and the active layer 30 of the thin film transistor is made of a metal oxide material.
  • the performance of the thin film transistor can be improved, the size of the channel region can be reduced, and the aperture ratio of the array substrate including the thin film transistor can be improved due to the characteristics of the graphite thin or nano silver line.
  • the step of forming the source 40 and the drain 42 of the thin film transistor from a graphite thin or nano silver wire includes forming the source and drain using an inkjet printing process.
  • the use of an inkjet printing process can reduce the number of reticle used to perform the patterning process relative to the formation of the gate and source using a patterning process.
  • the performance of the active layer made of IGZO is not affected in the process of forming the source and the drain by an inkjet printing process, thereby eliminating the need to provide between the active layer and the source and drain.
  • An etch stop layer simplifies the structure of the thin film transistor.
  • the step of forming the active layer 30 of the thin film transistor from a metal oxide material comprises: to an alumina-based binary metal oxide, a zinc oxide-based binary metal oxide, or an indium oxide-based
  • the metal oxide is doped with at least one of gallium ions, tin ions, indium ions, and cerium ions.
  • the metal oxide may be indium gallium zinc oxide (IGZO) or aluminum gallium tin oxide (AGTO).
  • IGZO indium gallium zinc oxide
  • AGTO aluminum gallium tin oxide
  • a method of fabricating an array substrate including the method of fabricating a thin film transistor described in the various embodiments above, is provided.
  • the size of the display area can be increased, thereby increasing the aperture ratio of the array substrate.
  • the step of forming the source and drain of the thin film transistor from the graphite thin or nano silver wire further comprises: forming the source 41 and the drain 42 by an inkjet printing process, and forming a drain 41 integrally connected electrode 42. Since the electrode 42 and the drain 41 are formed in the same inkjet printing process, the manufacturing process can be further simplified and the manufacturing cost can be reduced.
  • electrode 42 is a pixel electrode.
  • a pattern of the gate electrode 10 and a corresponding gate line (not shown) is formed on the substrate 1. More specifically, a clean substrate 1, such as a glass substrate, a transparent resin substrate, or the like, is prepared, and then the gate 10 is deposited on the substrate 1, and the gate 10 is generally made of Cr, W, Ti, Ta, Mo, Al, Cu, or the like. The metal and its alloy material are fabricated, and then the gate electrode 10 and the corresponding gate line are obtained by performing a first patterning process including a process of coating photoresist, exposure, development, and etching.
  • the gate and gate lines connected to the gate are formed from graphite or nano-silver lines using an inkjet printing process to further enhance the performance of the thin film transistor.
  • a gate insulating layer 20 is formed on the substrate 1 on which the gate electrode 10 and the gate line pattern are formed; more specifically, plasma enhanced chemistry is performed on the substrate 1 on which the gate electrode 10 and the gate line pattern are formed.
  • a gate insulating layer 20 is deposited by a vapor deposition (PECVD) method.
  • PECVD vapor deposition
  • An oxide, a nitride or an oxynitride compound such as SiO 2 or SiN x material may be used to form the gate insulating layer 20, and the corresponding reaction gas may be a mixed gas of SiH 4 , NH 3 , and N 2 .
  • the active layer 30 is formed on the gate insulating layer 20 at a position corresponding to the gate electrode 10. More specifically, a layer of IGZO metal oxide semiconductor material is deposited on the gate insulating layer 20 at a position corresponding to the gate electrode 10, by performing a second patterning process including coating photoresist, exposure, development, and etching. The process results in an active layer 30 comprising a channel region.
  • a source electrode 40, a drain electrode 41, and a pixel electrode 42 connected to the drain electrode 41 are formed on the active layer 30. More specifically, a transparent conductive layer is deposited by a method of inkjet printing on the substrate 1 on which the active layer 30 is formed, the transparent conductive layer including a source electrode 40, a drain electrode 41, and an electrode 42 integrally connected to the drain electrode.
  • a transparent conductive layer is deposited by a method of inkjet printing on the substrate 1 on which the active layer 30 is formed, the transparent conductive layer including a source electrode 40, a drain electrode 41, and an electrode 42 integrally connected to the drain electrode.
  • graphite thin or nano silver wires are utilized as the material for inkjet printing, and graphite thin or nano silver wires are nanoscale particles.
  • the source 40, the drain 41, and the electrode 42 are formed by curing.
  • the passivation layer 50 is covered on the source 40, the drain 41, and the electrode 42. More specifically, the passivation layer 50 is deposited by a PECVD method on the substrate 1 on which the source electrode 40, the drain electrode 41, and the electrode 42 are formed.
  • the passivation layer 50 may be formed of an oxide, a nitride or an oxynitride compound, such as a SiO 2 or SiN x material, and the corresponding reaction gas may be a mixed gas of SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , A mixed gas of N 2 .
  • a via is formed in the passivation layer 50 by performing a third patterning process including coating photoresist, exposure, development, and etching on the passivation layer 50 so as to be on the peripheral line. Electrical connection between the metal layer of the source or drain of the other thin film transistor (not shown) and the common electrode layer 60.
  • a common electrode 60 is formed on the passivation layer 50. More specifically, a thickness transparent conductive layer is deposited by sputtering or thermal evaporation on the substrate 1 on which the passivation layer 50 pattern is formed.
  • the transparent conductive layer is generally made of a conductive material such as indium tin oxide, indium zinc oxide or aluminum zinc oxide.
  • the common electrode 60 is formed in the pixel region by performing a fourth patterning process including a process of coating photoresist, exposure, development, and etching on the transparent conductive layer.
  • the common electrode 60 is formed in a plurality of strip structures to drive the deflection of the liquid crystal located above the common electrode by applying an electric field between the electrode 42 as the pixel electrode and the common electrode 60.
  • a method of fabricating an array substrate is performed by using an inkjet printing process using graphite thin or nano silver wires to form a source, a drain, and an electrode.
  • the source, the drain and the electrode are formed by an inkjet printing process, and an etch stop layer is not required between the active layer made of IGZO and the source and the drain, which reduces the patterning process and reduces the number of layers.
  • the step of forming a thin film transistor on the substrate includes: forming a source 140, a drain 141, and a pixel electrode 142 connected to the drain 141 on the substrate 1; An active layer 130 is formed on the source 140 and the drain 141; a gate insulating layer 120 is formed on the substrate 1 on which the active layer 130 is formed; and a gate is formed on the gate insulating layer 120 at a position corresponding to the active layer 130 Pole 110; at the gate The passivation layer 150 is overcoated 110; and a common electrode 60 is formed on the passivation layer 150.
  • the gate 110 is formed from graphite or nano-silver lines using an inkjet printing process.
  • the metal oxide semiconductor IGZO is irradiated with a light beam having a wavelength of 420 nm or more, the IV curve of the active layer thin film transistor including the IGZO is very stable, and substantially no photogenerated carriers are generated to affect the TFT electricity. Therefore, the structure of the thin film transistor based on the IGZO-based active layer can adopt the top gate type structure shown in FIG. 3, and a channel region having a smaller length can be formed. According to the above-described on-current formula, for the same amount of on-current, if the length of the channel region becomes smaller, the width of the channel region can be made smaller, thereby reducing the size of the thin film transistor and improving the pixel structure.
  • the aperture ratio for the same amount of on-current, if the length of the channel region becomes smaller, the width of the channel region can be made smaller, thereby reducing the size of the thin film transistor and improving the pixel structure.
  • the thin film transistor, the pixel structure, the array substrate, the display device, and the method of fabricating the array substrate according to the above embodiments of the present invention it is not necessary to provide an etching between the active layer made of IGZO and the source and the drain.
  • the barrier layer reduces the patterning process, simplifies the fabrication process of the thin film transistor, reduces the manufacturing cost, improves the performance of the thin film transistor, reduces the size of the channel region, and improves the pixel structure, the array substrate and the like having the thin film transistor.
  • the aperture ratio of the display device has a better display effect.

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Abstract

提供一种薄膜晶体管、阵列基板、显示装置、及薄膜晶体管和阵列基板的制作方法。薄膜晶体管的源极（40）和漏极（41）都由石墨稀或者纳米银线制成，薄膜晶体管的有源层（30）由金属氧化物材料制成。采用喷墨打印工艺形成所述源极（40）和漏极（41）。由于石墨稀或者纳米银线的特性，可以简化薄膜晶体管的制作工艺，可以提高薄膜晶体管的性能，降低沟道区域的尺寸。另外，可以提高具有这种薄膜晶体管的阵列基板和显示装置的开口率。

Description

薄膜晶体管、阵列基板及其制作方法
本申请要求于2015年1月22日递交中国专利局的、申请号为201510032732.3的中国专利申请的权益，该申请的全部公开内容以引用方式并入本文。
技术领域
本发明的实施例涉及一种显示装置，尤其涉及一种薄膜晶体管、阵列基板、显示装置、及薄膜晶体管和阵列基板的制作方法。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)在诸如液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light Emitting Diode，OLED)显示器、以及主动矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示器之类的平面显示装置中用作开关元件。例如，在常规的LCD中，TFT的沟道层主要由非晶硅层形成，其迁移率较低。随着显示器变得更大，对显示器的分辨率和高频驱动性能的要求越来越高，由此需要提高TFT的沟道层的迁移率。
目前已研发出利用金属氧化物，例如，Ga-In-Zn-O(IGZO)薄膜作为TFT的有源层，金属氧化物的迁移率是非晶硅层的迁移率的几十倍，表现出优良的半导体特性，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，显著提高像素的行扫描速率。
在由IGZO形成有源层的薄膜晶体管一般具有刻蚀阻挡层，即在形成IGZO有源层后需要在其上沉积一层绝缘层，以期在随后的刻蚀源、漏金属电极时保护金属氧化物IGZO层不被破坏，从而提高具有金属氧化物IGZO的TFT的性能，因而这样需要一次额外的光刻工艺形成刻蚀阻挡层，增加了TFT的制作工艺流程。
发明内容
本发明的实施例提供一种薄膜晶体管、阵列基板、显示装置、及薄膜晶体管和阵列基板的制作方法，可以简化薄膜晶体管的制作工艺，可以提高薄膜晶体管的性能，降低沟道区域的尺寸。
根据本发明一个发明的实施例，提供一种薄膜晶体管，所述薄膜晶体管的有源层由金属氧化物材料制成，所述薄膜晶体管的源极和漏极均由石墨稀或者纳米银线制成。
根据本发明一种实施例的薄膜晶体管，所述薄膜晶体管的源极和漏极均通过采用喷墨打印工艺由石墨稀或者纳米银线制成。
根据本发明一种实施例的薄膜晶体管，所述薄膜晶体管的栅极也由石墨稀或者纳米银线制成。
根据本发明另一方面的实施例，提供一种阵列基板，包括多个根据上述各种实施例所述的薄膜晶体管。
根据本发明一种实施例的阵列基板还包括多个电极，所述电极和所述漏极由相同的材料制成并一体连接。
根据本发明一种实施例的阵列基板，所述电极为像素电极，并且所述阵列基板还包括：设置在所述像素电极上的钝化层；以及设置在所述钝化层上的多个公共电极。
根据本发明再一方面的实施例，提供一种制作薄膜晶体管的方法，包括如下步骤：
在基板上形成薄膜晶体管，其中，由金属氧化物材料制成所述薄膜晶体管的有源层，并且由石墨稀或者纳米银线制成薄膜晶体管的源极和漏极。
根据本发明一种实施例的制作薄膜晶体管的方法，由石墨稀或者纳米银线制成薄膜晶体管的源极和漏极的步骤包括：采用喷墨打印工艺形成所述源极和漏极。
根据本发明一种实施例的制作薄膜晶体管的方法，由金属氧化物材料制成所述薄膜晶体管的有源层的步骤包括：向氧化铝系二元金属氧化物、氧化锌系二元金属氧化物或者氧化铟系二元金属氧化物中掺杂镓离子、锡离子、铟离子和铪离子中的至少一种而形成所述金属氧化物。
根据本发明再进一步方面的实施例，提供一种制作阵列基板的方法，包括上述各种实施例所述的薄膜晶体管的制作方法。
根据本发明一种实施例的制作阵列基板的方法，由石墨稀或者纳米银线制成薄膜晶体管的源极和漏极的步骤还包括：采用喷墨打印工艺形成所述源极和漏极的同时，还形成与所述漏极一体连接的像素电极。
根据本发明一种实施例的制作阵列基板的方法，由石墨稀或者纳米银线制成薄膜晶体管的源极和漏极的步骤还包括：通过喷墨打印的方法沉积透明导电层，所述透明导电层包括源极、漏极和与漏极一体连接的像素电极。
根据本发明一种实施例的制作阵列基板的方法，在基板上形成薄膜晶体管的步骤包括：采用喷墨打印工艺由石墨稀或者纳米银线形成所述薄膜晶体管的栅极和与所述栅极连接的栅线。
根据本发明再进一步方面的实施例，提供一种显示装置，包括根据所述各种实施例所述的阵列基板。
根据本发明上述实施例的薄膜晶体管、阵列基板、显示装置、及薄膜晶体管和阵列基板的制作方法，由于石墨稀或者纳米银线的特性，可以简化薄膜晶体管的制作工艺，可以提高薄膜晶体管的性能，降低沟道区域的尺寸。另外，可以提高具有这种薄膜晶体管的阵列基板和显示装置的开口率。
附图说明
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明，其中：
图1是根据本发明的第一种示例性实施例的阵列基板的局部剖视图；
图2a-2d是示出制作图1所示的阵列基板的操作过程示意图；以及
图3是根据本发明的第二种示例性实施例的阵列基板的局部剖视图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。
根据本发明总体上的发明构思，提供一种薄膜晶体管，所述薄膜晶体管的源极和漏极都由石墨稀或者纳米银线通过喷墨打印工艺制成，所述薄膜晶体管的有源层由金属氧化物材料制成。由于石墨稀或者纳米银线的特性，可以采用喷墨打印工艺制成薄膜晶体管的源极和漏极，而不须采用较为复杂的构图工艺，这样，可以简化薄膜晶体管的制作工艺，可以提高薄膜晶体管的性能，降低沟道区域的尺寸。
在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
图1是根据本发明的第一种示例性实施例的阵列基板的局部剖视图。参见图1，根据本发明实施例的阵列基板包括多个薄膜晶体管。在根据本发明一个方面的实施例中，每个薄膜晶体管的源极40和漏极41都由石墨稀(Graphene)或者纳米银线(SNW，silvernano wire)制成，所述薄膜晶体管的有源层30由金属氧化物材料制成。
作为一种纳米材料，石墨烯具有良好的透光率，几乎是完全透明的；石墨稀中电子的运动速度远超电子在一般导体中的运动速度，常温下其电子迁移率非常高；而且，石墨稀的电阻率非常小。纳米银线材料具有良好的透光率，具有银优良的导电性，而且在弯曲时电阻变化率较小。特别是，石墨稀或者纳米银线可以形成为纳米级的细微颗粒，能够以去离子水、乙醇等为溶剂混合形成纳米导电墨水，由此可以采用喷墨打印工艺形成线宽非常小的导电丝线。
由于源极40和漏极41都由石墨烯或者纳米银线制成，石墨烯或者纳米银线具有良好的导电性和透光性并可以采用喷墨打印工艺形成导电层，故可以实现细线化，可以降低沟道区域的长度。根据薄膜晶体管的如下导通电流(Ion)公式：
Figure PCTCN2015082346-appb-000001
其中，μ为载流子迁移率，Ci为单位面积的平行板电容，W为沟道区域的宽度，L为沟道区域的长度，VG为施加在栅极的电压，Vth为阈值电压。对于同样大小的导通电流，如果L变小了，W将可以做得更小，因此，降低了薄膜晶体管的尺寸。
在薄膜晶体管的一种实施例中，所述薄膜晶体管的栅极由石墨稀或者纳米银线制成，以进一步提高薄膜晶体管的性能。
在本发明实施例的薄膜晶体管中，薄膜晶体管的有源层由金属氧化物材料，例如铟镓锌氧化物(IGZO)或者铝镓锡氧化物(AGTO)，制成。采用金属氧化物形成有源层，可以提高薄膜晶体管对像素结构中的像素电极的充放电速率，提高像素的响应速度，提高像素的行扫描速率。但本发明的实施例并不局限于有源层由金属氧化物制成。在一种可替换的实施例中，有源层可以由多晶硅薄膜制成。
如图1所示，根据本发明另一方面的实施例，提供一种阵列基板，包括多个如上述实施例所述的薄膜晶体管。在阵列基板的同样大小的显示区域中，由于薄膜晶体管的尺寸降低了，可以增加显示区域的尺寸，从而提高了阵列基板的开口率。
根据本发明一种实施例的阵列基板还包括电极42，所述电极42和薄膜晶体管的漏极41由相同的材料制成并一体连接。由于电极42和漏极41一体连接，可以在同一喷墨打印工艺中形成，这样可以进一步简化制作工艺，降低制作成本。
根据本发明一种实施例，电极42为像素电极，并且像素结构还包括：设置在像素电极上的钝化层50；以及设置在钝化层50上的公共电极60。例如，像素电极可以形成为板式电极，公共电极可以包括多个条形电极。在本发明实施例的像素结构应用于液晶显示器的情况下，在像素电极42与公共电极60之间施加电场，可以驱动位于公共电极上方的液晶(未示出)的偏转。在一种可替换的实施例中，电极42可以是存储电容的一个极板。另外，在本发明实施例的像素结构应用于OLED显示装置或者AMOLED显示装置的情况下，电极42可以是发光组件中的阴极或者阳极。
在图1所示的实施例中，薄膜晶体管为底栅薄膜晶体管，即，栅极10相对于源极40和漏极41更靠近基板1。在图3所示的另一种实施例中，薄膜晶体管为顶栅薄膜晶体管，即，栅极10相对于源极40和漏极41更远离基板1。
根据本发明另一方面的实施例，提供一种显示装置，包括上述实施例所述的阵列基板。例如，可以将该阵列基板与彩膜基板进行对盒，并在阵列基板和彩膜基板之间填充液晶材料，从而形成液晶显示装置。在另外的实施例中，本发明实施例的阵列基板可以应用于OLED显示装置或者AMOLED显示装置。这些显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
根据本发明再进一步方面的实施例，参见图1和2a-2d，提供一种制作薄膜晶体管的方法，包括如下步骤：在基板1上形成薄膜晶体管，其中，由石墨稀或者纳米银线制成薄膜晶体管的源极40和漏极41，并且由金属氧化物材料制成所述薄膜晶体管的有源层30。根据本发明实施例的制作薄膜晶体管的方法，由于石墨稀或者纳米银线的特性，可以提高薄膜晶体管的性能，降低沟道区域的尺寸，从而提高包括这种薄膜晶体管的阵列基板的开口率。
在一种实施例中，由石墨稀或者纳米银线制成薄膜晶体管的源极40和漏极42的步骤包括：采用喷墨打印工艺形成所述源极和漏极。相对于采用构图工艺形成栅极和源极，采用喷墨打印工艺可以减少用于执行构图工艺的掩模板的数量。进一步地，在采用喷墨打印工艺形成所述源极和漏极的过程中不会影响由IGZO制成的有源层的性能，从而不需要在有源层与源极和漏极之间设置一层刻蚀阻挡层，因此简化了薄膜晶体管的结构。
在一种实施例中，由金属氧化物材料制成所述薄膜晶体管的有源层30的步骤包括：向氧化铝系二元金属氧化物、氧化锌系二元金属氧化物或者氧化铟系二元金属氧化物中掺杂镓离子、锡离子、铟离子和铪离子中的至少一种而形成所述金属氧化物。在一种示例性实施例中，金属氧化物可以是铟镓锌氧化物(IGZO)或者铝镓锡氧化物(AGTO)。采用金属氧化物形成有源层，可以提高薄膜晶体管对像素结构中的像素电极的充放电速率，提高像素的响应速度，提高像素的行扫描速率。
根据本发明再进一步方面的实施例，参见图1和2a-2d，提供一种制作阵列基板的方法，包括上述各种实施例所述的制作薄膜晶体管的方法。在阵列基板的同样大小的显示区域中，由于薄膜晶体管的尺寸降低了，可以增加显示区域的尺寸，从而提高了阵列基板的开口率。
在一种实施例中，由石墨稀或者纳米银线制成薄膜晶体管的源极和漏极的步骤还包括：采用喷墨打印工艺形成源极41和漏极42的同时，还形成与漏极41一体连接的电极42。由于电极42和漏极41在同一喷墨打印工艺中形成，这样可以进一步简化制作工艺，降低制作成本。在一种示例性实施例中，电极42为像素电极。
下面参见图1和2a-2d详细描述在基板1上形成阵列基板的步骤。
首先，如图2a所示，在基板1上形成栅极10和相应的栅线(未示出)的图形。更具体地，先准备一清洁的基板1，例如玻璃基板、透明树脂基板等，然后在基板1上沉淀栅极10，栅极10一般由Cr、W、Ti、Ta、Mo、Al、Cu等金属及其合金材料制成，接着通过执行包括涂覆光刻胶、曝光、显影和刻蚀等工艺的第一构图工艺后得到栅极10和相应的栅线。在一种可替换的实施例中，采用喷墨打印工艺由石墨稀或者纳米银线形成所述栅极和与栅极连接的栅线，以进一步提高薄膜晶体管的性能。
之后，如图2a所示，在形成栅极10和栅线图形的基板1上形成栅极绝缘层20；更具体地，在形成栅极10和栅线图形的基板1上通过等离子体增强化学气相沉积(简 称PECVD)方法沉积栅极绝缘层20。可以选用氧化物、氮化物或者氧氮化合物，例如SiO2或SiNx材料，形成栅极绝缘层20，对应的反应气体可以为SiH4、NH3、N2的混合气体。
之后，如图2b所示，在栅极绝缘层20上与栅极10相对应的位置形成有源层30。更具体地，在栅极绝缘层20上与栅极10相对应的位置沉积一层IGZO金属氧化物半导体材料，通过执行包括涂覆光刻胶、曝光、显影和刻蚀等工艺的第二构图工艺得到包括沟道区域的有源层30。
之后，如图2c所示，在有源层30上形成源极40、漏极41、以及与漏极41连接的像素电极42。更具体地，在形成有源层30的基板1上通过喷墨打印的方法沉积透明导电层，所述透明导电层包括源极40、漏极41和与漏极一体连接的电极42。在一种实施例中，利用石墨稀或者纳米银线作为喷墨打印的材料，石墨稀或者纳米银线为纳米级的微粒。喷墨打印之后，通过固化后形成源极40、漏极41和电极42。
之后，如图2d所示，在源极40、漏极41和电极42上覆盖钝化层50。更具体地，在形成源极40、漏极41和电极42的基板1上通过PECVD方法沉积钝化层50。钝化层50可由氧化物、氮化物或者氧氮化合物形成，例如SiO2或SiNx材料，对应的反应气体可以为SiH4、NH3、N2的混合气体或SiH2Cl2、NH3、N2的混合气体。在一种实施例中，通过对钝化层50执行包括涂覆光刻胶、曝光、显影和刻蚀等工艺的第三构图工艺在钝化层50中形成过孔，以便与周边线路上的其它薄膜晶体管(未示出)的源极或者漏极的金属层和公共电极层60之间的电连接。
之后，如图2d所示，在所述钝化层50上形成公共电极60。更具体地，在形成钝化层50图案的基板1上通过溅射或热蒸发的方法沉积厚度透明导电层。透明导电层一般由氧化铟锡、氧化铟锌或氧化铝锌之类的导电材料制成。通过对透明导电层执行包括涂覆光刻胶、曝光、显影和刻蚀等工艺的第四构图工艺而在像素区域形成公共电极60。公共电极60形成为多个条状结构，以便通过在作为像素电极的电极42与公共电极60之间施加电场而驱动位于公共电极上方的液晶的偏转。
根据本发明实施例的制作阵列基板的方法，利用石墨稀或者纳米银线采用喷墨打印工艺形成源极、漏极和电极。这样，采用喷墨打印工艺形成源极、漏极和电极，不需要在由IGZO制成的有源层与源极和漏极之间设置一层刻蚀阻挡层，减少了一次构图工艺，降低了一些导电部件发生接触不良的可能性；可以提高薄膜晶体管的性能，降低沟道区域的尺寸。
参见图3，在薄膜晶体管为顶栅薄膜晶体管的情况下，在基板上形成薄膜晶体管的步骤包括：在基板1上形成源极140、漏极141、以及与漏极141连接的像素电极142；在源极140和漏极141上形成有源层130；在形成有源层130的基板1上形成栅极绝缘层120；在栅极绝缘层120上与有源层130相对应的位置形成栅极110；在栅极 110上覆盖钝化层150；以及在钝化层150上形成公共电极60。在此实施例中，采用喷墨打印工艺由石墨稀或者纳米银线形成栅极110。
本领域的技术人员能够理解，形成图3所示的像素结构的各个层的材料和/或工艺与形成图1所示的像素结构的相应的各个层的材料和/或工艺类似，只是在整个制作步骤中的具体顺序可能不同，在此省略其详细描述。
需要说明的是，由于金属氧化物半导体IGZO在具有420nm以上波长的光束照射时，包括由IGZO制成的有源层薄膜晶体管的I-V曲线非常稳定，基本不会产生光生载流子而影响TFT电性，因此对于基于IGZO的有源层的薄膜晶体管的结构可以采取图3所示的顶栅型结构，能够形成具有更小长度的沟道区域。根据上述导通电流公式，对于同样大小的导通电流，如果沟道区域的长度变小了，沟道区域的宽度将可以做得更小，因此，降低了薄膜晶体管的尺寸，可以提高像素结构的开口率。
根据本发明上述实施例的薄膜晶体管、像素结构、阵列基板、显示装置、及阵列基板的制作方法，不需要在由IGZO制成的有源层与源极和漏极之间设置一层刻蚀阻挡层，减少了一次构图工艺，可以简化薄膜晶体管的制作工艺，降低了制造成本；可以提高薄膜晶体管的性能，降低沟道区域的尺寸；可以提高具有这种薄膜晶体管的像素结构、阵列基板和显示装置的开口率，显示装置具有较好的显示效果。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种薄膜晶体管，其特征在于，所述薄膜晶体管的有源层由金属氧化物材料制成，所述薄膜晶体管的源极和漏极均由石墨稀或者纳米银线制成。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管的源极和漏极均通过采用喷墨打印工艺由石墨稀或者纳米银线制成。
  3. 根据权利要求1或2所述的薄膜晶体管，其特征在于，所述薄膜晶体管的栅极也由石墨稀或者纳米银线制成。
  4. 一种阵列基板，其特征在于，包括多个根据权利要求1-3中任一项所述的薄膜晶体管。
  5. 根据权利要求4所述的阵列基板，其特征在于，还包括像素电极，所述像素电极和所述漏极由相同的材料制成并一体连接。
  6. 根据权利要求5所述的阵列基板，其特征在于，所述阵列基板还包括：
    设置在所述像素电极上的钝化层；以及
    设置在所述钝化层上的公共电极。
  7. 一种制作薄膜晶体管的方法，其特征在于，包括如下步骤：
    在基板上形成薄膜晶体管，其中，由金属氧化物材料制成所述薄膜晶体管的有源层，并且由石墨稀或者纳米银线制成薄膜晶体管的源极和漏极。
  8. 根据权利要求7所述的制作薄膜晶体管的方法，其特征在于，由石墨稀或者纳米银线制成薄膜晶体管的源极和漏极的步骤包括：
    采用喷墨打印工艺形成所述源极和漏极。
  9. 根据权利要求7或8所述的制作薄膜晶体管的方法，其特征在于，由金属氧化物材料制成所述薄膜晶体管的有源层的步骤包括：
    向氧化铝系二元金属氧化物、氧化锌系二元金属氧化物或者氧化铟系二元金属氧化物中掺杂镓离子、锡离子、铟离子和铪离子中的至少一种而形成所述金属氧化物。
  10. 一种制作阵列基板的方法，其特征在于，包括根据权利要求7-9中的任一项所述的薄膜晶体管的制作方法。
  11. 根据权利要求10所述的方法，其特征在于，由石墨稀或者纳米银线制成薄膜晶体管的源极和漏极的步骤还包括：
    采用喷墨打印工艺形成所述源极和漏极的同时，还形成与所述漏极一体连接的像素电极。
  12. 根据权利要求10所述的方法，其特征在于，由石墨稀或者纳米银线制成薄膜晶体管的源极和漏极的步骤还包括：
    通过喷墨打印的方法沉积透明导电层，所述透明导电层包括源极、漏极和与漏极一体连接的像素电极。
  13. 根据权利要求10所述的制作阵列基板的方法，其特征在于，在基板上形成薄膜晶体管的步骤包括：采用喷墨打印工艺由石墨稀或者纳米银线形成所述薄膜晶体管的栅极和与所述栅极连接的栅线。
  14. 一种显示装置，其特征在于，包括根据权利要求4-6中的任一项所述的阵列基板。
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