CN110729018A - Memory diagnosis data compression method based on dynamic fault mode identification - Google Patents
Memory diagnosis data compression method based on dynamic fault mode identification Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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Abstract
The invention relates to a memory diagnosis data compression method based on dynamic fault mode identification, which comprises the following steps: a memory arrangement; the March algorithm capable of detecting dynamic faults is used for detecting the storage units one by one; identifying a fault mode, and carrying out mode classification on the fault storage unit; determining the constitution of diagnostic data in different modes, wherein the diagnostic data consists of four parts, namely a fault address, a session number, a compression correction code and an effective bit; compressing the diagnostic data; serially outputting or transmitting the diagnostic data to a memory repair module through a port; in the stage of compressing the diagnostic data and outputting, the correction code stored in the addressable memory is read out to the input-output register unit by unit, and then the data in the input-output register is output bit by bit; finally, the diagnostic data including the fail address, the read status, the correction code, and the valid bit is serially output through the input-output port.
Description
Technical Field
The invention belongs to the field of integrated circuit testing, and relates to the compression transmission of diagnostic data in an embedded memory by Built-in Self-Test (BIST) technology.
Background
With the improvement of the microelectronic technology level, the proportion of the system on the chip of the embedded memory is continuously increased; since memory fabrication is very sensitive to process defects, the yield of memory dominates the chip yield. Built-in self-test (BIST) technology is widely used in testing and diagnosing embedded memories in order to guarantee memory yield, BIST providing a simple and low cost method without affecting memory performance. For fault analysis, the BIST circuit typically needs to output diagnostic data to the automatic test equipment. The BIST circuit typically outputs diagnostic data serially due to limitations of the input-output interface of the test circuit. Obviously, because the data is output serially bit by bit, the diagnostic data output is very time consuming. At present, the diagnostic data is a compressed design aiming at static faults, and the test output diagnostic data (PAE) is suspended after the faults are detected.
On the other hand, in the nanoscale RAM, as the number of interconnect layers increases, the probability of occurrence of a resistive open defect becomes high, and the resistive open defect often causes a dynamic failure. The March algorithm is generally applied to detect dynamic faults, continuous multiple read operations are required in the March algorithm, and the PAE method is used for frequently interrupting a test program to output fault diagnosis data, so that redundant output of the diagnosis data is caused. To improve efficiency, elimination of static fault redundancy diagnostic data output by the PAE method was proposed by lujin in 2014 to improve efficiency [1 ]. Joshi improved this by Poorvi k in 2016 [2] and proposed that an address differentiator was added to compress the difference of the failed address while eliminating the static failure redundancy diagnostic data. However, the improved algorithms are implemented based on a single memory unit of the memory, and the row and column fault condition of the memory is not considered. When a row-column fault is encountered, the repeated redundancy of diagnostic data for the same fault greatly reduces output efficiency.
Reference documents:
[1]Hou C S,Li J F,Fu T J.A BIST scheme with the ability of diagnosticdata compression for RAMs[J].IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems,2014,33(12):2020-2024.
[2]Koshy T,Arun C S.Diagnostic data detection of faults in RAM usingdifferent march algorithms with BIST scheme[C]//Emerging Technological Trends(ICETT),International Conference on.IEEE,2016:1-6.
disclosure of Invention
In view of the above problems, the present invention provides a memory diagnostic data compression method based on identifying dynamic failure modes. The invention can obviously improve the output efficiency of the diagnosis data by only adding one addressable memory and changing the output flow of the diagnosis data. The technical scheme of the invention is as follows:
a method of memory diagnostic data compression based on identifying dynamic failure modes, comprising:
the method comprises the following steps: the memory is composed of a memory cell array, and the failure modes of the memory are divided into three types according to whether the memory cells with failures are formed into rows or columns: setting the average number of injected static faults, dynamic faults and the proportion of the static faults to the dynamic faults by a fault row, a fault column and a single fault unit;
step two: the March algorithm capable of detecting dynamic faults is used for detecting the storage units one by one;
step three: and identifying a fault mode, and performing mode classification on the fault storage unit:
and (4) fault row: when the tested memory cell has a fault, testing the next memory cell in the same row, if the next memory cell is the same as the correction code of the tested memory cell, continuing to test the next memory cell until the memory cell with different correction codes appears or the tail of the row is reached;
fault column: the correction codes of the tested memory cell and the next memory cell in the same row are different; testing the memory cells on the same column, wherein the correction code of the upper memory cell is the same as that of the fault memory cell, and the fault memory cell is covered by the earlier fault column; if the correction codes are the same, the next storage unit in the same column is tested, and if the correction codes are the same, the next storage unit is tested continuously until the storage units with different correction codes appear or the tail of the column is reached;
single failed memory cell: when the tested storage unit is not a fault row or a fault column, the tested storage unit is a single fault storage unit;
step four: determining the constitution of diagnostic data in different modes, wherein the diagnostic data consists of four parts, namely a fault address, a session number, a compression correction code and an effective bit;
step five: compressing the diagnostic data; the correction code is temporarily stored in the addressable memory, and the zone bit of the storage unit of the addressable memory is set to be 0 in the compression stage of the correction code; when the first read operation of the March algorithm detects a fault, the generated correction code is stored in a first storage unit 0, and the corresponding flag position is 1; if the subsequent read operation in the March algorithm detects a fault, comparing the new correction code with the correction code stored in the storage unit 0; if the two are the same, the corresponding read state register is set to be 1; otherwise, the counter is increased by 1, and the newly generated correction code is stored in the storage unit 1; executing the process until all the test operations of the March algorithm of the failed storage unit are completed;
step six: serially outputting or transmitting the diagnostic data to a memory repair module through a port; in the stage of compressing the diagnostic data and outputting, the correction code stored in the addressable memory is read out to the input-output register unit by unit, and then the data in the input-output register is output bit by bit; finally, the diagnostic data including the fail address, the read status, the correction code, and the valid bit is serially output through the input-output port.
Due to the adoption of the technical scheme, the invention has the following advantages:
the invention relates to a memory diagnostic data compression design based on dynamic fault mode identification. Compared with the PAE method, the method provided by the invention fully utilizes the difference of the failure modes of the memory and introduces the diagnostic data compressor, thereby improving the output efficiency; compared with the method for eliminating the static fault redundancy diagnosis data, the method provided by the invention overcomes the problem that the diagnosis data is repeatedly output under the same fault, and effectively reduces the time consumption. The method proves that the method is superior to the PAE method in compression ratio and the method for eliminating the static fault redundant diagnosis data through MATLAB simulation.
In order to visually verify that the positioning performance of the method is superior to that of the existing algorithm, positioning error comparison is carried out with static fault redundancy diagnosis data elimination design and differential address compression design. It can be seen from fig. 4 that the improved memory diagnostic data compression design for identifying dynamic failure modes herein has a significant effect of reducing the compression ratio, and the compression effect is significantly better than the other two algorithms.
Drawings
FIG. 1 is a schematic diagram of a memory failure in the present invention.
Fig. 2 is a graph of diagnostic data for different failure modes in the present invention.
FIG. 3 is a simplified block diagram of the diagnostic data compressor of the present invention.
FIG. 4 is a compression ratio comparison chart for different compression designs.
Detailed description of the invention
The invention is further described in detail below with reference to the drawings and examples. The present example is intended to illustrate only one embodiment of the invention and is not intended to limit the scope of the invention. FIG. 1 is a schematic diagram of a memory failure in the present invention. Fig. 2 is a graph of diagnostic data for different failure modes in the present invention. FIG. 3 is a simplified block diagram of the diagnostic data compressor of the present invention. FIG. 4 is a compression ratio comparison chart for different compression designs. The compression ratio of the present invention is measured using the data bit ratio:
CR＝(NsLs+NcLc+NrLr)/(NfLf)
the compression ratio CR is defined as the ratio of the number of bits of diagnostic data to be compressed and output to the number of bits of diagnostic data output by the PAE method. Defining the number of single fault storage units as NsThe number of fail columns and fail rows is NcAnd Nr，Ls、LcAnd LrThe number of diagnostic data bits representing a single faulty memory cell, a faulty row and a faulty column; total number of defective memory cells is NfThe diagnostic data generated by the fault storage unit using the PAE method is about Lf。
The specific implementation process of the method is described as follows:
the method comprises the following steps: memory setting: a model of an 8k multiplied by 16 memory is established by using a 0.58um process library, injected functional faults are set as static faults of fixed 1 and dynamic faults of fixed 1 sensitization operation as 3, the average number of the faults is 7.8, the ratio of the static faults to the dynamic faults is 4:1, and the faults are distributed in a Poisson mode (close to actual fault distribution).
Step two: memory cells are individually tested (read and write operations) using a March algorithm (e.g., March RAW) that can detect dynamic faults.
Step three: and identifying a failure mode. And carrying out pattern classification on the fault storage unit:
and (4) fault row: when the tested memory cell has a fault, testing the next memory cell in the same row (namely, the row address is unchanged, and the column address is added with 1), and if the next memory cell is the same as the correction code of the tested memory cell, continuing to test the next memory cell until a memory cell with a different correction code appears or the tail of the row is reached.
Fault column: the correction codes of the tested memory cell and the next memory cell in the same row are different; testing the memory cells on the same column (namely, the column address is unchanged, and the row address is reduced by 1), wherein the correction code of the upper memory cell is the same as that of the fault memory cell, which indicates that the fault memory cell is covered by the earlier fault column; if the correction codes are the same, the next memory cell in the same column is tested, and if the correction codes are the same, the next memory cell is tested continuously until the memory cell with the different correction codes appears or the column tail is reached.
Single failed memory cell: when the tested memory cell is not a failed row or a failed column, the tested memory cell is a single failed memory cell.
Step four: different patterns of diagnostic data formation are determined. The diagnostic data consists of four parts, namely a fault address, a session number, a compression correction code and a valid bit.
The fault address, session number are the same as the diagnostic data derived by the PAE method. A compressed correction code is a correction code that compresses the same redundant data that some read operations produce. The valid bit is the flag diagnostic data valid for a plurality of consecutive read operations, typically generated for the first read operation in which the March algorithm detects a dynamic fault. For a single failing memory cell, the correction code is typically shorter than the correction code output by the PAE method. The fault row diagnostic data requires the first and last fault cell addresses to be recorded. Since the same row address is provided, only the column address of the last defective cell needs to be stored more. The faulty column diagnostic data only needs to store the row address of the last faulty cell more.
Step five: and (5) compressing the diagnostic data. The correction code is temporarily stored in the addressable memory, and the zone bit of the memory cell of the addressable memory is set to 0 in the compression stage of the correction code. When the first read operation of the March algorithm detects a failure, the resulting correction code is stored in the first memory location 0, with the corresponding flag bit being 1. If a subsequent read operation in the March algorithm detects a failure, the new correction code is compared to the correction code stored in memory location 0. If so, the corresponding read status register is set to 1. Otherwise, the counter is incremented by 1 and the newly generated correction code is stored in the memory unit 1. This process is performed until all test operations of the March algorithm for the failed memory cell are completed.
Step six: the diagnostic data is serially output through the port or delivered to the memory repair module. In the stage of outputting compressed diagnosis data, the correction codes stored in the addressable memory are read out to the input-output register unit by unit, and then the data in the input-output register is output bit by bit. Finally, the diagnostic data including the fail address, the read status, the correction code, and the valid bit is serially output through the input-output port.
Claims (1)
1. A method of memory diagnostic data compression based on identifying dynamic failure modes, comprising:
the method comprises the following steps: the memory is composed of a memory cell array, and the failure modes of the memory are divided into three types according to whether the memory cells with failures are formed into rows or columns: and a fault row, a fault column and a single fault unit, and setting the average number of injected static faults and dynamic faults and the average number of the injected faults and the proportion of the static faults to the dynamic faults.
Step two: the March algorithm capable of detecting dynamic faults is used for detecting the storage units one by one;
step three: and identifying a fault mode, and performing mode classification on the fault storage unit:
and (4) fault row: when the tested memory cell has a fault, testing the next memory cell in the same row, if the next memory cell is the same as the correction code of the tested memory cell, continuing to test the next memory cell until the memory cell with different correction codes appears or the tail of the row is reached;
fault column: the correction codes of the tested memory cell and the next memory cell in the same row are different; testing the memory cells on the same column, wherein the correction code of the upper memory cell is the same as that of the fault memory cell, and the fault memory cell is covered by the earlier fault column; if the correction codes are the same, the next storage unit in the same column is tested, and if the correction codes are the same, the next storage unit is tested continuously until the storage units with different correction codes appear or the tail of the column is reached;
single failed memory cell: when the tested storage unit is not a fault row or a fault column, the tested storage unit is a single fault storage unit;
step four: determining the constitution of diagnostic data in different modes, wherein the diagnostic data consists of four parts, namely a fault address, a session number, a compression correction code and an effective bit;
step five: compressing the diagnostic data; the correction code is temporarily stored in the addressable memory, and the zone bit of the storage unit of the addressable memory is set to be 0 in the compression stage of the correction code; when the first read operation of the March algorithm detects a fault, the generated correction code is stored in a first storage unit 0, and the corresponding flag position is 1; if the subsequent read operation in the March algorithm detects a fault, comparing the new correction code with the correction code stored in the storage unit 0; if the two are the same, the corresponding read state register is set to be 1; otherwise, the counter is increased by 1, and the newly generated correction code is stored in the storage unit 1; executing the process until all the test operations of the March algorithm of the failed storage unit are completed;
step six: serially outputting or transmitting the diagnostic data to a memory repair module through a port; in the stage of compressing the diagnostic data and outputting, the correction code stored in the addressable memory is read out to the input-output register unit by unit, and then the data in the input-output register is output bit by bit; finally, the diagnostic data including the fail address, the read status, the correction code, and the valid bit is serially output through the input-output port.
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| CN112835745A (en) * | 2021-02-09 | 2021-05-25 | 天津易鼎丰动力科技有限公司 | High-reliability storage algorithm of embedded system |
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