CN107039084B - Wafer test method for memory chip with redundant unit - Google Patents
Wafer test method for memory chip with redundant unit Download PDFInfo
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- CN107039084B CN107039084B CN201710116685.XA CN201710116685A CN107039084B CN 107039084 B CN107039084 B CN 107039084B CN 201710116685 A CN201710116685 A CN 201710116685A CN 107039084 B CN107039084 B CN 107039084B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
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Abstract
The invention discloses a wafer test method of a memory chip with a redundancy unit, which comprises the following steps: step one, setting the length of a row address and a column address of a memory storing a failure address in a memory tester according to an array structure of a main area of a memory chip on a wafer and the structure of a redundancy unit; step two, testing the chip units, and storing the test result of each line into a memory for storing the failure address with the same line address after performing OR operation; reading the content of each row in a memory for storing the failure address to obtain the number of failed rows and the row address; and step four, judging whether each failed row in the main area of the memory chip can be repaired or not, and if so, allocating a redundant unit to replace the failed row in the main area of the memory chip. The invention can effectively reduce the test time and the test cost.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit manufacturing process, and more particularly, to a wafer test method for a memory chip with a redundancy unit.
Background
Wafer testing (CP), also called Circuit probe testing, is a process of directly testing chip dies (die) on a wafer (wafer) before packaging, and is used to verify whether each chip meets the product specification.
At present, in order to improve a test yield when a Memory chip (Memory IC) is tested, i.e., when the Memory chip is subjected to a wafer test, a Redundancy unit (Redundancy Sector) is added, and the Redundancy unit can be used for replacing a failure unit (fail bit cell) in a main area (main) of the chip when the failure unit (fail bit cell) is detected, the replacement mode generally includes hardware replacement and software replacement, and a software replacement is a more general method at present.
Testing such chips typically requires a dedicated Memory Tester (Memory Tester) because the Memory Tester may have a special Random Access Memory (RAM) for storing the addresses of failed cells of the chip under test (DUT), commonly referred to as ECR or AFM. The RAM can record the addresses of failure units of each test item accumulation test in the test process, BIT (BIT) addresses of ECR or AFM correspond to BIT addresses of a tested chip one by one in normal use, so that a state diagram (BITMAP) of each BIT chip can be obtained through testing by defining the length of X or Y addresses of the ECR or AFM, then BITMAP address data of each ECR or AFM are read, the addresses of the failure units are calculated through an algorithm, the sum of the number of the failure units and the failure addresses are counted at the end of the process, and the failure units are replaced by redundant units. However, this method needs to repeatedly read BIT MAP and perform arithmetic operation, because reading and arithmetic operation belong to serial operation on the bus, the efficiency of simultaneous testing is not high, if the number of simultaneous testing is high, the testing time will be very long, which causes too high testing cost, so how to reduce the testing time of the chip with redundant unit becomes a great challenge for testing engineers.
Disclosure of Invention
The invention aims to provide a wafer test method of a memory chip with a redundancy unit, which can effectively reduce the test time and reduce the test cost.
In order to solve the above technical problem, the wafer testing method of the memory chip with the redundancy unit provided by the invention comprises the following steps:
step one, setting the length of a row address and a column address of a memory for storing a failure address in a memory tester according to an array structure of a main area of a memory chip on a wafer and a structure of a redundancy unit, wherein the array structure of the main area of the memory chip is an M-row and N-column structure, and M and N are integers; the redundancy unit is of a structure with 1 row and N columns, the length of a row address of the memory for storing the failure address is M, and the length of a column address is 1.
And step two, testing each chip unit of the main area of the memory chip by adopting the memory tester, and storing the test result of each line into the memory storing the failure address with the same line address after performing OR operation.
And step three, reading the content of each row in the memory for storing the failure address to obtain the number of failed rows and the row address.
And step four, judging whether each failed row in the main area of the memory chip can be repaired or not, and if so, allocating the redundant unit to replace the failed row in the main area of the memory chip.
In a further improvement, the memory storing the failing address in the memory tester is an ECR or an AFM.
In a further improvement, the item of testing each chip unit in the main area of the memory chip in the step two comprises more than one time.
A further improvement is that in the second step, a test vector needs to be set in each test performed on each chip unit in the main area of the memory chip, so that row address carry is performed after each row of chip units in the main area of the memory chip is read.
In a further improvement, the performing an or operation on the test result of each row in the step two includes:
and performing OR operation on the test results of the chip units in the same row of each test to obtain a corresponding OR operation result.
And performing OR operation on OR operation results corresponding to items in the same row of different test items to obtain an integral OR operation result.
In a further improvement, the whole or operation result is stored in the memory storing the failure address with the same row address in the second step.
A further improvement is that, in the second step, each chip unit in the main area of the memory chip is tested, the test result of a normal chip unit is "0", the test result of a failed chip unit is "1", when the value stored in the corresponding row in the memory storing the failed address is "1", it indicates that the failed chip unit exists in the row of the main area of the memory chip corresponding to the row address, and when the value stored in the corresponding row in the memory storing the failed address is "0", it indicates that the chip units in the row of the main area of the memory chip corresponding to the row address are all normal.
In a further improvement, in the fourth step, the redundant unit is replaced by a failed row of the main area of the memory chip in a hardware or software replacement mode.
The invention sets the length of the row address and the column address of the memory storing the failure address in the memory tester according to the array structure of the main area of the memory chip and the structure of the redundant unit on the wafer, utilizes the same structure of the redundant unit and the array structure of the main area of the memory chip, and the failure replacement is performed by replacing one row of the array structure of the main area of the memory chip by the redundant unit, so that the memory storing the fail address in the memory tester no longer adopts a structure corresponding to each bit address of the array structure of the main area of the memory chip, instead, only the structure corresponding to the row address of the memory storing the fail address in the memory tester and the row address of the array structure of the main area of the memory chip is adopted, and the length of the column address of the memory storing the fail address in the memory tester is set to 1.
In the wafer test, the tests in the same row obtained by each test are subjected to OR operation and then stored in one row of the memory for storing the failure address, or the result of the OR operation is only one bit, so that the memory for storing the failure address with the row length of 1 can store the final test result.
As can be seen from the test results stored in the memory storing the failure address, the method greatly reduces the memory amount, thereby increasing the use efficiency of the memory storing the failure address, which is usually an ECR or AFM module.
The reduction of the number of the storage results greatly reduces the time for reading the memory storing the failed address when the subsequent redundancy replacement is carried out, namely, only one bit needs to be read for each row, so that the test time can be greatly reduced, the test efficiency is greatly improved, and the time is money in the manufacture of the semiconductor integrated circuit, so the invention can finally greatly reduce the test cost.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is an array structure diagram of a main area of a memory chip on a wafer;
FIG. 2 is a block diagram of a redundancy unit;
FIG. 3 is a flow chart of ECR or AFM reading of a wafer test method for a memory chip with redundant cells of the prior art;
FIG. 4 is a flowchart of a wafer test method for a memory chip with redundancy units according to an embodiment of the present invention;
FIG. 5 is a memory map of an ECR or an AFM corresponding to a wafer test method for a memory chip with a redundancy unit according to an embodiment of the present invention;
fig. 6 is a flowchart of reading the ECR or AFM in the wafer test method for the memory chip with the redundancy unit according to the embodiment of the present invention.
Detailed Description
Firstly, the following description is made on the test mechanism of the existing memory tester for testing the chip with the redundancy function:
testing such chips typically requires a dedicated memory tester because the memory tester may have a special RAM for storing the addresses of failed cells of the chip under test (DUT), commonly referred to as ECR or AFM. As a simple example, as shown in fig. 1, the array structure diagram of the main area of a memory chip on a wafer is shown, where a certain memory chip is composed of 10 units of X address and 8 units of Y address, the X address is defined as a column address, and the Y address is defined as a row address; the unit of the redundant cell is a row, i.e. 10 cells in the X direction and 1 cell in the Y direction, and the structure diagram of the redundant cell is shown in fig. 2. Since the minimum unit of the redundant cell is a row, as long as a cell in a row fails, the row is determined to be failed and repaired with the redundant cell. In an actual test process, the ECR may record the address of a fail cell of each test item accumulation test in the test flow, a graph structure of a test result recorded in the ECR and an array structure diagram of a main area of a memory chip in the conventional method are in one-to-one correspondence, that is, one test result corresponds to one chip unit of the main area of the memory chip, and the graph structure of the test result recorded in the conventional ECR is a BITMAP, so the BITMAP is the same as that shown in fig. 1.
For redundancy replacement, ECR needs to be read, the number and address of corresponding failed cells are found first, and then redundancy replacement is performed, as shown in fig. 3, which is a flow chart of ECR or AFM reading by the existing wafer testing method for memory chips with redundancy cells; it can be seen that, when the graph is read, the Y address, i.e. the row address, is read first, then the X address, i.e. the column address, on the same row is changed, the data of each bit is read, and the data of each bit on the same row is subjected to or operation, after the reading of the same row is finished, the Y address is added to realize the reading of the next cycle, and the reading is finished until the cycle is finished. It can be seen that the test program described in fig. 3 reads the contents stored in each X address ECR according to the Y address, and takes the 8 × 10 array shown in fig. 1 as an example, the chip reads 80 cells from 8 × 10; when coincidence is encountered, the ECR content of each chip needs to be read serially. In the ECR, 0 represents no failure, 1 represents failure, and each row of data needs to be subjected to OR operation after each bit of data is read to obtain the number of failed rows and row addresses, whether the failed rows and the row addresses can be repaired is judged, and if the failed rows and the row addresses can be repaired, a redundant unit is allocated to replace a failed row unit, so that the chips are guaranteed to be good after the test is passed and the chips at the rear-end user position are obtained.
The above is a testing mechanism for testing a chip with a redundancy function by an ECR for a memory tester, but when the capacity of a chip to be tested is large, the content stored by the ECR becomes large, which means that the time for reading the content of the ECR each time is prolonged.
As shown in fig. 4, which is a flowchart of a wafer testing method for a memory chip with a redundancy unit according to an embodiment of the present invention, the wafer testing method for a memory chip with a redundancy unit according to an embodiment of the present invention includes the following steps:
step one, setting the length of a row address and a column address of a memory for storing a failure address in a memory tester according to an array structure of a main area of a memory chip and a structure of a redundancy unit on a wafer, wherein the array structure of the main area of the memory chip is an M-row-N-column structure, M and N are integers, M is the actual row number of the array structure of the main area of the memory chip, and N is the actual column number; referring to fig. 1, in fig. 1, M is 8, N is 9, and row addresses are respectively represented by 0 to 7, and column addresses are respectively represented by 0 to 9.
The redundant unit has a structure of 1 row and N columns, please refer to fig. 2.
The length of the row address and the length of the column address of the memory storing the failing address are M and 1, as shown in fig. 5.
The memory storing the failure address in the memory tester is ECR or AFM, namely the ECR or AFM of the memory tester is used as the memory storing the failure address.
And step two, testing each chip unit of the main area of the memory chip by adopting the memory tester, and storing the test result of each line into the memory storing the failure address with the same line address after performing OR operation.
The items of testing each chip unit of the main area of the memory chip include more than one time. In each test performed on each chip unit in the main area of the memory chip, a test vector needs to be set, so that row address carry is performed after one row of chip units in the main area of the memory chip are read.
The OR operation of the test result of each row comprises the following steps:
and performing OR operation on the test results of the chip units in the same row of each test to obtain a corresponding OR operation result. As shown in fig. 1, the positions of the 3 rd, 4 th and 6 th columns in the 2 nd row are crossed to represent that the corresponding chip units fail, when the memory tester is used for testing, the bits in the same row are tested sequentially, the test result of the normal chip unit is "0", the test result of the failed chip unit is "1", and then the test results are subjected to an or operation, it can be seen that, since 3 failed chip units appear in the second row, if the test result can detect all the 3 failed chip units, the obtained structure is 1, so that the or operation result corresponding to the test item obtained after the or operation of the bits in the 2 nd row is 1.
Generally, the items of the test for each chip unit in the main area of the memory chip include more than one time, and some failed units may pass through some test items, so that the or operation results corresponding to the items in the same row of different test items need to be or-operated to obtain the whole or operation result. Finally, the overall or operation result obtained is: the values of the 2 nd and 5 th rows are 1, and the values of the other rows are 0. And then, storing the whole or operation result into the memory storing the failure address with the same row address to obtain the memory map shown in fig. 5, wherein only 8 rows and 1 columns of memory arrays are needed in fig. 5 to satisfy the storage of the test result, and the one-to-one correspondence relationship between the array structure shown in fig. 1 and the array structure of the main area of the memory chip is no longer needed. In fig. 5, when the value stored in the corresponding row in the memory storing the failing address is "1", it indicates that the failing chip unit exists in the row in the main area of the memory chip corresponding to the row address, and when the value stored in the corresponding row in the memory storing the failing address is "0", it indicates that the chip units in the row in the main area of the memory chip corresponding to the row address are all normal.
Comparing fig. 5 with fig. 1, it can be seen that the method of the embodiment of the present invention greatly reduces the amount of memory, thereby increasing the efficiency of using the memory storing the failed address, which is typically an ECR or AFM module.
And step three, reading the content of each row in the memory for storing the failure address to obtain the number of failed rows and the row address. As shown in fig. 6, which is a flowchart of the ECR or AFM reading in the method for testing a wafer of a memory chip with a redundancy unit according to the embodiment of the present invention, it can be seen that only the Y address needs to be cycled because the X address has only 1 bit, and in the method according to the embodiment of the present invention, the stored value corresponding to each row is the result of the or operation performed on the same row, so that the or operation does not need to be performed on the test result on the same row in the reading flow of the method according to the embodiment of the present invention.
Taking the display structure shown in fig. 1 as an example, the method of the embodiment of the invention can be realized by only 8 times of reading, and the reading is reduced by 72 times compared with the existing method; in addition, the method of the embodiment of the invention also saves a large amount of OR operation time; therefore, the method of the embodiment of the invention can greatly reduce the test time and greatly improve the test efficiency, and the time is money in the manufacture of the semiconductor integrated circuit, so the test cost can be greatly reduced finally. Particularly, when the number of simultaneous tests is increased, the effect of the method provided by the embodiment of the invention on reduction of the test time is more obvious.
And step four, judging whether each failed row in the main area of the memory chip can be repaired or not, and if so, allocating the redundant unit to replace the failed row in the main area of the memory chip. In the method of the embodiment of the invention, the redundant unit is used for replacing the failure row of the main area of the memory chip in a software replacement mode. In other embodiment methods, the redundant unit can replace a failed row of the main area of the memory chip by adopting a hardware replacement mode.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (8)
1. A wafer test method for a memory chip with a redundant unit is characterized by comprising the following steps:
step one, setting the length of a row address and a column address of a memory for storing a failure address in a memory tester according to an array structure of a main area of a memory chip on a wafer and a structure of a redundancy unit, wherein the array structure of the main area of the memory chip is an M-row and N-column structure, and M and N are integers; the redundancy unit is in a structure of 1 row and N columns, the length of a row address of the memory for storing the failure address is M, and the length of a column address is 1;
step two, testing each chip unit of the main area of the memory chip by adopting the memory tester, and storing the test result of each line into the memory storing the failure address with the same line address after performing OR operation;
reading the content of each row in the memory for storing the failure address to obtain a failure row number and a row address;
and step four, judging whether each failed row in the main area of the memory chip can be repaired or not, and if so, allocating the redundant unit to replace the failed row in the main area of the memory chip.
2. The wafer test method of a memory chip with a redundancy unit as claimed in claim 1, wherein: the memory storing the failure address in the memory tester is ECR or AFM.
3. The wafer test method of a memory chip with a redundancy unit as claimed in claim 1, wherein: and in the second step, the items of testing each chip unit in the main area of the memory chip are more than once.
4. The wafer test method of a memory chip with a redundancy unit according to claim 3, wherein: and step two, setting a test vector in each test of each chip unit in the main area of the memory chip, so that row address carry is carried out after one row of chip units in the main area of the memory chip are read.
5. The wafer test method of a memory chip with a redundancy unit as claimed in claim 4, wherein: in the second step, the performing or operation on the test result of each row comprises:
carrying out OR operation on the test results of the chip units in the same row of each test to obtain a corresponding OR operation result;
and performing OR operation on OR operation results corresponding to items in the same row of different test items to obtain an integral OR operation result.
6. The wafer test method of a memory chip with a redundancy unit as claimed in claim 5, wherein: and in the second step, the whole OR operation result is stored into the memory for storing the failure address with the same row address.
7. The wafer test method of a memory chip with a redundancy unit according to claim 1, 5 or 6, wherein: and step two, testing each chip unit in the main area of the memory chip, wherein the test result of a normal chip unit is '0', the test result of a failed chip unit is '1', when the value stored in the row corresponding to the memory storing the failed address is '1', the failed chip unit exists in the row of the main area of the memory chip corresponding to the row address, and when the value stored in the row corresponding to the memory storing the failed address is '0', the chip units in the row of the main area of the memory chip corresponding to the row address are all normal.
8. The wafer test method of a memory chip with a redundancy unit as claimed in claim 1, wherein: and in the fourth step, replacing the failed row of the main area of the memory chip by the redundant unit in a hardware or software replacement mode.
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| CN114171103B (en) * | 2020-09-11 | 2023-09-12 | 长鑫存储技术有限公司 | Determination method of repair scheme of failure bit |
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