CN110663096A - Compound semiconductor substrate and method for manufacturing same - Google Patents
Compound semiconductor substrate and method for manufacturing same Download PDFInfo
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- CN110663096A CN110663096A CN201880033331.1A CN201880033331A CN110663096A CN 110663096 A CN110663096 A CN 110663096A CN 201880033331 A CN201880033331 A CN 201880033331A CN 110663096 A CN110663096 A CN 110663096A
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- 239000000758 substrate Substances 0.000 title claims abstract description 562
- 239000004065 semiconductor Substances 0.000 title claims abstract description 119
- 150000001875 compounds Chemical class 0.000 title claims abstract description 97
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000013078 crystal Substances 0.000 claims abstract description 53
- 230000002093 peripheral effect Effects 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims description 52
- 239000001257 hydrogen Substances 0.000 claims description 25
- 229910052739 hydrogen Inorganic materials 0.000 claims description 25
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 24
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 10
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 10
- 238000000926 separation method Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 84
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 17
- 229910010271 silicon carbide Inorganic materials 0.000 description 16
- 230000007547 defect Effects 0.000 description 15
- 238000005520 cutting process Methods 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 7
- 229910002601 GaN Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 238000005092 sublimation method Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
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- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/04—After-treatment of single crystals or homogeneous polycrystalline material with defined structure using electric or magnetic fields or particle radiation
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/16—Oxides
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- C30—CRYSTAL GROWTH
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- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
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- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
- C30B29/406—Gallium nitride
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- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/06—Joining of crystals
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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Abstract
The method for manufacturing a compound semiconductor substrate of the present invention includes the steps of: a partial substrate forming step of removing at least a part of the peripheral edge portion of a circular 1 st substrate made of a single crystal of a compound semiconductor from the 1 st substrate to form a 1 st partial substrate (12) including the center of the 1 st substrate; and a 1 st bonding step of forming a 1 st bonding substrate (71) in which two or more 1 st partial substrates (12) are aligned and bonded to a 1 st support substrate (2) having a larger diameter than the 1 st substrate.
Description
Technical Field
The present invention relates to a compound semiconductor substrate and a method for manufacturing the same. More specifically, the present invention relates to a compound semiconductor substrate formed by bonding a compound semiconductor substrate to a support substrate having a larger diameter, and a method for manufacturing the compound semiconductor substrate.
Background
As a substrate of a semiconductor device for high voltage use, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga) having a large band gap width2O3) Attention is being paid to compound semiconductor substrates. In such a wide band gap compound semiconductor, the increase in the diameter of the substrate and the reduction in crystal defects are major problems. In a small-diameter substrate, the defect density is decreasing, but in a large-diameter substrate, the reduction of crystal defects is not easy. For example. In the case of SiC substrates, it is known that a SiC layer is formed by vapor phase growth at a high temperature of 2000 ℃ or higher by a sublimation method, and when the crystal grows, the possibility of disorder of the arrangement of Si and C increases, and the crystal defect density increases. Therefore, the diameter of the SiC semiconductor substrate is usually 4 inches to 6 inches. In the case of a gallium oxide semiconductor substrate, the diameter of about 4 inches is practically the largest.
On the other hand, in the process of forming a semiconductor device, the larger the diameter of the wafer, the higher the productivity, and the larger the diameter of the semiconductor substrate is required. Further, cost reduction of a semiconductor substrate for a wide bandgap device is also an issue, and a proposal for reducing cost by substrate bonding has been made (see patent document 1). As a substrate of a semiconductor element made of, for example, SiC, a surface layer forming the semiconductor element may be a single crystal. The support substrate may be single-crystalline, polycrystalline, or amorphous regardless of its crystallinity. Patent document 1 discloses a method for manufacturing a semiconductor substrate, the method including: the single crystal SiC substrate and the polycrystalline SiC substrate as the support substrate are bonded together with the substrate surfaces modified.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 2015-15401
Disclosure of Invention
Problems to be solved by the invention
With the expansion of the use of high-voltage-driven compound semiconductor devices, cost reduction of these devices and practical use of higher-performance devices have become important issues. However, it has been difficult to achieve both high quality and large diameter of the compound semiconductor substrate.
The present invention has been made in view of the above-described situation, and an object thereof is to provide a compound semiconductor substrate having a relatively low crystal defect density and a relatively large diameter, which is formed by bonding a compound semiconductor substrate to a support substrate having a relatively large diameter, and a method for manufacturing the same.
Means for solving the problems
The present invention is as follows.
1. A method for manufacturing a compound semiconductor substrate, comprising: a partial substrate forming step of removing at least a part of a peripheral portion of a circular 1 st substrate made of a single crystal of a compound semiconductor from the 1 st substrate to form a 1 st partial substrate including a center of the 1 st substrate; and a 1 st bonding step of forming a 1 st bonded substrate in which two or more 1 st partial substrates are aligned and bonded to a 1 st support substrate having a larger diameter than the 1 st substrate.
2. The method for manufacturing a compound semiconductor substrate according to the above 1, wherein in the partial substrate forming step, the 1 st substrate is cut by two straight lines orthogonal to a reference point having a distance from the center of a radius or less and having an equal angle with respect to a diameter passing through the reference point, and a portion including the center of the 1 st substrate is formed as the 1 st partial substrate, and in the 1 st bonding step, 4 pieces of the 1 st partial substrates are aligned and bonded to the 1 st support substrate such that the reference point corresponds to an approximate center of the 1 st support substrate and the portions cut by the straight lines contact each other.
3. The method for manufacturing a compound semiconductor substrate according to claim 2, wherein in the partial substrate forming step, the 1 st partial substrate is further formed into a quadrangle by being cut by two straight lines orthogonal in diameter passing through the reference point.
4. The method for producing a compound semiconductor substrate according to the above 3, wherein in the first bonding step 1, n is2The 1 st partial substrates (n is a natural number of 2 or more) are arranged so as to be in contact with each other on the sides, and are bonded to the 1 st supporting substrate.
5. The method for manufacturing a compound semiconductor substrate according to the above 4, wherein in the 1 st bonding step, 4 1 st partial substrates are aligned and bonded to the 1 st support substrate so that the reference point corresponds to a substantial center of the 1 st support substrate.
6. The method for manufacturing a compound semiconductor substrate according to any one of claims 1 to 5, comprising: a 2 nd bonding step of bonding a 2 nd support substrate to the surface of the 1 st partial substrate aligned and bonded on the 1 st support substrate; and a 1 st removal step of removing the 1 st support substrate to form a 2 nd bonding substrate.
7. The method for manufacturing a compound semiconductor substrate according to the above 6, wherein the method for manufacturing a compound semiconductor substrate includes: a hydrogen layer forming step of forming a hydrogen layer at a position of the 1 st partial substrate of the 1 st or 2 nd bonding substrate, the position being a predetermined depth from a surface; a 3 rd bonding step of bonding a 3 rd support substrate to the surface of the 1 st partial substrate in the 3 rd bonding step; and a separation step of separating the 1 st partial substrate from the hydrogen layer to obtain a 3 rd bonded substrate in which a 1 st thin film layer made of a single crystal of the compound semiconductor is formed on the 3 rd support substrate.
8. The method of manufacturing a compound semiconductor substrate according to any one of claims 1.7, wherein the compound semiconductor is one of SiC, gallium oxide, and GaN.
9. A compound semiconductor substrate in which a 1 st thin film layer composed of a single crystal of a compound semiconductor is bonded to a support substrate, wherein the 1 st thin film layer is divided into two or more 1 st partial thin film layers, and the 1 st partial thin film layers are arranged on the support substrate so as to be in contact with each other.
10. The compound semiconductor substrate according to claim 9, wherein a surface of the 1 st thin film layer is divided into 4 1 st partial thin film layers in a sector shape having a center angle of 90 degrees, and the 1 st partial thin film layers are arranged around a center of the support substrate so as to be in contact with each other.
11. The compound semiconductor substrate according to the 9. or 10, wherein the compound semiconductor is one of SiC, gallium oxide, and GaN.
ADVANTAGEOUS EFFECTS OF INVENTION
The method for manufacturing a compound semiconductor substrate according to the present invention includes the steps of: a partial substrate forming step of removing at least a part of a peripheral portion of a circular 1 st substrate made of a single crystal of a compound semiconductor from the 1 st substrate to form a 1 st partial substrate including a center of the 1 st substrate; and a 1 st bonding step of forming a 1 st bonded substrate in which two or more 1 st partial substrates are aligned and bonded to a 1 st support substrate having a larger diameter than the 1 st substrate, so that the 1 st substrate having a small diameter made of a single crystal of a compound semiconductor can be combined with the 1 st support substrate to form a single crystal substrate having a large diameter. The 1 st bonded substrate can be formed into a circular or disk-shaped semiconductor substrate by further performing a step of bonding to or separating from another supporting substrate and the like and finally adjusting the shape of the peripheral edge portion of the substrate. However, if the produced 1 st bonding substrate is used not as an element substrate but as a seed substrate for constituting a bonding substrate, it can serve as a large number of bonding substrates, and a large-diameter bonding substrate can be realized at low cost. Further, since the crystal defect density of the small-diameter single crystal substrate is low, the crystal defect density of the substrate composed of the small-diameter single crystal substrates can be made low.
In the partial substrate forming step, the 1 st substrate is cut by two straight lines which are orthogonal to each other at a reference point having a distance from the center of a radius or less and which have an equal angle with respect to a diameter passing through the reference point, and a portion including the center of the 1 st substrate is formed as the 1 st partial substrate, and in the 1 st bonding step, 4 pieces of the 1 st partial substrates are aligned and bonded to the 1 st support substrate so that the reference point corresponds to an approximate center of the 1 st support substrate and the portions cut by the straight lines are in contact with each other, and in this case, the 1 st partial substrate having an arbitrary shape such as a sector shape or a quadrangle can be formed, and the 1 st partial substrate is formed by cutting the 1 st substrate so that at least two sides are orthogonal to each other. Further, two or more of the 1 st partial substrates may be combined on the surface of the 1 st support substrate to form the 1 st bonding substrate. In addition, although there is discontinuity of crystals at the boundary line portion where the adjacent 1 st partial substrates are in contact, it is possible to prevent a loss by using it as a position line when forming a semiconductor element.
In the partial substrate forming step, the 1 st partial substrate may be further formed into a quadrangle by cutting the 1 st partial substrate into two straight lines orthogonal in diameter passing through the reference point, and in this case, the 1 st partial substrate may be formed into a quadrangle such as a square according to the sizes of the 1 st substrate and the 1 st support substrate, and the handleability may be improved.
In the first bonding step, n is2In the case where the 1 st partial substrates (n is a natural number of 2 or more) are arranged and bonded to the 1 st support substrate so as to be in contact with each other, the 1 st partial substrates, such as 4, 9, and 16, can be arranged in order according to the size of the 1 st support substrate.
In the first bonding step, 4 pieces of the 1 st partial substrates are aligned and bonded to the 1 st support substrate so that the reference point corresponds to the approximate center of the 1 st support substrate, and in this case, the boundary line portion of each 1 st support substrate can be set as a position line at the time of forming the semiconductor element.
The method for manufacturing a compound semiconductor substrate comprises the following steps: a 2 nd bonding step of bonding a 2 nd support substrate to the surface of the 1 st partial substrate aligned and bonded on the 1 st support substrate; and a 1 st removing step of removing the 1 st support substrate to form a 2 nd bonding substrate, in which case the 2 nd support substrate is used as a support substrate, and the 2 nd bonding substrate in which the 1 st partial substrate is combined on the 2 nd support substrate can be formed. In the 2 nd bonding step, the surface of the 1 st partial substrate and the 2 nd support substrate can be firmly bonded to each other so as to withstand a high temperature, and thus the substrate is suitable as a seed substrate.
The method for manufacturing a compound semiconductor substrate comprises the following steps: a hydrogen layer forming step of forming a hydrogen layer at a position of the 1 st partial substrate of the 1 st or 2 nd bonding substrate, the position being a predetermined depth from a surface; a 3 rd bonding step of bonding a 3 rd support substrate to the surface of the 1 st partial substrate in the 3 rd bonding step; and a separation step of separating the 1 st partial substrate at the hydrogen layer to obtain a 3 rd bonded substrate in which a 1 st thin film layer made of a single crystal of the compound semiconductor is formed on the 3 rd support substrate, and in this case, the 3 rd support substrate is used as the support substrate, and the 3 rd bonded substrate in which the 1 st thin film layer made of a single crystal of the compound semiconductor separated from the 1 st partial substrate is bonded on the 3 rd support substrate can be formed. Since the thickness of the 1 st thin film layer can be made thin, a large number of 3 rd bonded substrates, in which the 1 st thin film layer is bonded to the 3 rd support substrate, can be manufactured using the 1 st bonded substrate or the 2 nd bonded substrate, in which the 1 st partial substrate is combined with the 1 st bonded substrate or the 2 nd support substrate, as a seed substrate. The 1 st or 2 nd bonded substrate has a larger diameter than the 1 st substrate having a smaller diameter.
In the case where the compound semiconductor is one of SiC, gallium oxide, and GaN, high-quality semiconductor elements can be formed on the bonding substrates, respectively.
The compound semiconductor substrate according to the present invention is a compound semiconductor substrate in which a 1 st thin film layer composed of a single crystal of a compound semiconductor is bonded to a support substrate, wherein the 1 st thin film layer is divided into two or more 1 st partial thin film layers, and the 1 st partial thin film layers are arranged on the support substrate so as to be in contact with each other, and therefore, a compound semiconductor substrate having a large diameter in which the 1 st thin film layer composed of a high-quality single crystal of a compound semiconductor having a small diameter is combined to a support substrate can be produced.
In addition, in the case where the surface of the 1 st thin film layer is divided into 4 1 st partial thin film layers having a sector shape with a center angle of 90 degrees, and the 1 st partial thin film layers are arranged so as to be in contact with each other around the center of the support substrate, a discontinuous boundary line portion where crystals exist due to contact between adjacent 1 st partial thin film layers can be used as a position line of the semiconductor element, and the compound semiconductor substrate can be used without causing loss.
When the compound semiconductor is one of SiC, gallium oxide, and GaN, the compound semiconductor substrate is suitable for forming high-quality semiconductor elements on the support substrate.
Drawings
The present invention will be further described in the following detailed description, which refers to the above-mentioned plurality of drawings, exemplifying non-limiting examples of typical embodiments of the invention, wherein like reference numerals refer to like parts throughout the several views of the drawings.
Fig. 1 is a plan view showing a 1 st partial substrate cut out from a 1 st substrate.
Fig. 2 is a plan view and a cross-sectional view showing an example of combining 4 sheets of the part 1 substrate.
Fig. 3 is a plan view showing a 1 st partial substrate cut out in a quadrangular shape from the 1 st substrate.
Fig. 4 is a plan view and a cross-sectional view showing an example of combining 4 quadrangular part 1 substrates.
Fig. 5 is a plan view and a cross-sectional view showing an example of combining 9 square partial substrates 1.
Fig. 6 is a plan view and a cross-sectional view showing an example of bonding 4 sheets of the partial No. 1 substrate to a support substrate.
Fig. 7 is a plan view and a cross-sectional view showing an example of bonding 4 sheets of the part 1 substrate to another support substrate.
Fig. 8 is a plan view and a cross-sectional view showing an example of bonding the 4-piece quadrangular No. 1 substrate to a support substrate.
Fig. 9 is a plan view and a cross-sectional view showing an example of bonding the 4-piece quadrangular 1 st partial substrate to another support substrate.
Fig. 10 is a schematic cross-sectional view showing an example of the 1 st bonding step, the 2 nd bonding step, and the 1 st removal step.
Fig. 11 is a schematic cross-sectional view showing another example of the 1 st bonding step, the 2 nd bonding step, and the 1 st removing step.
Fig. 12 is a schematic cross-sectional view showing the hydrogen layer forming step and the 3 rd bonding step.
Fig. 13 is a schematic plan view and a schematic cross-sectional view showing a compound semiconductor substrate.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
The matters shown herein are illustrative matters and matters for exemplarily describing the embodiments of the present invention and are described for the purpose of providing an explanation that is considered to be the most effective and easy understanding of the principle and conceptual features of the present invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice.
The method for manufacturing a compound semiconductor substrate of the present embodiment includes the steps of: a partial substrate forming step of removing at least a part of the peripheral edge portion of a circular 1 st substrate (1) made of a single crystal of a compound semiconductor from the substrate to form 1 st partial substrates (11, 12) including the center of the 1 st substrate (1); and a 1 st bonding step of forming a 1 st bonding substrate (71) in which two or more 1 st partial substrates (11, 12) are aligned and bonded to a 1 st support substrate (2) having a larger diameter than the 1 st substrate (1).
In the partial substrate forming step, the 1 st substrate (1) is cut by two straight lines (101, 102) so that a portion including the center (C1) of the circular shape is formed as the 1 st partial substrate (11, 12), the two straight lines (101, 102) are orthogonal to a reference point (P1) having a distance from the center (C1) of the circular shape of not more than a radius and have an equal angle with respect to a diameter (D) passing through the reference point (P1), and in the 1 st bonding step, the 1 st bonded substrate (71) in which 4 pieces of the 1 st partial substrates (11, 12) are bonded to the 1 st support substrate (2) so that the reference point (P1) corresponds to an approximate center (C2) of the 1 st support substrate (2) and the straight lines (101, 102) are aligned in contact with each other can be formed (see fig. 1 to 9).
In the partial substrate forming step, the other partial substrate 1 (12) may be further formed into a quadrangle cut by two straight lines 103 and 104 orthogonal to each other on a diameter D passing through the reference point P1 (see fig. 3 to 5).
The method for manufacturing a compound semiconductor substrate may further include: a 2 nd bonding step of bonding a 2 nd support substrate (3) to the surface of a 1 st partial substrate (11) aligned and bonded on the 1 st support substrate (2); and a 1 st removal step of removing the 1 st support substrate (2) to form a 2 nd bonding substrate (72) (see fig. 10 and 11).
The method for manufacturing a compound semiconductor substrate may further include: a hydrogen layer forming step of forming a hydrogen layer (15) at a position of a predetermined depth from the surface of a 1 st partial substrate (11) of a 2 nd bonding substrate (72); a 3 rd bonding step of bonding a 3 rd support substrate (4) to the surface of the 1 st partial substrate (11); and a separation step in which the 1 st partial substrate (11) is separated at the hydrogen layer (15) to obtain a 3 rd bonded substrate (73) in which a 1 st thin film layer (110) composed of a single crystal of the compound semiconductor is formed on a 3 rd support substrate (4) (see fig. 12).
Hereinafter, the method for manufacturing a compound semiconductor substrate according to the present embodiment will be described in detail with reference to the drawings.
(partial substrate Forming Process)
In the partial substrate forming step, the 1 st partial substrate 11 is cut out from the 1 st substrate 1 made of a single crystal of a compound semiconductor and having a circular surface. The shape and size of the 1 st partial substrate 11 are arbitrary, and may be cut out in a manner to reduce waste according to the size of the support substrate to be bonded later.
Fig. 1 (a) shows the following example: a circular 1 st substrate 1 made of a single crystal of a compound semiconductor is cut by two straight lines 101 and 102 so that a portion including a center C1 is formed as a 1 st partial substrate 11, the two straight lines 101 and 102 being orthogonal to a reference point P1 at a distance of a radius or less from the center C1 and having an equal angle with respect to a diameter D passing through the reference point P1. In this example, as shown in fig. 1 (b), the 1 st partial substrate 11 has a shape surrounded by two straight line portions (hereinafter, referred to as "sides") 101 and 102 and an arc 115. The 1 st substrate 1 of single crystal generally has a large number of crystal defects at the peripheral portion. Therefore, the reference point P1, which is the center of the combination of the 1 st partial substrates 11, is preferably located inward of the outer periphery of the 1 st substrate.
For example, the diameter of the 1 st substrate 1 is 6 inches. In fig. 1 (a), the center C1 of the 1 st substrate 1 is located at the origin (0, 0) of xy coordinates, and the diameter of the 1 st substrate 1 is 6 (unit: inch, the same applies hereinafter). The coordinates of reference point P1 are (2, -2), with edge 101 passing through reference point P1 and being parallel to the x-axis and edge 102 passing through reference point P1 and being parallel to the y-axis. The 1 st partial substrate 11 shown in fig. 1 (b) is cut by cutting the 1 st substrate 1 with straight lines corresponding to the sides 101 and 102, respectively.
Fig. 2 is a view in which 4 1 st partial substrates 11a to 11d cut out from the 4 1 st substrates 1 as described above are combined so that the sides 101a to 101d, 102a to 102d are in contact with each other with the reference points P1a to P1d as the center. For example, it can be configured that one side 101a of the part 1 substrate 11a is in contact with the side 102b of the part 1 substrate 11b and the other side 102a of the part 1 substrate 11a is in contact with the side 101d of the part 1 substrate 11 d. Fig. 2 (b) shows an AA' cross section of fig. 2 (a).
In the case where the diameter of the 1 st substrate 1 is 6 inches, the length of each side of the 1 st partial substrate 11 is 4.2 inches at maximum. This is because, in the right triangle having C1, M1, and M2 as vertexes shown in fig. 1, the length between C1 and M1 is 3 inches, and the length between C1 and M2 is 2 inches, so that the length between M1 and M2 is 2.2 inches, and the length of each side (101, 102) of the 1 st partial substrate 11 is 4.2 inches at maximum. The reference point P1 is located inward of the outer periphery of the 1 st substrate 1 so as to avoid the peripheral edge portion of the 1 st substrate 1 having many crystal defects. Therefore, as shown in fig. 2, when 4 number 1 of partial substrates 11a to 11d are arranged, the size (L1) of the single crystal portion is 8.4 inches at the maximum.
In the above, the example in which the 1 st partial substrate 11 is formed by cutting the 1 st substrate 1 with the two straight lines 101, 102 orthogonal to the reference point P1 has been shown, but the shape of the 1 st partial substrate is not limited to this. Further, the cutting is performed by two straight lines orthogonal on the diameter D passing through the reference point P1, whereby the part 1 substrate 12 can be formed into a quadrangle. The handling of the 1 st partial substrate 12 having a square shape is facilitated.
Fig. 3 shows the following example: the first partial substrate 12 is formed by cutting the first 1 circular substrate 1 made of a single crystal of a compound semiconductor by two straight lines 101 and 102, the two straight lines 101 and 102 being orthogonal to a reference point P1 having a distance from the center C1 of a radius or less and having an equal angle with respect to a diameter D passing through the reference point P1, and further cutting the first 1 circular substrate by two straight lines 103 and 104 being orthogonal to the diameter D passing through the reference point P1 and having an equal angle with respect to the diameter D. In this example, as shown in fig. 3 (b), the 1 st partial substrate 12 is a square surrounded by 4 straight line portions (sides) 101, 102, 103, and 104. Since the 1 st substrate 1 of a single crystal generally has a large number of crystal defects in the peripheral portion, the reference point P1 which is the center of the combination of the 1 st partial substrates 12 is preferably located inward of the outer periphery of the 1 st substrate.
For example, the diameter of the 1 st substrate 1 is 6 inches. In fig. 3 (a), the center C1 of the 1 st substrate 1 is located at the origin (0, 0) of xy coordinates, and the diameter of the 1 st substrate 1 is 6. Reference point P1 has coordinates of (2, -2), with side 101 passing through reference point P1 and parallel to the x-axis, and side 102 passing through reference point P1 and parallel to the y-axis. A straight line 103 perpendicular to the diameter D passing through the reference point P1 is parallel to the x-axis, and a straight line 104 is parallel to the y-axis. The 1 st substrate 12 shown in fig. 3 (b) is cut by cutting the 1 st substrate 1 with straight lines corresponding to the sides 101, 102, 103, and 104, respectively.
Fig. 4 is a view in which 4 1 st partial substrates 12a to 12d cut out from the 4 1 st substrates 1 as described above are combined so that the reference points P1a to P1d are centered and the two sides 101a to 101d, 102a to 102d are in contact with each other. For example, it can be configured such that one side 101a of the part 1 substrate 12a is in contact with the side 102b of the part 1 substrate 12b and the other side 102a of the part 1 substrate 12a is in contact with the side 101d of the part 1 substrate 12 d. Fig. 4 (b) shows the AA' cross section of fig. 4 (a).
In the case of the 1 st substrate 1 having a diameter of 6 inches, the length of each side of the 1 st partial substrate 12 is 4.2 inches at the maximum. This is because, in a right triangle having C1, M1, and M2 as vertexes shown in fig. 3, the length between C1 and M1 is 3 inches, and the length between C1 and M2 is 2 inches, so the length between M1 and M2 is 2.2 inches, and the length of each side (101 to 104) of the part 1 substrate 12 is 4.2 inches at the maximum. The reference point P1 is located inward of the outer periphery of the 1 st substrate 1 so as to avoid the peripheral edge portion of the 1 st substrate 1 having many crystal defects. Therefore, as shown in fig. 4, when 4 partial substrates 12a to 12d are arranged, the single crystal portion is a quadrangle having 1 side and 8.4 inches at the maximum.
In fig. 4, an example in which 4 part 1 substrates 12 are arranged is shown, but the number of part 1 substrates 12 is not particularly limited, and n may be set, for example2The 1 st partial substrates 12 (n is a natural number of 2 or more) are arranged so that the sides thereof contact each other.
Fig. 5 shows an example in which 9 of the 1 st partial substrates 12(12a to 12i) are arranged in 3 × 3. Further, 16 partial substrates 12 may be arranged in 4 × 4. In fig. 5, the 9 1 st partial substrates 12a to 12i are square, the four sides of the 9 1 st partial substrates 12a to 12i are denoted by 101a to 101i, 102a to 102i, 103a to 103i, and 104a to 104i, and the reference points are denoted by P1a to P1 i. This makes it possible to form a compound semiconductor substrate having a size of at most 3 times the size of 1 side of the 1 st partial substrate 12.
(the 1 st joining step)
In the first bonding step, a 1 st bonding substrate 71 is formed on the 1 st support substrate 2 having a diameter larger than that of the 1 st substrate 1, wherein 4 1 st partial substrates (11a to 11d or 12a to 12d) are bonded to each other in an arrangement such that the reference point P1 of each 1 st partial substrate corresponds to an approximate center of the 1 st support substrate 2 and the straight portions 101 and 102 contact each other.
Fig. 6 shows a 1 st bonding substrate 71 formed by combining 4 1 st partial substrates 11a to 11d cut out from 4 1 st substrates 1 having a diameter of 6 inches as shown in fig. 2 and mounting them on a 1 st support substrate 21 having a diameter of 8 inches. Fig. 6 (b) shows an AA' cross section of the 1 st bonding substrate 71. As described above, since the size of the single crystal portion constituted by the 4 1 st partial substrates 11a to 11d is about 8.4 inches, it is larger than the 1 st support substrate 21 having a diameter of 8 inches.
The 1 st bonding substrate 71 corresponding to such an 8-inch size is formed by sequentially bonding the 1 st partial substrates 11a to 11d to the 1 st support substrate 21 via an adhesive. By using the adhesive material, the 1 st partial substrate can be bonded to the 1 st support substrate with high accuracy.
Fig. 7 shows a 1 st bonded substrate 71 formed by mounting 4 1 st partial substrates 11a to 11d cut out from 4 1 st substrates 1 having a diameter of 6 inches on a 1 st support substrate 22 having a diameter of 10 inches in the same manner as described above. The size of the single crystal portion constituted by the 4 1 st partial substrates 11a to 11d is about 8.4 inches, and therefore, is smaller than the 1 st support substrate 22 having a diameter of 10 inches. Therefore, a defect 221 where no single crystal portion exists is generated at the peripheral edge portion 4 on the 1 st support substrate 22. However, since the area of the defect portion 221 is small relative to the entire 1 st support substrate 22, the influence on the substrate for forming the semiconductor element can be said to be small. In this manner, the 1 st bonding substrate 71 corresponding to the 10-inch size can be formed.
Fig. 8 shows a 1 st bonding substrate 71 formed by combining 4 1 st partial substrates 12a to 12d cut out from 4 1 st substrates 1 having a diameter of 6 inches as shown in fig. 4 and mounting them on a 1 st support substrate 21 having a diameter of 8 inches. Fig. 8 (b) shows an AA' cross section of the 1 st bonding substrate 71. As described above, 1 side of the single crystal portion constituted by the 4 1 st partial substrates 12a to 12d is about 8.4 inches, and therefore, is larger than the 1 st support substrate 21 having a diameter of 8 inches.
The 1 st bonding substrate 71 corresponding to such an 8-inch size is formed by sequentially bonding the 1 st partial substrates 12a to 12d to the 1 st support substrate 21 via an adhesive. By using the adhesive material, the 1 st partial substrate can be bonded to the 1 st support substrate with high accuracy.
Fig. 9 shows a 1 st bonded substrate 71 formed by mounting 4 1 st partial substrates 12a to 12d cut out from 4 1 st substrates 1 having a diameter of 6 inches on a 1 st support substrate 22 having a diameter of 10 inches in the same manner as described above. Since 1 side of the single crystal portion composed of the 4 1 st partial substrates 12a to 12d is about 8.4 inches, a defect 223 in which no single crystal portion exists is generated in the peripheral portion 4 of the 1 st support substrate 22 having a diameter of 10 inches. However, since the area of the defective portion 223 is small relative to the entire 1 st support substrate 22, the influence on the substrate for forming the semiconductor element can be said to be small. In this manner, the 1 st bonding substrate 71 corresponding to the 10-inch size can be formed.
As described above, the number of the part 1 substrates 12 is not limited to 4, and can be increased to 9 (see fig. 5), 16, and the like. Therefore, by using the 1 st support substrate 2 having a diameter corresponding to the size of the 1 st partial substrate 12, the 1 st bonding substrate 71 having a larger diameter can be formed. By forming the 1 st bonding substrate 71 or the 2 nd bonding substrate 72 (described later) having a large diameter, the 3 rd bonding substrate 73 (described later) which is a compound semiconductor substrate having a large diameter can be manufactured as a seed substrate (hereinafter, a seed substrate). This enables the wide bandgap semiconductor substrate, which is difficult to increase in diameter, to be increased in diameter. Further, it is possible to obtain a compound semiconductor substrate having a small diameter and good quality by combining a high-quality compound semiconductor substrate having a small diameter (the 1 st substrate 1) without limiting the object of increasing the diameter.
(circular cutting)
The 1 st bonding substrate 71 formed as described above can be cut (circular cut) in accordance with the size of the 1 st support substrate 2(21, 22). Thereby, the outer periphery of the 1 st bonding substrate 71 is adjusted to the size of the 1 st support substrate 2(21, 22). The position of the circular cut does not necessarily have to be the same as the size of the 1 st support substrate 2(21, 22), and the circular cut may be slightly smaller than the 1 st support substrate 2(21, 22). Thereby, the 1 st bonding substrate 71 having a diameter of 8 inches or 10 inches is formed (see fig. 10 (a)).
(the 2 nd joining step and the 1 st removing step)
Fig. 10 shows the following procedure: a 2 nd bonding step of bonding the 2 nd support substrate 3 to the surface of the 1 st bonding substrate 71, that is, to the surfaces of the 1 st partial substrates (11, 12) aligned and bonded on the 1 st support substrates 2(21, 22); and a 1 st removal step, which is performed after that, the 1 st support substrate 2 is removed to form a 2 nd bonding substrate 72. In the present figure, the 1 st bonding substrate 71 is drawn with the outer periphery thereof adjusted by circular dicing, but the 1 st bonding substrate 71 may be in a state in which the outer periphery thereof is not adjusted (see fig. 6 to 9). The 2 nd bonding substrate 72 can be a seed substrate of a bonding substrate to be formed later. In forming the 1 st bonding substrate 71, the 1 st support substrate 2(21, 22) is bonded to the 1 st support substrate 2 with high accuracy using an adhesive or the like, but needs to withstand a high temperature of approximately 1000 ℃ in order to be a seed substrate of the bonding substrate. In the case where the bonding portion of the 1 st bonding substrate 71 cannot withstand high temperature, the 1 st partial substrate (11, 12) can be attached to the 2 nd support substrate 3 in turn.
Fig. 10 (a) shows a state where the peripheral edge portion of a 1 st bonding substrate 71 obtained by mounting a plurality of 1 st partial substrates (11, 12) on the 1 st support substrate 2(21, 22) is removed by circular dicing (AA' cross section).
Fig. 10 (b) shows a state where the 2 nd support substrate 3 is bonded to the 1 st partial substrate (11, 12) side surface of the 1 st bonding substrate 71 in the 2 nd bonding step. The size of the 2 nd support substrate 3 can be set to 8 inches, 10 inches, or the like according to the size of the 1 st bonding substrate 71. When the material of the 1 st substrate 1, which is the 1 st partial substrates (11, 12) made of single crystal, is SiC, the 2 nd support substrate 3 is preferably a polycrystalline SiC substrate having the same linear expansion coefficient. The bonding method is not particularly limited, and for example, the surfaces of the 1 st partial substrates (11, 12) and the surface of the 2 nd support substrate 3 may be planarized, and then both surfaces may be activated by an argon beam (japanese patent: ア ル ゴ ン ビ ー ム) or the like to bond them at normal temperature. By thus bonding, a seed substrate that can withstand high temperature can be obtained.
Fig. 10 (c) shows a state where the 1 st supporting substrate 2(21, 22) is peeled and removed by the 1 st removing step to form the 2 nd bonding substrate 72. The method of peeling is not particularly limited, and for example, when the 1 st supporting substrate 2 is made of transparent alkali-free glass or the like and the 1 st partial substrates (11, 12) are bonded to each other with a photo-curable adhesive material, peeling can be easily performed by heating to a high temperature.
Fig. 11 (a) to 11 (c) show the case where there are defects (221, 223, etc.) in the single crystal portion in the 1 st bonding substrate 71. In this case, too, there is no structural problem, and the 2 nd bonding substrate 72 can be formed in the same manner as in (a) to (c) of the preceding drawings.
This makes it possible to obtain the 2 nd bonding substrate 72 having a size of 8 inches or 10 inches, and the 2 nd bonding substrate 72 is suitable as a seed substrate of the bonding substrate.
(Hydrogen layer formation step, No. 3 bonding step, separation step)
In the present embodiment, the method may include the steps of: a hydrogen layer forming step of forming a hydrogen layer 15 on the 1 st partial substrate (11, 12) of the 1 st bonding substrate 71 or the 2 nd partial substrate 72 at a predetermined depth from the surface; a 3 rd bonding step of bonding a 3 rd support substrate 4 to the surface of the 1 st partial substrate (11, 12); and a separation step of separating the 1 st partial substrates (11, 12) at the hydrogen layer 15 to obtain a 3 rd bonded substrate 73 in which a 1 st thin film layer 110 made of a single crystal of the compound semiconductor is formed on the 3 rd support substrate 4. This makes it possible to obtain a large number of bonded substrates (3 rd bonded substrate 73) using the 2 nd bonded substrate 72 as a seed substrate.
Fig. 12 shows the hydrogen layer forming step, the 3 rd bonding step, and the separation step.
As shown in fig. 12 (a), the 2 nd bonding substrate 72 is configured by bonding a plurality of 1 st partial substrates (11, 12) to the entire surface of the 2 nd support substrate 3. In the hydrogen layer formation step, hydrogen ions are implanted into the position of the 1 st partial substrate (11, 12) at a constant depth (e.g., a depth of about 0.5 μm) from the surface (lower surface in the drawing) to form the hydrogen layer 15. The single crystal surface layer portion from the hydrogen layer 15 to the surface of the 1 st partial substrate (11, 12) is defined as the 1 st thin film layer 110.
Fig. 12 (b) shows a state where the 3 rd support substrate 4 is bonded to the surface of the 1 st partial substrate (11, 12). The bonding method is not particularly limited, and for example, the surface of the 1 st partial substrate (11, 12), that is, the surface of the 1 st thin film layer 110 and the surface of the 3 rd support substrate 4 may be processed to be flat, and bonding may be performed at room temperature in a state where both surfaces are activated by an argon beam or the like.
Thereafter, the 1 st partial substrate (11, 12) is separated at the hydrogen layer 15 by setting to a high temperature of about 1000 ℃. As a result, as shown in fig. 12 (c), the 3 rd bonded substrate 73 in which the 1 st thin film layer 110 separated from the hydrogen layer 15 is bonded to the 3 rd support substrate 4 can be obtained. When the thickness of the 1 st partial substrate (11, 12), that is, the thickness of the 1 st substrate 1 is set to 100 μm, the 1 st thin film layer 110 is separated 1 time and the thickness is reduced by about 1 μm, and therefore, the 1 nd 2 nd bonded substrate 72 can be reused several hundred times as a seed substrate by performing polishing or the like after peeling.
The seed substrate is not limited to the 2 nd bonding substrate 72 formed by forming a single crystal layer on the 2 nd support substrate 3, and the 1 st bonding substrate 71 formed by forming a single crystal layer on the 1 st support substrate 2 may be used. In this case, the bonding layer for bonding the 1 st support substrate 2 and the 1 st partial substrates (11, 12) may be a bonding layer having high heat resistance.
(epitaxial layer Forming step)
Then, as shown in fig. 12 (d), the surface of the 1 st thin film layer 110 of the 3 rd bonding substrate 73 is polished or the like, and a bonding substrate 74 in which the epitaxial layer 5 is formed on the surface of the 1 st thin film layer 110 can be obtained. The thickness of the epitaxial layer 5 can be about 10 μm, and the epitaxial layer 5 becomes an active layer in the semiconductor element.
Since the epitaxial layer 5 is formed on the 1 st thin film layer 110 formed of the 4 1 st partial substrates (11, 12), the epitaxial layer 5 also has a junction line portion 51 (see fig. 13) in which crystallinity is discontinuous in a portion contacting the boundary line portion of each of the 1 st partial substrates (11, 12). The bonding wire portion 51 serves as a position line (japanese: ス ク ラ イ ブ ラ イ ン) at the time of formation of the semiconductor element. Therefore, if the visibility of the bonding wire portion 51 is insufficient, the mark for mask alignment can be applied by printing or the like at the stage shown in fig. 12 (d).
The bonding substrate formed on the basis of the bonding substrate 74 as described above can be used as the final compound semiconductor substrate 75. The compound semiconductor substrate 75 is a compound semiconductor substrate in which a 1 st thin film layer 110 made of a single crystal of a compound semiconductor is bonded to a support substrate 4, and the 1 st thin film layer 110 is divided into two or more 1 st partial thin film layers, and the 1 st partial thin film layers are arranged on the support substrate 4 so as to be in contact with each other.
Fig. 13 is a schematic plan view and cross-sectional view of a compound semiconductor substrate 75. In this example, the surface of the 1 st thin film layer 110 is divided into 4 1 st partial thin film layers 110a to 110d in a sector shape having a center angle of 90 degrees, and the 1 st thin film layer 110 is configured such that the 1 st partial thin film layers 110a to 110d are arranged around the center of the support substrate 4 so as to be in contact with each other. The compound semiconductor can be selected from SiC, gallium oxide, and GaN. The compound semiconductor substrate 75 may be a substrate in which the epitaxial layer 5 is formed on the surface of the 1 st partial thin film layers 110a to 110 d.
The size of the compound semiconductor substrate 75 is not particularly limited, and may be, for example, 10 inches or 12 inches in diameter.
The compound semiconductor substrate 75 may be provided with a mark for visually recognizing the boundary line portion of the 1 st partial thin film layers 110a to 110 d. By using this mark, the boundary line portion (bonding line portion 51 of epitaxial layer 5) of the 1 st partial thin film layers 110a to 110d can be used as a position line at the time of forming the semiconductor element, and can be used as a semiconductor substrate without waste.
The compound semiconductor substrate and the method for manufacturing the same according to the present embodiment can increase the diameter of a wide bandgap substrate, which is difficult to increase the diameter. By setting the boundary line portion 51 of the 1 st partial thin film layer 110 made of 4 sheets as a position line, the compound semiconductor substrate can be used without waste. When the 1 st thin film layer 110 is formed by arranging 9, 16, or other 1 st partial thin film layers, it is difficult to make the boundary line portion thereof a position line of an arbitrary element size. That is, although 1 boundary line portion can be made to function as a position line, the pitches of the other boundary line portions do not match and cannot function as a position line. For example, when 9 partial film layers 1 are combined (see fig. 5) to form the 1 st film layer 110, only 1 column in the vertical direction and 1 row in the horizontal direction do not coincide with the position line, and thus only a very small portion is wasted. To further reduce waste, the part 1 substrate 12 can be sized accordingly to the component size.
Although the example of forming the 8-inch or 10-inch seed substrate using the 6-inch compound semiconductor substrate has been described above, the 6-inch seed substrate can be formed using the 4-inch compound semiconductor substrate in the same manner. Although the SiC substrate is mainly described as the compound semiconductor substrate, the present invention can be similarly applied to wide band gap materials such as GaN and gallium oxide.
The final support substrate (the 3 rd support substrate 4) is not limited to the polycrystalline SiC substrate, and may be a sapphire substrate or an Si substrate, for example, as long as it has high heat resistance at a temperature equal to or higher than the temperature required for the separation of the hydrogen layer.
The support substrate (1 st support substrate 2) to be temporarily provided is not limited to alkali-free glass, and a photocurable adhesive can be used for bonding to the 1 st partial substrate if the substrate is a transparent substrate. In addition, in the case of using an adhesive, the material is not limited. The Si substrate can also be used as a support substrate temporarily provided at a time.
Industrial applicability
In the field of vehicles, along with the spread of hybrid vehicles and electric vehicles, the importance of using high-voltage driving elements such as SiC has increased. In the home, along with the spread of smart grids, the role of high-voltage devices is becoming more important for the electric operation and energy management of household electrical appliances. According to the present invention, a compound semiconductor substrate having a large diameter and high quality can be manufactured, which contributes to cost reduction of a wide band gap device.
Description of the reference numerals
1. A 1 st substrate; 11. 12, part 1 substrate; 110. 1 st film layer (part 1 film layer); 2. 21, 22, the 1 st support substrate; 3. a 2 nd support substrate; 4. a support substrate (3 rd support substrate); 5. an epitaxial layer; 71. 1 st bonding substrate; 72. a 2 nd bonding substrate; 73. a 3 rd bonding substrate; 74. a bonding substrate; 75. a compound semiconductor substrate.
Claims (11)
1. A method for manufacturing a compound semiconductor substrate is characterized in that,
the method for manufacturing a compound semiconductor substrate comprises the following steps:
a partial substrate forming step of removing at least a part of a peripheral portion of a circular 1 st substrate made of a single crystal of a compound semiconductor from the 1 st substrate to form a 1 st partial substrate including a center of the 1 st substrate; and
and a 1 st bonding step of forming a 1 st bonded substrate in which two or more 1 st partial substrates are aligned and bonded to a 1 st support substrate having a larger diameter than the 1 st substrate.
2. The method for manufacturing a compound semiconductor substrate according to claim 1,
in the partial substrate forming step, the 1 st substrate is cut by two straight lines that are orthogonal to each other at a reference point having a distance from the center of not more than a radius and that have an equal angle with respect to a diameter passing through the reference point, and a portion including the center of the 1 st substrate is formed as the 1 st partial substrate,
in the first bonding step, 4 of the 1 st partial substrates are aligned and bonded to the 1 st support substrate such that the reference point corresponds to a substantial center of the 1 st support substrate and the portions cut by the straight line contact each other.
3. The method for manufacturing a compound semiconductor substrate according to claim 2, wherein,
in the partial substrate forming step, the 1 st partial substrate is further formed into a quadrangle by being cut by two straight lines orthogonal in diameter passing through the reference point.
4. The method for manufacturing a compound semiconductor substrate according to claim 3, wherein,
at the 1 st jointerIn the sequence, n is2The 1 st partial substrates are arranged and bonded to the 1 st support substrate so that the sides thereof are in contact with each other, and n is a natural number of 2 or more.
5. The method for manufacturing a compound semiconductor substrate according to claim 4, wherein,
in the 1 st bonding step, 4 1 st partial substrates are aligned and bonded to the 1 st support substrate such that the reference point corresponds to a substantial center of the 1 st support substrate.
6. The method for manufacturing a compound semiconductor substrate according to any one of claims 1 to 5,
the method for manufacturing a compound semiconductor substrate comprises the following steps:
a 2 nd bonding step of bonding a 2 nd support substrate to the surface of the 1 st partial substrate aligned and bonded on the 1 st support substrate; and
and a 1 st removing step of removing the 1 st support substrate to form a 2 nd bonding substrate.
7. The method for manufacturing a compound semiconductor substrate according to claim 6, wherein,
the method for manufacturing a compound semiconductor substrate comprises the following steps:
a hydrogen layer forming step of forming a hydrogen layer at a position of the 1 st partial substrate of the 1 st or 2 nd bonding substrate, the position being a predetermined depth from a surface;
a 3 rd bonding step of bonding a 3 rd support substrate to the surface of the 1 st partial substrate in the 3 rd bonding step; and
and a separation step of separating the 1 st partial substrate from the hydrogen layer to obtain a 3 rd bonded substrate in which a 1 st thin film layer made of a single crystal of the compound semiconductor is formed on the 3 rd support substrate.
8. The method for manufacturing a compound semiconductor substrate according to any one of claims 1 to 7,
the compound semiconductor is one of SiC, gallium oxide, and GaN.
9. A compound semiconductor substrate in which a 1 st thin film layer composed of a single crystal of a compound semiconductor is bonded to a support substrate,
the 1 st thin film layer is divided into two or more 1 st partial thin film layers, and the 1 st partial thin film layers are arranged on the support substrate so as to be in contact with each other.
10. The compound semiconductor substrate according to claim 9, wherein,
the surface of the 1 st thin film layer is divided into 4 1 st partial thin film layers having a sector shape with a center angle of 90 degrees, and the 1 st partial thin film layers are arranged around the center of the support substrate in a mutually contacting manner.
11. The compound semiconductor substrate according to claim 9 or 10, wherein,
the compound semiconductor is one of SiC, gallium oxide, and GaN.
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| JPH04293241A (en) * | 1991-03-22 | 1992-10-16 | Nissan Motor Co Ltd | Manufacture of semiconductor substrate |
| JP2003324136A (en) * | 2002-04-30 | 2003-11-14 | Shin Etsu Handotai Co Ltd | Automatic inspecting apparatus and automatic inspecting method of crystal defect |
| JP2004117147A (en) * | 2002-09-26 | 2004-04-15 | Shin Etsu Handotai Co Ltd | Automatic inspection method and automatic inspection device of crystal defect |
| JP2008235723A (en) * | 2007-03-22 | 2008-10-02 | Zycube:Kk | Wafer body structure and manufacturing method thereof |
| WO2009028399A1 (en) * | 2007-08-24 | 2009-03-05 | Sumco Corporation | Semiconductor wafer and method for manufacturing the same |
| JP2011114327A (en) * | 2009-11-30 | 2011-06-09 | Shibaura Mechatronics Corp | Device and method of supplying semiconductor chip |
| JP2013098572A (en) * | 2011-11-04 | 2013-05-20 | Samsung Corning Precision Materials Co Ltd | Method for manufacturing thin film-bonded substrate |
| CN105474354A (en) * | 2013-07-05 | 2016-04-06 | 株式会社丰田自动织机 | Manufacturing method for semiconductor substrate |
| JP2016192544A (en) * | 2015-02-25 | 2016-11-10 | インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ | Semiconductor substrate arrangement and method for forming semiconductor substrate arrangement |
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| Publication number | Publication date |
|---|---|
| DE112018003706T5 (en) | 2020-04-09 |
| WO2019017398A1 (en) | 2019-01-24 |
| CN110663096B (en) | 2023-06-06 |
| JP2019021818A (en) | 2019-02-07 |
| JP6854516B2 (en) | 2021-04-07 |
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