JP2019021818A - Compound semiconductor substrate and method for manufacturing the same - Google Patents

Compound semiconductor substrate and method for manufacturing the same Download PDF

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JP2019021818A
JP2019021818A JP2017140348A JP2017140348A JP2019021818A JP 2019021818 A JP2019021818 A JP 2019021818A JP 2017140348 A JP2017140348 A JP 2017140348A JP 2017140348 A JP2017140348 A JP 2017140348A JP 2019021818 A JP2019021818 A JP 2019021818A
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JP6854516B2 (en
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光治 加藤
Mitsuharu Kato
光治 加藤
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Abstract

To provide a compound semiconductor substrate formed by sticking a compound semiconductor substrate to a support substrate larger in diameter, and having a low crystal defect density and a large diameter, and a method for manufacturing the compound semiconductor substrate.SOLUTION: A method for manufacturing a compound semiconductor substrate comprises: a partial substrate forming step of removing, from a first substrate of a circular form made of a compound semiconductor monocrystal, at least a part of its peripheral edge to form a portion including the center of the first substrate as a first partial substrate 12; and a first bonding step of arranging two or more first partial substrates 12 formed by the partial substrate forming step on a first support substrate 2 larger than the first substrate in diameter, bonding them together to form a first bonded substrate 71.SELECTED DRAWING: Figure 9

Description

本発明は、化合物半導体基板及びその製造方法に関する。詳しくは、化合物半導体基板をより口径の大きい支持基板に貼り合わせて形成される化合物半導体基板及びその製造方法に関する。   The present invention relates to a compound semiconductor substrate and a manufacturing method thereof. Specifically, the present invention relates to a compound semiconductor substrate formed by bonding a compound semiconductor substrate to a support substrate having a larger aperture and a method for manufacturing the same.

高電圧用途の半導体素子の基板として、バンドギャップ幅が大きい炭化ケイ素（ＳｉＣ）、窒化ガリウム（ＧａＮ）、酸化ガリウム（Ｇａ２Ｏ３）などの化合物半導体基板が着目されている。このようなワイドバンドギャップの化合物半導体においては、基板の大口径化と結晶欠陥の低減が大きな課題となっている。小口径の基板においては欠陥密度が低くなりつつあるが、大口径の基板では結晶欠陥の低減が容易ではない。例えばＳｉＣ基板の場合、昇華法により気層成長で２０００℃以上の高温下でＳｉＣ層が形成され、その結晶成長時にＳｉとＣの配列が乱れる可能性が高く、結晶欠陥密度が高くなることが知られている。そのため、ＳｉＣ半導体基板は口径４インチから６インチが一般的である。また、酸化ガリウム半導体基板の場合には、口径４インチ程度が実用上最大のサイズとなっている。 Compound semiconductor substrates such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga 2 O 3 ) having a large band gap are attracting attention as substrates for semiconductor devices for high voltage applications. In such a compound semiconductor having a wide band gap, increasing the diameter of the substrate and reducing crystal defects are major issues. Although the defect density is decreasing in a small-diameter substrate, it is not easy to reduce crystal defects in a large-diameter substrate. For example, in the case of a SiC substrate, a SiC layer is formed at a high temperature of 2000 ° C. or higher by gas phase growth by sublimation, and there is a high possibility that the arrangement of Si and C is disturbed during the crystal growth, resulting in a high crystal defect density. Are known. Therefore, the diameter of the SiC semiconductor substrate is generally 4 inches to 6 inches. In the case of a gallium oxide semiconductor substrate, a diameter of about 4 inches is the maximum practical size.

一方、半導体素子の形成に当たっては、ウエーハの口径が大きい方が生産性は高く、半導体基板の大口径化が求められている。また、ワイドバンドギャップ素子用の半導体基板のコスト低減も課題であり、基板接合によりコスト低減を図ることも提案されている（特許文献１を参照。）。例えばＳｉＣからなる半導体素子の基板としては、半導体素子が形成される表層だけが単結晶であればよい。その支持基板は結晶性を問わず、単結晶でも多結晶でも非晶質でもよい。特許文献１には、単結晶ＳｉＣ基板と支持基板である多結晶ＳｉＣ基板とを、基板表面を改質して接合する半導体基板の製造方法が開示されている。   On the other hand, in forming a semiconductor element, the larger the wafer diameter is, the higher the productivity is, and there is a demand for a larger semiconductor substrate. In addition, cost reduction of a semiconductor substrate for a wide band gap element is an issue, and it has been proposed to reduce the cost by substrate bonding (see Patent Document 1). For example, as a substrate of a semiconductor element made of SiC, only the surface layer on which the semiconductor element is formed needs to be a single crystal. The supporting substrate may be single crystal, polycrystalline or amorphous regardless of crystallinity. Patent Document 1 discloses a method for manufacturing a semiconductor substrate in which a single crystal SiC substrate and a polycrystalline SiC substrate as a support substrate are bonded by modifying the substrate surface.

特開２０１５−１５４０１号公報Japanese Patent Laying-Open No. 2015-15401

高電圧駆動の化合物半導体素子の用途が拡大するにつれて、それらの素子の低コスト化と、より性能の高い素子の実用化が重要な課題となってきている。しかし、従来、化合物半導体基板の高品質化と大口径化を両立させることは困難であった。
本発明は、上記現状に鑑みてなされたものであり、化合物半導体基板をより口径の大きい支持基板に貼り合わせて形成される、結晶欠陥密度が低く且つ大口径の化合物半導体基板及びその製造方法を提供することを目的とする。 As the use of high-voltage-driven compound semiconductor devices expands, the cost reduction of these devices and the practical use of devices with higher performance have become important issues. However, conventionally, it has been difficult to achieve both high quality and large diameter compound semiconductor substrates.
The present invention has been made in view of the above situation, and a compound semiconductor substrate having a low crystal defect density and a large diameter, which is formed by bonding a compound semiconductor substrate to a support substrate having a larger diameter, and a method for manufacturing the compound semiconductor substrate. The purpose is to provide.

本発明は、以下の通りである。
１．化合物半導体の単結晶からなる円形の第１基板から少なくともその周縁部の一部を除去し、前記第１基板の中心を含む部分を第１部分基板として形成する部分基板形成工程と、前記第１基板よりも直径の大きい第１支持基板上に、２以上の前記第１部分基板を配列して接合した第１接合基板を形成する第１接合工程と、を含むことを特徴とする化合物半導体基板の製造方法。
２．前記部分基板形成工程において、前記第１基板を、その中心からの距離が半径以下である基準点において直交し且つ前記基準点を通る直径に対して等角となる２つの直線により切断し、前記中心を含む部分を第１部分基板として形成し、前記第１接合工程において、前記第１支持基板上に、前記第１支持基板の略中心に前記基準点を対応させ且つ前記直線で切断された部分が相互に接するように４つの前記第１部分基板を配列して接合する、前記１．記載の化合物半導体基板の製造方法。
３．前記部分基板形成工程において、前記第１部分基板は、更に前記基準点を通る直径上で直交する２つの直線によって切断され、四辺形に形成される前記２．記載の化合物半導体基板の製造方法。
４．前記第１接合工程において、前記第１支持基板上に、ｎ２個（ｎは２以上の自然数）の前記第１部分基板を相互に辺が接するように配列して接合する前記３．記載の化合物半導体基板の製造方法。
５．前記第１接合工程において、前記第１支持基板上に、前記第１支持基板の略中心に前記基準点を対応させて４つの前記第１部分基板を配列して接合する前記４．記載の化合物半導体基板の製造方法。
６．前記第１支持基板上に配列して接合された前記第１部分基板の表面に、第２支持基板を接合する第２接合工程と、前記第１支持基板を除去することにより第２接合基板を形成する第１除去工程と、を含む前記１．乃至５．のいずれかに記載の化合物半導体基板の製造方法。
７．前記第１接合基板又は前記第２接合基板の前記第１部分基板の表面から所定の深さに水素層を形成する水素層形成工程と、前記第１部分基板の前記表面に第３支持基板を接合する第３接合工程と、前記第１部分基板を前記水素層において分離することにより、前記第３支持基板上に前記化合物半導体の単結晶からなる第１薄膜層が形成された第３接合基板を得る分離工程と、を含む前記６．に記載の化合物半導体基板の製造方法。
８．前記化合物半導体はＳｉＣ、酸化ガリウム及びＧａＮのうちの１つである前記１．乃至７．のいずれかに記載の化合物半導体基板の製造方法。
９．化合物半導体の単結晶からなる第１薄膜層が支持基板上に接合された化合物半導体基板であって、前記第１薄膜層は２以上の第１部分薄膜層に分割されており、各前記第１部分薄膜層が相互に接するように配列されていることを特徴とする化合物半導体基板。
１０．前記第１薄膜層は表面が中心角９０度の扇形である４つの第１部分薄膜層に分割されており、前記支持基板の中心の回りに前記第１部分薄膜層が相互に接するように配列されている前記９．記載の化合物半導体基板。
１１．前記化合物半導体はＳｉＣ、酸化ガリウム及びＧａＮのうちの１つである前記９．又は１０．に記載の化合物半導体基板。 The present invention is as follows.
1. A partial substrate forming step of removing at least a part of a peripheral portion from a circular first substrate made of a single crystal of a compound semiconductor and forming a portion including the center of the first substrate as a first partial substrate; And a first bonding step of forming a first bonding substrate in which two or more first partial substrates are arranged and bonded on a first support substrate having a diameter larger than that of the substrate. Manufacturing method.
2. In the partial substrate forming step, the first substrate is cut by two straight lines that are orthogonal to a reference point whose distance from the center is equal to or less than the radius and are equiangular with the diameter passing through the reference point, A portion including a center is formed as a first partial substrate, and in the first bonding step, the reference point is made to correspond to the approximate center of the first support substrate and cut along the straight line on the first support substrate. 4. arranging and bonding the four first partial substrates so that the portions are in contact with each other; The manufacturing method of the compound semiconductor substrate of description.
3. In the partial substrate forming step, the first partial substrate is further cut by two straight lines perpendicular to each other on a diameter passing through the reference point, and formed into a quadrilateral. The manufacturing method of the compound semiconductor substrate of description.
4). In the first bonding step, the n 2 (n is a natural number of 2 or more) first partial substrates are arranged and bonded on the first support substrate so that the sides are in contact with each other. The manufacturing method of the compound semiconductor substrate of description.
5. 4. In the first bonding step, the four first partial substrates are arranged and bonded on the first support substrate so that the reference point corresponds to the approximate center of the first support substrate. The manufacturing method of the compound semiconductor substrate of description.
6). A second bonding step of bonding a second support substrate to a surface of the first partial substrate arrayed and bonded on the first support substrate; and removing the first support substrate to form a second bond substrate. A first removal step to be formed. To 5. The manufacturing method of the compound semiconductor substrate in any one of.
7). A hydrogen layer forming step of forming a hydrogen layer at a predetermined depth from a surface of the first partial substrate of the first bonded substrate or the second bonded substrate; and a third support substrate on the surface of the first partial substrate. A third bonding step in which a first thin film layer made of a single crystal of the compound semiconductor is formed on the third support substrate by separating the first partial substrate in the hydrogen layer by bonding a third bonding step to be bonded; And a separation step to obtain 6. The manufacturing method of the compound semiconductor substrate of description.
8). The compound semiconductor is one of SiC, gallium oxide, and GaN. To 7. The manufacturing method of the compound semiconductor substrate in any one of.
9. A compound semiconductor substrate in which a first thin film layer made of a single crystal of a compound semiconductor is bonded onto a support substrate, wherein the first thin film layer is divided into two or more first partial thin film layers, and each of the first thin film layers A compound semiconductor substrate, wherein the partial thin film layers are arranged in contact with each other.
10. The first thin film layer is divided into four first partial thin film layers having a fan-shaped surface with a central angle of 90 degrees, and arranged so that the first partial thin film layers are in contact with each other around the center of the support substrate. Said 9. The compound semiconductor substrate as described.
11. 8. The compound semiconductor is one of SiC, gallium oxide, and GaN. Or 10. A compound semiconductor substrate according to 1.

本発明の化合物半導体基板の製造方法によれば、化合物半導体の単結晶からなる円形の第１基板から少なくともその周縁部の一部を除去し、前記第１基板の中心を含む部分を第１部分基板として形成する部分基板形成工程と、前記第１基板よりも直径の大きい第１支持基板上に、２以上の前記第１部分基板を配列して接合した第１接合基板を形成する第１接合工程と、を含むため、化合物半導体の単結晶からなる小口径の第１基板を第１支持基板上に組み合わせて、大口径の単結晶基板を形成することができる。第１接合基板は、更に別の支持基板との接合、分離等の工程を経て、最終的には基板の周縁部の形状を整えることによって、円形或いは円盤形の半導体基板を構成することができる。基板を組み合わせるための加工費用により製造コストは高くなるが、製造された第１接合基板をそのまま素子基板として使用するのではなく、更に接合基板を構成するための種基板として使用すれば、多くの枚数の接合基板に充当することができ、大口径の接合基板を安価に実現することが可能になる。また、小口径の単結晶基板の方が結晶欠陥密度は低いため、これを組み合わせた基板の結晶欠陥密度は低くすることができる。
前記部分基板形成工程において、前記第１基板を、その中心からの距離が半径以下である基準点において直交し且つ前記基準点を通る直径に対して等角となる２つの直線により切断し、前記中心を含む部分を第１部分基板として形成し、前記第１接合工程において、前記第１支持基板上に、前記第１支持基板の略中心に前記基準点を対応させ且つ前記直線で切断された部分が相互に接するように４つの前記第１部分基板を配列して接合する場合には、第１基板を少なくとも２辺が直交するように切除して形成した、扇形、四辺形等の任意の形状の第１部分基板を形成することができる。そして、２以上の第１部分基板を第１支持基板の平面上に組み合わせて第１接合基板を形成することができる。また、隣り合う第１部分基板が接する境界線部には結晶の不連続が存在することになるが、これを半導体素子形成時のスクライブラインに当てることにより、損失とはならないようすることができる。 According to the method for manufacturing a compound semiconductor substrate of the present invention, at least a part of the peripheral portion is removed from a circular first substrate made of a single crystal of a compound semiconductor, and a portion including the center of the first substrate is a first portion. A partial substrate forming step for forming a substrate, and a first bonding for forming a first bonding substrate in which two or more first partial substrates are arranged and bonded on a first support substrate having a diameter larger than that of the first substrate. A large-diameter single crystal substrate can be formed by combining a small-diameter first substrate made of a compound semiconductor single crystal on the first support substrate. The first bonded substrate can be formed into a circular or disk-shaped semiconductor substrate by finalizing the shape of the peripheral edge of the substrate through steps such as bonding and separation with another support substrate. . Manufacturing costs increase due to processing costs for combining the substrates, but if the manufactured first bonded substrate is not used as an element substrate as it is, but if it is used as a seed substrate for constituting the bonded substrate, many A large number of bonded substrates can be realized at a low cost. Further, since the single-crystal substrate having a small diameter has a lower crystal defect density, the crystal defect density of a substrate in which this is combined can be lowered.
In the partial substrate forming step, the first substrate is cut by two straight lines that are orthogonal to a reference point whose distance from the center is equal to or less than the radius and are equiangular with the diameter passing through the reference point, A portion including a center is formed as a first partial substrate, and in the first bonding step, the reference point is made to correspond to the approximate center of the first support substrate and cut along the straight line on the first support substrate. When the four first partial substrates are arranged and bonded so that the portions are in contact with each other, the first substrate is formed by cutting out the first substrate so that at least two sides are orthogonal to each other, such as a sector shape or a quadrilateral shape. A first partial substrate having a shape can be formed. Then, the first bonded substrate can be formed by combining two or more first partial substrates on the plane of the first support substrate. Further, although there is a discontinuity of crystal at the boundary line portion where the adjacent first partial substrates are in contact with each other, it is possible to prevent a loss by applying this to the scribe line at the time of forming the semiconductor element. .

前記部分基板形成工程において、前記第１部分基板は、更に前記基準点を通る直径上で直交する２つの直線によって切断され、四辺形に形成される場合には、第１基板と第１支持基板の大きさに応じて、第１部分基板を正方形等の四辺形に形成することができ、取扱い性をよくすることができる。
前記第１接合工程において、前記第１支持基板上に、ｎ２個（ｎは２以上の自然数）の前記第１部分基板を相互に辺が接するように配列して接合する場合には、第１支持基板の大きさに応じて、４、９、１６個等の第１部分基板を整然と配列することができる。
前記第１接合工程において、前記第１支持基板上に、前記第１支持基板の略中心に前記基準点を対応させて４つの前記第１部分基板を配列して接合する場合には、各第１支持基板の境界線部を半導体素子形成時のスクライブラインとすることができる。 In the partial substrate forming step, when the first partial substrate is further cut by two straight lines perpendicular to each other on the diameter passing through the reference point and formed into a quadrilateral, the first substrate and the first support substrate Depending on the size, the first partial substrate can be formed in a quadrilateral shape such as a square, and the handleability can be improved.
In the first bonding step, when n 2 (n is a natural number of 2 or more) first partial substrates are arranged on the first support substrate so that the sides are in contact with each other, Depending on the size of one supporting substrate, 4, 9, 16, etc. first partial substrates can be arranged in an orderly manner.
In the first bonding step, when the four first partial substrates are arranged and bonded on the first support substrate with the reference point corresponding to the approximate center of the first support substrate, The boundary line part of 1 support substrate can be used as the scribe line at the time of semiconductor element formation.

前記第１支持基板上に配列して接合された前記第１部分基板の表面に、第２支持基板を接合する第２接合工程と、前記第１支持基板を除去することにより第２接合基板を形成する第１除去工程と、を含む場合には、第２支持基板を支持基板とし、その上に第１部分基板が組み合わされた第２接合基板を形成することができる。第２接合工程においては、第１部分基板の表面と第２支持基板とを、強固且つ高温度に耐えられるように接合することができ、種基板として好適である。
前記第１接合基板又は前記第２接合基板の前記第１部分基板の表面から所定の深さに水素層を形成する水素層形成工程と、前記第１部分基板の前記表面に第３支持基板を接合する第３接合工程と、前記第１部分基板を前記水素層において分離することにより、前記第３支持基板上に前記化合物半導体の単結晶からなる第１薄膜層が形成された第３接合基板を得る分離工程と、を含む場合には、第３支持基板を支持基板とし、その上に第１部分基板から分離された化合物半導体の単結晶からなる第１薄膜層が接合された第３接合基板を形成することができる。この第１薄膜層の厚さは薄くてよいため、前記第１接合基板上又は前記第２支持基板上に第１部分基板が組み合わされた第１接合基板又は第２接合基板を種基板として、第３支持基板上に第１薄膜層が接合された第３接合基板を多数製造することができる。第１接合基板又は第２接合基板は、小口径の第１基板と比べて大きな口径の種基板となる。
前記化合物半導体はＳｉＣ、酸化ガリウム及びＧａＮのうちの１つである場合には、前記接合基板上にそれぞれ高品質な半導体素子を形成することが可能になる。 A second bonding step of bonding a second support substrate to a surface of the first partial substrate arrayed and bonded on the first support substrate; and removing the first support substrate to form a second bond substrate. In the case of including the first removal step to be formed, a second bonding substrate in which the second supporting substrate is used as the supporting substrate and the first partial substrate is combined thereon can be formed. In the second bonding step, the surface of the first partial substrate and the second support substrate can be bonded so as to be strong and able to withstand high temperatures, which is suitable as a seed substrate.
A hydrogen layer forming step of forming a hydrogen layer at a predetermined depth from a surface of the first partial substrate of the first bonded substrate or the second bonded substrate; and a third support substrate on the surface of the first partial substrate. A third bonding step in which a first thin film layer made of a single crystal of the compound semiconductor is formed on the third support substrate by separating the first partial substrate in the hydrogen layer by bonding a third bonding step to be bonded; Including a third thin film layer made of a single crystal of a compound semiconductor separated from the first partial substrate, on which the third support substrate is used as a support substrate. A substrate can be formed. Since the thickness of the first thin film layer may be thin, the first bonded substrate or the second bonded substrate in which the first partial substrate is combined on the first bonded substrate or the second supporting substrate is used as a seed substrate. A large number of third bonded substrates in which the first thin film layer is bonded onto the third support substrate can be manufactured. The first bonded substrate or the second bonded substrate is a seed substrate having a larger diameter than the first substrate having a small diameter.
When the compound semiconductor is one of SiC, gallium oxide, and GaN, it is possible to form high-quality semiconductor elements on the bonding substrate.

本発明の化合物半導体基板によれば、化合物半導体の単結晶からなる第１薄膜層が支持基板上に接合された化合物半導体基板であって、前記第１薄膜層は２以上の第１部分薄膜層に分割されており、各前記第１部分薄膜層が相互に接するように配列されているため、小口径の化合物半導体の高品質な単結晶からなる第１薄膜層が支持基板上に組み合わされた、大口径の化合物半導体基板とすることができる。
また、前記第１薄膜層は表面が中心角９０度の扇形である４つの第１部分薄膜層に分割されており、前記支持基板の中心の回りに前記第１部分薄膜層が相互に接するように配列されている場合には、隣り合う第１部分薄膜層が接するため結晶の不連続が存在する境界線部を半導体素子のスクライブラインに当てることにより、損失とはならないように利用することができる。
前記化合物半導体はＳｉＣ、酸化ガリウム及びＧａＮのうちの１つである場合には、前記支持基板上にそれぞれ高品質な半導体素子を形成するために好適な化合物半導体基板となる。 According to the compound semiconductor substrate of the present invention, the first thin film layer made of a single crystal of the compound semiconductor is bonded to the support substrate, and the first thin film layer includes two or more first partial thin film layers. Since the first partial thin film layers are arranged so as to contact each other, the first thin film layer made of a high-quality single crystal of a small-diameter compound semiconductor is combined on the support substrate. A large-diameter compound semiconductor substrate can be obtained.
The first thin film layer is divided into four first partial thin film layers having a fan-shaped surface with a central angle of 90 degrees, and the first partial thin film layers are in contact with each other around the center of the support substrate. In the case where the first partial thin film layers are in contact with each other, the boundary portion where the discontinuity of the crystal exists is applied to the scribe line of the semiconductor element so that no loss occurs. it can.
When the compound semiconductor is one of SiC, gallium oxide, and GaN, the compound semiconductor substrate is suitable for forming high-quality semiconductor elements on the support substrate.

本発明について、本発明による典型的な実施形態の非限定的な例を挙げ、言及された複数の図面を参照しつつ以下の詳細な記述にて更に説明するが、同様の参照符号は図面のいくつかの図を通して同様の部品を示す。
第１基板から切り出される第１部分基板を示す平面図 ４枚の第１部分基板を組み合わせる例を示す平面図及び断面図 第１基板から切り出される四辺形の第１部分基板を示す平面図 ４枚の四辺形の第１部分基板を組み合わせる例を示す平面図及び断面図 ９枚の四辺形の第１部分基板を組み合わせる例を示す平面図及び断面図 ４枚の第１部分基板を支持基板に接合する例を示す平面図及び断面図 ４枚の第１部分基板を別の支持基板に接合する例を示す平面図及び断面図 ４枚の四辺形の第１部分基板を支持基板に接合する例を示す平面図及び断面図 ４枚の四辺形の第１部分基板を別の支持基板に接合する例を示す平面図及び断面図 第１接合工程、第２接合工程及び第１除去工程の例を示す模式的断面図 第１接合工程、第２接合工程及び第１除去工程の別の例を示す模式的断面図 水素層形成工程及び第３接合工程を示す模式的断面図 化合物半導体基板を示す模式的平面図及び断面図 The present invention will be further described in the following detailed description with reference to the drawings referred to, with reference to non-limiting examples of exemplary embodiments according to the present invention. Similar parts are shown throughout the several figures.
The top view which shows the 1st partial board | substrate cut out from the 1st board | substrate. Plan view and sectional view showing an example of combining four first partial substrates The top view which shows the quadrilateral first partial substrate cut out from the first substrate Plan view and sectional view showing an example of combining four quadrilateral first partial substrates Plan view and sectional view showing an example of combining nine quadrilateral first partial substrates A plan view and a sectional view showing an example in which four first partial substrates are bonded to a support substrate. A plan view and a sectional view showing an example in which four first partial substrates are bonded to another support substrate Plane view and sectional view showing an example of joining four quadrilateral first partial substrates to a support substrate Plane view and sectional view showing an example of joining four quadrangular first partial substrates to another support substrate Typical sectional drawing which shows the example of the 1st joining process, the 2nd joining process, and the 1st removal process Typical sectional drawing which shows another example of a 1st joining process, a 2nd joining process, and a 1st removal process. Schematic sectional view showing the hydrogen layer forming step and the third bonding step Schematic plan view and cross-sectional view showing a compound semiconductor substrate

以下、図を参照しながら、本発明を詳しく説明する。
ここで示される事項は例示的なもの及び本発明の実施形態を例示的に説明するためのものであり、本発明の原理と概念的な特徴とを最も有効に且つ難なく理解できる説明であると思われるものを提供する目的で述べたものである。この点で、本発明の根本的な理解のために必要である程度以上に本発明の構造的な詳細を示すことを意図してはおらず、図面と合わせた説明によって本発明の幾つかの形態が実際にどのように具現化されるかを当業者に明らかにするものである。 Hereinafter, the present invention will be described in detail with reference to the drawings.
The items shown here are for illustrative purposes and exemplary embodiments of the present invention, and are the most effective and easy-to-understand explanations of the principles and conceptual features of the present invention. It is stated for the purpose of providing what seems to be. In this respect, it is not intended to illustrate the structural details of the present invention beyond what is necessary for a fundamental understanding of the present invention. It will be clear to those skilled in the art how it is actually implemented.

本実施形態に係る化合物半導体基板の製造方法は、化合物半導体の単結晶からなる円形の第１基板（１）から少なくともその周縁部の一部を除去し、第１基板（１）の中心を含む部分を第１部分基板（１１、１２）として形成する部分基板形成工程と、第１基板（１）よりも直径の大きい第１支持基板（２）上に、２以上の第１部分基板（１１、１２）を配列して接合した第１接合基板（７１）を形成する第１接合工程と、を含んでいる。
前記部分基板形成工程において、第１基板（１）を、前記円形の中心（Ｃ１）からの距離が半径以下である基準点（Ｐ１）において直交し且つ基準点（Ｐ１）を通る直径（Ｄ）に対して等角となる２つの直線（１０１、１０２）により切断し、前記円形の中心（Ｃ１）を含む部分を第１部分基板（１１、１２）として形成し、前記第１接合工程において、第１支持基板（２）上に、第１支持基板（２）の略中心（Ｃ２）に前記基準点（Ｐ１）を対応させ且つ前記直線部分（１０１、１０２）が相互に接するように４つの第１部分基板（１１、１２）を配列して接合した第１接合基板（７１）を形成することができる。（図１〜９参照）。
前記部分基板形成工程において、別の第１部分基板（１２）は、更に前記基準点（Ｐ１）を通る直径（Ｄ）上で直交する２つの直線（１０３、１０４）によって切断された四辺形に形成することができる（図３〜５参照）。
また、化合物半導体基板の製造方法は、第１支持基板（２）上に配列して接合された第１部分基板（１１）の表面に、第２支持基板（３）を接合する第２接合工程と、第１支持基板（２）を除去することにより第２接合基板（７２）を形成する第１除去工程と、を含んでもよい（図１０、１１参照）。
更に、化合物半導体基板の製造方法は、第２接合基板（７２）の第１部分基板（１１）の表面から所定の深さに水素層（１５）を形成する水素層形成工程と、第１部分基板（１１）の前記表面に第３支持基板（４）を接合する第３接合工程と、第１部分基板（１１）を水素層（１５）において分離することにより、第３支持基板（４）上に前記化合物半導体の単結晶からなる第１薄膜層（１１０）が形成された第３接合基板（７３）を得る分離工程と、を含んでもよい（図１２参照）。 The method for manufacturing a compound semiconductor substrate according to the present embodiment removes at least a part of the peripheral edge from a circular first substrate (1) made of a single crystal of a compound semiconductor and includes the center of the first substrate (1). A partial substrate forming step of forming a portion as a first partial substrate (11, 12) and two or more first partial substrates (11) on a first support substrate (2) having a diameter larger than that of the first substrate (1). , 12), and a first bonding step for forming a first bonding substrate (71) bonded to each other.
In the partial substrate forming step, the diameter (D) of the first substrate (1) is orthogonal to the reference point (P1) whose distance from the circular center (C1) is equal to or less than the radius and passes through the reference point (P1). Are cut by two straight lines (101, 102) that are equiangular to each other, and a portion including the circular center (C1) is formed as a first partial substrate (11, 12). In the first bonding step, On the first support substrate (2), four reference points (P1) are made to correspond to the approximate center (C2) of the first support substrate (2) and the linear portions (101, 102) are in contact with each other. A first bonded substrate (71) in which the first partial substrates (11, 12) are arranged and bonded can be formed. (See FIGS. 1-9).
In the partial substrate forming step, the other first partial substrate (12) is further formed into a quadrilateral cut by two straight lines (103, 104) perpendicular to each other on a diameter (D) passing through the reference point (P1). Can be formed (see FIGS. 3-5).
Moreover, the manufacturing method of the compound semiconductor substrate includes a second bonding step of bonding the second support substrate (3) to the surface of the first partial substrate (11) arranged and bonded on the first support substrate (2). And a first removal step of forming the second bonded substrate (72) by removing the first support substrate (2) (see FIGS. 10 and 11).
Further, the method of manufacturing the compound semiconductor substrate includes a hydrogen layer forming step of forming a hydrogen layer (15) at a predetermined depth from the surface of the first partial substrate (11) of the second bonding substrate (72), and a first portion. By separating the first partial substrate (11) in the hydrogen layer (15) by a third bonding step of bonding the third support substrate (4) to the surface of the substrate (11), the third support substrate (4) And a separation step of obtaining a third bonding substrate (73) having a first thin film layer (110) made of a single crystal of the compound semiconductor formed thereon (see FIG. 12).

以下、図面を参照しつつ、本実施形態に係る化合物半導体基板の製造方法について具体的に説明する。
（部分基板形成工程）
前記部分基板形成工程では、化合物半導体の単結晶からなる円形の第１基板１から第１部分基板１１が切り出される。第１部分基板１１の形状やサイズは任意であり、後に接合される支持基板の大きさに応じて、無駄を少なくするように切出せばよい。
図１（ａ）は、化合物半導体の単結晶からなる円形の第１基板１を中心Ｃ１からの距離が半径以下である基準点Ｐ１において直交し、且つ基準点Ｐ１を通る直径Ｄに対して等角となる２つの直線１０１、１０２により切断し、中心Ｃ１を含む部分を第１部分基板１１として形成する例を示している。本例では、同図（ｂ）に示すように、第１部分基板１１は２つの直線部分（以下、「辺」という。）１０１、１０２と弧１１５とによって囲まれた形状となる。単結晶の第１基板１は、一般に周縁部では結晶欠陥が多くなる。このため、後に第１部分基板１１の組み合わせの中心となる基準点Ｐ１は、第１基板の外周よりも内側の位置とすることが好ましい。 Hereinafter, the method for manufacturing a compound semiconductor substrate according to the present embodiment will be specifically described with reference to the drawings.
(Partial substrate formation process)
In the partial substrate forming step, the first partial substrate 11 is cut out from the circular first substrate 1 made of a single crystal of a compound semiconductor. The shape and size of the first partial substrate 11 are arbitrary, and the first partial substrate 11 may be cut out so as to reduce waste according to the size of the support substrate to be bonded later.
FIG. 1A shows a circular first substrate 1 made of a single crystal of a compound semiconductor, perpendicular to a reference point P1 whose distance from the center C1 is equal to or less than a radius, and is equal to a diameter D passing through the reference point P1. An example is shown in which a portion including the center C1 is formed as the first partial substrate 11 by being cut by two straight lines 101 and 102 serving as corners. In this example, as shown in FIG. 5B, the first partial substrate 11 has a shape surrounded by two straight portions (hereinafter referred to as “sides”) 101 and 102 and an arc 115. The single-crystal first substrate 1 generally has many crystal defects at the periphery. For this reason, it is preferable that the reference point P1 that becomes the center of the combination of the first partial substrates 11 later is a position inside the outer periphery of the first substrate.

例えば、第１基板１の直径を６インチとする。図１（ａ）においては、ｘｙ座標の原点（０，０）に第１基板１の中心Ｃ１が位置し、第１基板１の直径は６（単位：インチ、以下同様。）である。基準点Ｐ１の座標は（２，−２）であり、辺１０１は基準点Ｐ１を通りｘ軸に平行、辺１０２は基準点Ｐ１を通りｙ軸に平行としている。同図（ｂ）に示す第１部分基板１１は、第１基板１を辺１０１及び辺１０２にそれぞれ対応する直線で裁断することにより切り出される。   For example, the diameter of the first substrate 1 is 6 inches. In FIG. 1A, the center C1 of the first substrate 1 is located at the origin (0, 0) of the xy coordinates, and the diameter of the first substrate 1 is 6 (unit: inch, the same applies hereinafter). The coordinates of the reference point P1 are (2, -2), the side 101 passes through the reference point P1 and is parallel to the x axis, and the side 102 passes through the reference point P1 and is parallel to the y axis. The first partial substrate 11 shown in FIG. 5B is cut out by cutting the first substrate 1 with straight lines corresponding to the sides 101 and 102, respectively.

図２は、４つの第１基板１からそれぞれ上記のように切り出した４つの第１部分基板１１ａ〜１１ｄを、各基準点Ｐ１ａ〜Ｐ１ｄを中心に集め、各辺１０１ａ〜１０１ｄ、１０２ａ〜１０２ｄが接するように組み合わせた図である。例えば、第１部分基板１１ａの一方の辺１０１ａは第１部分基板１１ｂの辺１０２ｂと接し、第１部分基板１１ａの他方の辺１０２ａは第１部分基板１１ｄの辺１０１ｄと接するように配置することができる。同図（ｂ）は（ａ）のＡＡ’断面を表している。   In FIG. 2, four first partial substrates 11a to 11d cut out from four first substrates 1 as described above are gathered around the respective reference points P1a to P1d, and the respective sides 101a to 101d and 102a to 102d are formed. It is the figure combined so that it might touch. For example, one side 101a of the first partial substrate 11a is in contact with the side 102b of the first partial substrate 11b, and the other side 102a of the first partial substrate 11a is arranged in contact with the side 101d of the first partial substrate 11d. Can do. FIG. 4B shows the AA ′ cross section of FIG.

第１基板１の直径が６インチである場合、第１部分基板１１の各辺の長さは最大４．２インチである。これは図１に示されたＣ１、Ｍ１、Ｍ２を頂点とする直角３角形において、Ｃ１−Ｍ１間の長さが３インチ、Ｃ１−Ｍ２間の長さが２インチであるから、Ｍ１−Ｍ２間の長さは２．２インチ、第１部分基板１１の各辺（１０１、１０２）の長さは最大４．２インチとなる。基準点Ｐ１は、結晶欠陥が多い第１基板１の周縁部を避けるため、第１基板１の外周よりも内側に位置している。したがって、図２に示すように４つの第１部分基板１１ａ〜１１ｄを配置したとき、単結晶部の寸法（Ｌ１）は最大８．４インチとなる。   When the diameter of the first substrate 1 is 6 inches, the length of each side of the first partial substrate 11 is a maximum of 4.2 inches. This is because the length between C1 and M1 is 3 inches and the length between C1 and M2 is 2 inches in the right triangle having apexes C1, M1 and M2 shown in FIG. The length between them is 2.2 inches, and the length of each side (101, 102) of the first partial substrate 11 is a maximum of 4.2 inches. The reference point P1 is located inside the outer periphery of the first substrate 1 in order to avoid the peripheral portion of the first substrate 1 having many crystal defects. Therefore, when the four first partial substrates 11a to 11d are arranged as shown in FIG. 2, the dimension (L1) of the single crystal portion is 8.4 inches at the maximum.

以上においては、第１基板１を基準点Ｐ１において直交する２つの直線１０１、１０２により切断することによって第１部分基板１１を形成する例を示したが、第１部分基板の形状はこれに限られない。第１部分基板１２は、更に前記基準点Ｐ１を通る直径Ｄ上で直交する２つの直線によって切断し、四辺形に形成することができる。四辺形の第１部分基板１２とすれば、その取り扱いが容易になる。
図３は、化合物半導体の単結晶からなる円形の第１基板１を中心Ｃ１からの距離が半径以下である基準点Ｐ１において直交し、且つ基準点Ｐ１を通る直径Ｄに対して等角となる２つの直線１０１、１０２により切断し、更に、基準点Ｐ１を通る直径Ｄ上で直交する２つの直線１０３、１０４によって切断することにより、第１部分基板１２を形成する例を示している。本例では、同図（ｂ）に示すように、第１部分基板１２は４つの直線部分（辺）１０１、１０２、１０３、１０４によって囲まれた正方形になる。単結晶の第１基板１は、一般に周縁部では結晶欠陥が多くなるため、後に第１部分基板１２の組み合わせの中心となる基準点Ｐ１は、第１基板の外周よりも内側の位置とすることが好ましい。 In the above, the example in which the first partial substrate 11 is formed by cutting the first substrate 1 by the two straight lines 101 and 102 orthogonal to the reference point P1 is shown. However, the shape of the first partial substrate is not limited thereto. I can't. The first partial substrate 12 can be further formed into a quadrilateral by cutting along two straight lines that are perpendicular to each other on the diameter D passing through the reference point P1. If the first partial substrate 12 is a quadrilateral, the handling becomes easy.
FIG. 3 shows that a circular first substrate 1 made of a single crystal of a compound semiconductor is orthogonal to a reference point P1 whose distance from the center C1 is equal to or less than the radius, and is equiangular with a diameter D passing through the reference point P1. An example is shown in which the first partial substrate 12 is formed by cutting along two straight lines 101 and 102 and further cutting along two straight lines 103 and 104 orthogonal to each other on the diameter D passing through the reference point P1. In this example, as shown in FIG. 5B, the first partial substrate 12 is a square surrounded by four straight portions (sides) 101, 102, 103, and 104. Since the single crystal first substrate 1 generally has many crystal defects at the peripheral portion, the reference point P1 that will be the center of the combination of the first partial substrates 12 later is set to a position inside the outer periphery of the first substrate. Is preferred.

例えば、第１基板１の直径を６インチとする。図３（ａ）においては、ｘｙ座標の原点（０，０）に第１基板１の中心Ｃ１が位置し、第１基板１の直径は６である。基準点Ｐ１の座標は（２，−２）であり、辺１０１は基準点Ｐ１を通りｘ軸に平行、辺１０２は基準点Ｐ１を通りｙ軸に平行としている。また、基準点Ｐ１を通る直径Ｄ上で直交する直線１０３はｘ軸に平行、直線１０４はｙ軸に平行である。同図（ｂ）に示す第１部分基板１２は、第１基板１を辺１０１、１０２、１０３及び１０４にそれぞれ対応する直線で裁断することにより切り出される。   For example, the diameter of the first substrate 1 is 6 inches. In FIG. 3A, the center C1 of the first substrate 1 is located at the origin (0, 0) of the xy coordinates, and the diameter of the first substrate 1 is 6. The coordinates of the reference point P1 are (2, -2), the side 101 passes through the reference point P1 and is parallel to the x axis, and the side 102 passes through the reference point P1 and is parallel to the y axis. Further, the straight line 103 orthogonal to the diameter D passing through the reference point P1 is parallel to the x axis, and the straight line 104 is parallel to the y axis. The first partial substrate 12 shown in FIG. 5B is cut out by cutting the first substrate 1 with straight lines corresponding to the sides 101, 102, 103, and 104, respectively.

図４は、４つの第１基板１からそれぞれ上記のように切り出した４つの第１部分基板１２ａ〜１２ｄを、各基準点Ｐ１ａ〜Ｐ１ｄを中心に集め、それぞれの２辺１０１ａ〜１０１ｄ、１０２ａ〜１０２ｄが接するように組み合わせた図である。例えば、第１部分基板１２ａの一つの辺１０１ａは第１部分基板１２ｂの辺１０２ｂと接し、第１部分基板１２ａの他方の辺１０２ａは第１部分基板１２ｄの辺１０１ｄと接するように配置することができる。同図（ｂ）は（ａ）のＡＡ’断面を表している。   In FIG. 4, four first partial substrates 12a to 12d cut out from four first substrates 1 as described above are gathered around the respective reference points P1a to P1d, and the two sides 101a to 101d, 102a to It is the figure combined so that 102d may touch. For example, one side 101a of the first partial substrate 12a is in contact with the side 102b of the first partial substrate 12b, and the other side 102a of the first partial substrate 12a is arranged in contact with the side 101d of the first partial substrate 12d. Can do. FIG. 4B shows the AA ′ cross section of FIG.

第１基板１の直径が６インチである場合、第１部分基板１２の各辺の長さは最大４．２インチである。これは図３に示されたＣ１、Ｍ１、Ｍ２を頂点とする直角３角形において、Ｃ１−Ｍ１間の長さが３インチ、Ｃ１−Ｍ２間の長さが２インチであるから、Ｍ１−Ｍ２間の長さは２．２インチ、第１部分基板１２の各辺（１０１〜１０４）の長さは最大４．２インチとなる。基準点Ｐ１は、結晶欠陥が多い第１基板１の周縁部を避けるため、第１基板１の外周よりも内側に位置している。したがって、図４に示すように４つの第１部分基板１２ａ〜１２ｄを配置したとき、単結晶部は１辺が最大８．４インチの四辺形になる。   When the diameter of the first substrate 1 is 6 inches, the length of each side of the first partial substrate 12 is a maximum of 4.2 inches. This is because the length between C1 and M1 is 3 inches and the length between C1 and M2 is 2 inches in the right triangle having apexes C1, M1 and M2 shown in FIG. The length between them is 2.2 inches, and the length of each side (101 to 104) of the first partial substrate 12 is a maximum of 4.2 inches. The reference point P1 is located inside the outer periphery of the first substrate 1 in order to avoid the peripheral portion of the first substrate 1 having many crystal defects. Therefore, when the four first partial substrates 12a to 12d are arranged as shown in FIG. 4, the single crystal portion has a quadrilateral shape with a maximum of 8.4 inches on one side.

図４では４個の第１部分基板１２を配列する例を示したが、第１部分基板１２の数は特に限定されず、例えばｎ２個（ｎは２以上の自然数）の第１部分基板１２を相互に辺が接するように配列することができる。
図５は、９個の第１部分基板１２（１２ａ〜１２ｉ）を３×３に配列する例を示している。更に、１６個の第１部分基板１２が４×４に配列されてもよい。図５において、９個の第１部分基板１２ａ〜１２ｉは正方形であり、それぞれの四辺を１０１ａ〜ｉ、１０２ａ〜ｉ、１０３ａ〜ｉ、１０４ａ〜ｉ、前記基準点をＰ１ａ〜ｉと表している。これにより１辺が第１部分基板１２の最大３倍の大きさの化合物半導体基板を構成することが可能となる。 FIG. 4 shows an example in which four first partial substrates 12 are arranged. However, the number of first partial substrates 12 is not particularly limited. For example, n 2 (n is a natural number of 2 or more) first partial substrates. 12 can be arranged so that the sides are in contact with each other.
FIG. 5 shows an example in which nine first partial substrates 12 (12a to 12i) are arranged in 3 × 3. Further, the 16 first partial substrates 12 may be arranged in 4 × 4. In FIG. 5, nine first partial substrates 12a to 12i are squares, and the four sides are denoted by 101a to i, 102a to i, 103a to i, 104a to i, and the reference point is denoted as P1a to i. . As a result, it is possible to form a compound semiconductor substrate whose one side is three times as large as the first partial substrate 12.

（第１接合工程）
前記第１接合工程において、第１基板１よりも直径の大きい第１支持基板２上に、第１支持基板２の略中心に前記基準点Ｐ１を対応させ且つ前記直線部分１０１、１０２が相互に接するように４つの第１部分基板（１１ａ〜１１ｄ、又は１２ａ〜１２ｄ）を配列して接合した第１接合基板７１を形成する。
図６は、４つの直径６インチの第１基板１から切り出された４つの第１部分基板１１ａ〜１１ｄを図２に示したように組み合わせ、直径８インチの第１支持基板２１上に搭載することによって形成された第１接合基板７１を表している。図６（ｂ）はそのＡＡ’断面を表している。前記のとおり、４つの第１部分基板１１ａ〜１１ｄからなる単結晶部の寸法は約８．４インチであるから、直径８インチの第１支持基板２１よりも大きくなる。
このような８インチサイズに対応した第１接合基板７１は、第１支持基板２１上に、接着材を介して第１部分基板１１ａ〜１１ｄを順に貼り合せることによって形成することができる。接着材を用いることにより、第１部分基板を精度よく第１支持基板上に貼り合せることができる。 (First joining process)
In the first bonding step, the reference point P1 is made to correspond to the approximate center of the first support substrate 2 on the first support substrate 2 having a diameter larger than that of the first substrate 1, and the linear portions 101 and 102 are mutually connected. A first bonded substrate 71 is formed by arranging and bonding the four first partial substrates (11a to 11d or 12a to 12d) so as to be in contact with each other.
In FIG. 6, four first partial substrates 11a to 11d cut from four first substrates 1 having a diameter of 6 inches are combined as shown in FIG. 2 and mounted on a first support substrate 21 having a diameter of 8 inches. The 1st joining board | substrate 71 formed by this is represented. FIG. 6B shows the AA ′ cross section. As described above, since the size of the single crystal portion including the four first partial substrates 11a to 11d is about 8.4 inches, it is larger than the first support substrate 21 having a diameter of 8 inches.
The first bonding substrate 71 corresponding to the 8-inch size can be formed on the first support substrate 21 by sequentially bonding the first partial substrates 11a to 11d with an adhesive. By using the adhesive, the first partial substrate can be bonded onto the first support substrate with high accuracy.

図７は、上記と同様にして、４つの直径６インチの第１基板１から切り出された４つの第１部分基板１１ａ〜１１ｄを、直径１０インチの第１支持基板２２上に搭載することによって形成された第１接合基板７１を表している。４つの第１部分基板１１ａ〜１１ｄからなる単結晶部の寸法は約８．４インチであるから、直径１０インチの第１支持基板２２よりも小さくなる。このため、第１支持基板２２上の周縁部４か所に単結晶部が存在しない欠損部２２１が生じる。しかし、第１支持基板２２全体に対して欠損部２２１の面積は小さいため、半導体素子を形成するための基板として影響はわずかであるといえる。このようにして、１０インチサイズに対応した第１接合基板７１を形成することができる。   FIG. 7 is similar to the above in that four first partial substrates 11a to 11d cut out from four first substrates 1 having a diameter of 6 inches are mounted on a first support substrate 22 having a diameter of 10 inches. The formed first bonded substrate 71 is shown. Since the size of the single crystal portion including the four first partial substrates 11a to 11d is about 8.4 inches, the size is smaller than that of the first support substrate 22 having a diameter of 10 inches. For this reason, the defect | deletion part 221 in which a single crystal part does not exist in the peripheral part 4 places on the 1st support substrate 22 arises. However, since the area of the defect portion 221 is small with respect to the entire first support substrate 22, it can be said that the influence as a substrate for forming a semiconductor element is slight. In this manner, the first bonded substrate 71 corresponding to the 10-inch size can be formed.

図８は、４つの直径６インチの第１基板１から切り出された４つの第１部分基板１２ａ〜１２ｄを図４に示したように組み合わせ、直径８インチの第１支持基板２１上に搭載することによって形成された第１接合基板７１を表している。図８（ｂ）はそのＡＡ’断面を表している。前記のとおり、４つの第１部分基板１２ａ〜１２ｄからなる単結晶部の１辺は約８．４インチであるから、直径８インチの第１支持基板２１よりも大きくなる。
このような８インチサイズに対応した第１接合基板７１は、第１支持基板２１上に、接着材を介して第１部分基板１２ａ〜１２ｄを順に貼り合せることによって形成することができる。接着材を用いることにより、第１部分基板を精度よく第１支持基板上に貼り合せることができる。 In FIG. 8, four first partial substrates 12a to 12d cut out from four first substrates 1 having a diameter of 6 inches are combined as shown in FIG. 4 and mounted on a first support substrate 21 having a diameter of 8 inches. The 1st joining board | substrate 71 formed by this is represented. FIG. 8B shows the AA ′ cross section. As described above, since one side of the single crystal portion including the four first partial substrates 12a to 12d is about 8.4 inches, it is larger than the first support substrate 21 having a diameter of 8 inches.
The first bonding substrate 71 corresponding to the 8-inch size can be formed on the first support substrate 21 by sequentially bonding the first partial substrates 12a to 12d with an adhesive. By using the adhesive, the first partial substrate can be bonded onto the first support substrate with high accuracy.

図９は、上記と同様にして、４つの直径６インチの第１基板１から切り出された４つの第１部分基板１２ａ〜１２ｄを、直径１０インチの第１支持基板２２上に搭載することによって形成された第１接合基板７１を表している。４つの第１部分基板１２ａ〜１２ｄからなる単結晶部の１辺は約８．４インチであるから、直径１０インチの第１支持基板２２上の周縁部４か所に単結晶部が存在しない欠損部２２３が生じる。しかし、第１支持基板２２全体に対して欠損部２２３の面積は小さいため、半導体素子を形成するための基板として影響はわずかであるといえる。このようにして、１０インチサイズに対応した第１接合基板７１を形成することができる。   FIG. 9 is similar to the above in that four first partial substrates 12a to 12d cut out from four first substrates 1 having a diameter of 6 inches are mounted on a first support substrate 22 having a diameter of 10 inches. The formed first bonded substrate 71 is shown. Since one side of the single crystal portion composed of the four first partial substrates 12a to 12d is about 8.4 inches, there are no single crystal portions at four peripheral portions on the first support substrate 22 having a diameter of 10 inches. A defect 223 is generated. However, since the area of the defect portion 223 is small with respect to the entire first support substrate 22, it can be said that the influence as a substrate for forming a semiconductor element is slight. In this manner, the first bonded substrate 71 corresponding to the 10-inch size can be formed.

前記のとおり、第１部分基板１２の数は４個に限らず、９個（図５参照）、１６個等と増すことができる。よって、第１部分基板１２を配列したサイズに応じた直径の第１支持基板２を使用することにより、より大口径の第１接合基板７１を形成することができる。そして、大口径の第１接合基板７１又は第２接合基板７２（後述）を形成することにより、それを種基板として大口径の化合物半導体基板となる第３接合基板７３（後述）を製造することができる。これによって、大口径化が難しいワイドバンドギャップ半導体基板の大口径化が可能になる。また、大口径化を目的とする場合に限らず、小口径の高品質な化合物半導体基板（第１基板１）を組み合わせて品質の良い小口径の化合物半導体基板を得ることも可能である。   As described above, the number of first partial substrates 12 is not limited to four, but can be increased to nine (see FIG. 5), sixteen, and the like. Therefore, by using the first support substrate 2 having a diameter corresponding to the size in which the first partial substrates 12 are arranged, the first bonded substrate 71 having a larger diameter can be formed. Then, by forming the large-diameter first bonded substrate 71 or the second bonded substrate 72 (described later), the third bonded substrate 73 (described later) to be a large-diameter compound semiconductor substrate is manufactured using the first bonded substrate 71 or the second bonded substrate 72 (described later) as a seed substrate. Can do. This makes it possible to increase the diameter of a wide band gap semiconductor substrate that is difficult to increase in diameter. In addition to the purpose of increasing the diameter, it is also possible to obtain a high-quality small-diameter compound semiconductor substrate by combining a small-diameter high-quality compound semiconductor substrate (first substrate 1).

（サークルカット）
以上のように形成された第１接合基板７１は、第１支持基板２（２１、２２）の大きさに合わせて切断（サークルカット）することができる。これにより、第１接合基板７１の外周は、第１支持基板２（２１、２２）の大きさに整えられる。サークルカットの位置は、必ずしも第１支持基板２（２１、２２）の大きさに合わせる必要はなく、やや小さめにサークルカットされてもよい。これにより、直径８インチ又は１０インチの第１接合基板７１が形成される。 (Circle cut)
The first bonded substrate 71 formed as described above can be cut (circle cut) in accordance with the size of the first support substrate 2 (21, 22). Thereby, the outer periphery of the 1st joining board | substrate 71 is adjusted to the magnitude | size of the 1st support substrate 2 (21, 22). The position of the circle cut is not necessarily matched with the size of the first support substrate 2 (21, 22), and the circle may be cut slightly smaller. Thereby, the first bonding substrate 71 having a diameter of 8 inches or 10 inches is formed.

（第２接合工程、第１除去工程）
図１０は、第１接合基板７１の表面、すなわち第１支持基板２（２１、２２）上に配列して接合された第１部分基板（１１、１２）の表面に、第２支持基板３を接合する第２接合工程と、その後、第１支持基板２を除去することにより第２接合基板７２を形成する第１除去工程を示している。本図では、第１接合基板７１はサークルカットにより外周が整えられたものとして描いているが、外周が整えられていない状態（図６〜９参照）であってもよい。第２接合基板７２は、後に形成される接合基板の種基板とすることができる。第１接合基板７１を形成する際には、接着剤等を用いて第１支持基板２上に第１支持基板２（２１、２２）を精度よく貼り合わせたが、接合基板の種基板とするためには１０００℃近い高温に耐える必要がある。第１接合基板７１の接合部が高温度に耐えられない場合には、第１部分基板（１１、１２）を第２支持基板３に貼り替えることができる。 (Second joining step, first removing step)
FIG. 10 shows the second support substrate 3 on the surface of the first bonding substrate 71, that is, the surface of the first partial substrate (11, 12) arranged and bonded on the first support substrate 2 (21, 22). A second bonding step for bonding and a first removal step for forming the second bonding substrate 72 by removing the first support substrate 2 are shown. In this drawing, the first bonded substrate 71 is depicted as having an outer periphery that has been trimmed by circle cutting, but may be in a state in which the outer periphery is not trimmed (see FIGS. 6 to 9). The second bonding substrate 72 can be a seed substrate for a bonding substrate to be formed later. When the first bonded substrate 71 is formed, the first support substrate 2 (21, 22) is accurately bonded to the first support substrate 2 using an adhesive or the like. Therefore, it is necessary to endure a high temperature close to 1000 ° C. When the joint portion of the first joint substrate 71 cannot withstand a high temperature, the first partial substrate (11, 12) can be replaced with the second support substrate 3.

図１０（ａ）は、サークルカットにより、第１支持基板２（２１、２２）上に第１部分基板（１１、１２）が搭載された第１接合基板７１の周縁部が除去されている状態（ＡＡ’断面）を示している。
同図（ｂ）は、第２接合工程により、上記第１接合基板７１の第１部分基板（１１、１２）側の表面に、第２支持基板３が接合された状態を表している。第２支持基板３のサイズは、第１接合基板７１のサイズに応じて、８インチ、１０インチ等とすることができる。また、単結晶からなる第１部分基板（１１、１２）すなわち第１基板１の材料がＳｉＣである場合には、第２支持基板３は線膨張係数が同じ多結晶ＳｉＣ基板とすることが好ましい。接合の方法は特に問わず、例えば、第１部分基板（１１、１２）の表面及び第２支持基板３の表面を平坦化した上で、アルゴンビーム等により両表面を活性化し、常温にて接合することができる。このように接合すれば、高温度に耐えられる接合基板の種基板を得ることができる。
同図（ｃ）は、第１除去工程により、第１支持基板２（２１、２２）を剥離除去して第２接合基板７２を形成した状態を示す。剥離の方法は特に問わず、例えば、第１支持基板２として透明な無アルカリガラス等を使用し、光硬化接着材を用いて第１部分基板（１１、１２）と接合した場合には、高温とすることにより容易に剥離することができる。
図１１（ａ）〜（ｃ）は、第１接合基板７１において単結晶部の欠損部（２２１、２２３等）が存在している場合を示している。この場合にも構造上の問題はなく、前図（ａ）〜（ｃ）と同様にして第２接合基板７２を形成することができる。
以上により、８インチ又は１０インチサイズの第２接合基板７２を得ることができ、この第２接合基板７２は接合基板の種基板として好適である。 FIG. 10A shows a state in which the peripheral portion of the first bonding substrate 71 on which the first partial substrate (11, 12) is mounted on the first support substrate 2 (21, 22) is removed by circle cutting. (AA 'cross section) is shown.
FIG. 4B shows a state in which the second support substrate 3 is bonded to the surface of the first bonded substrate 71 on the first partial substrate (11, 12) side in the second bonding step. The size of the second support substrate 3 can be 8 inches, 10 inches, or the like depending on the size of the first bonding substrate 71. When the first partial substrate (11, 12) made of single crystal, that is, the material of the first substrate 1 is SiC, the second support substrate 3 is preferably a polycrystalline SiC substrate having the same linear expansion coefficient. . The bonding method is not particularly limited. For example, the surfaces of the first partial substrate (11, 12) and the surface of the second support substrate 3 are flattened, and both surfaces are activated by an argon beam or the like, and bonded at room temperature. can do. By bonding in this way, a seed substrate of a bonded substrate that can withstand high temperatures can be obtained.
FIG. 6C shows a state in which the first bonding substrate 72 is formed by peeling and removing the first support substrate 2 (21, 22) in the first removal step. The peeling method is not particularly limited. For example, when transparent non-alkali glass or the like is used as the first support substrate 2 and is bonded to the first partial substrate (11, 12) using a photo-curing adhesive, the temperature is high. It can be easily peeled off.
FIGS. 11A to 11C show the case where single crystal portion defects (221, 223, etc.) are present in the first bonding substrate 71. FIG. Also in this case, there is no structural problem, and the second bonding substrate 72 can be formed in the same manner as in the previous drawings (a) to (c).
As described above, the second bonded substrate 72 having a size of 8 inches or 10 inches can be obtained, and the second bonded substrate 72 is suitable as a seed substrate for the bonded substrate.

（水素層形成工程、第３接合工程、分離工程）
本実施形態には、前記第１接合基板７１又は前記第２接合基板７２の第１部分基板（１１、１２）の表面から所定の深さに水素層１５を形成する水素層形成工程と、第１部分基板（１１、１２）の前記表面に第３支持基板４を接合する第３接合工程と、第１部分基板（１１、１２）を水素層１５において分離することにより、第３支持基板４上に前記化合物半導体の単結晶からなる第１薄膜層１１０が形成された第３接合基板７３を得る分離工程と、を含むことができる。これにより、第２接合基板７２を種基板として、多数の接合基板（第３接合基板７３）を得ることができる。
図１２は、上記水素層形成工程、第３接合工程及び分離工程を表している。
同図（ａ）に示されるように、第２接合基板７２は、第２支持基板３の全面に第１部分基板（１１、１２）が接合されて構成されている。水素層形成工程においては、その第１部分基板（１１、１２）の表面（図における下面）から一定の深さ（例えば、約０．５μｍの深さ）に水素イオンを注入することにより、水素層１５を形成する。この水素層１５から第１部分基板（１１、１２）の表面までの単結晶表層部を第１薄膜層１１０とする。
同図（ｂ）は、第１部分基板（１１、１２）の上記表面に第３支持基板４を接合した状態を示している。接合方法は特に問わず、例えば、第１部分基板（１１、１２）すなわち第１薄膜層１１０の表面と第３支持基板４の表面を平坦に加工し、両表面をアルゴンビーム等により活性化した状態で常温接合が可能である。
その後、約１０００℃の高温度にすることにより、第１部分基板（１１、１２）は水素層１５において分離される。これによって、同図（ｃ）に示すように、水素層１５において分離された第１薄膜層１１０が、第３支持基板４上に接合された第３接合基板７３を得ることができる。第１部分基板（１１、１２）の厚さ、即ち第１基板１の厚さが１００μｍであったとすると、第１薄膜層１１０が１回分離されることにより厚さが１μｍ程度減少するのみであるから、剥離後に研磨等することにより、１つの第２接合基板７２を種基板として数百回の再利用が可能である。
なお、第２支持基板３上に単結晶層が形成された第２接合基板７２を種基板とすることに限らず、第１支持基板２上に単結晶層が形成された第１接合基板７１を種基板とすることも可能である。この場合には、第１支持基板２と第１部分基板（１１、１２）とを接合する接合層を、耐熱性の高いものとすればよい。 (Hydrogen layer forming step, third joining step, separation step)
In the present embodiment, a hydrogen layer forming step of forming a hydrogen layer 15 at a predetermined depth from the surface of the first partial substrate (11, 12) of the first bonding substrate 71 or the second bonding substrate 72, By separating the first partial substrate (11, 12) in the hydrogen layer 15, a third bonding step of bonding the third support substrate 4 to the surface of the partial substrate (11, 12), the third support substrate 4 And a separation step of obtaining a third bonding substrate 73 on which the first thin film layer 110 made of a single crystal of the compound semiconductor is formed. Accordingly, a large number of bonded substrates (third bonded substrates 73) can be obtained using the second bonded substrate 72 as a seed substrate.
FIG. 12 shows the hydrogen layer forming step, the third bonding step, and the separation step.
As shown in FIG. 6A, the second bonded substrate 72 is configured by bonding the first partial substrates (11, 12) to the entire surface of the second support substrate 3. In the hydrogen layer forming step, hydrogen ions are implanted at a certain depth (for example, a depth of about 0.5 μm) from the surface (lower surface in the figure) of the first partial substrate (11, 12), thereby Layer 15 is formed. A single crystal surface layer portion from the hydrogen layer 15 to the surface of the first partial substrate (11, 12) is defined as a first thin film layer 110.
FIG. 4B shows a state where the third support substrate 4 is bonded to the surface of the first partial substrate (11, 12). The bonding method is not particularly limited. For example, the first partial substrate (11, 12), that is, the surface of the first thin film layer 110 and the surface of the third support substrate 4 are processed to be flat, and both surfaces are activated by an argon beam or the like. Normal temperature bonding is possible in the state.
Thereafter, the first partial substrate (11, 12) is separated in the hydrogen layer 15 by raising the temperature to about 1000 ° C. As a result, as shown in FIG. 5C, a third bonded substrate 73 in which the first thin film layer 110 separated in the hydrogen layer 15 is bonded onto the third support substrate 4 can be obtained. If the thickness of the first partial substrate (11, 12), that is, the thickness of the first substrate 1 is 100 μm, the thickness is only reduced by about 1 μm by separating the first thin film layer 110 once. Therefore, it is possible to reuse the second bonded substrate 72 several hundred times by using the second bonded substrate 72 as a seed substrate by polishing after peeling.
Note that the first bonded substrate 71 in which the single crystal layer is formed on the first support substrate 2 is not limited to the second bonded substrate 72 having the single crystal layer formed on the second support substrate 3 as a seed substrate. Can be used as a seed substrate. In this case, the bonding layer for bonding the first support substrate 2 and the first partial substrates (11, 12) may be made to have high heat resistance.

（エピタキシャル層形成工程）
更に、図１２（ｄ）に示すように、第３接合基板７３の第１薄膜層１１０表面を研摩等して、その上にエピタキシャル層５を形成した接合基板７４を得ることができる。エピタキシャル層５の厚さは１０μｍ程度とすることができ、このエピタキシャル層５が半導体素子における能動層となる。
エピタキシャル層５は、４つの第１部分基板（１１、１２）から形成された第１薄膜層１１０の上に成膜されるため、エピタキシャル層５においても、各第１部分基板（１１、１２）の境界線部に当たる部分に結晶性が不連続となる接合線部５１が存在することとなる。この接合線部５１は、半導体素子の形成時にスクライブラインに当てることができる。このため、接合線部５１の視認性が不十分であれば、同図（ｄ）に示す段階で、印刷等によりマスクアライメント用のマーキングを施すことができる。 (Epitaxial layer formation process)
Furthermore, as shown in FIG. 12D, the surface of the first thin film layer 110 of the third bonding substrate 73 is polished or the like, and the bonding substrate 74 having the epitaxial layer 5 formed thereon can be obtained. The thickness of the epitaxial layer 5 can be about 10 μm, and this epitaxial layer 5 becomes an active layer in the semiconductor element.
Since the epitaxial layer 5 is formed on the first thin film layer 110 formed from the four first partial substrates (11, 12), each first partial substrate (11, 12) is also formed in the epitaxial layer 5. The joint line portion 51 where the crystallinity becomes discontinuous exists at the portion corresponding to the boundary line portion. The joint line portion 51 can be applied to a scribe line when forming a semiconductor element. For this reason, if the visibility of the joining line part 51 is inadequate, the marking for mask alignment can be given by printing etc. in the step shown to the same figure (d).

上記のように接合基板７４を基に形成された接合基板を、最終的な化合物半導体基板７５とすることができる。化合物半導体基板７５は、化合物半導体の単結晶からなる第１薄膜層１１０が支持基板４上に接合された化合物半導体基板であって、第１薄膜層１１０は２以上の第１部分薄膜層に分割されており、各第１部分薄膜層が相互に接するように配列されて構成されている。
図１３は、化合物半導体基板７５の模式的な上面図及び断面図である。本例においては、第１薄膜層１１０は表面が中心角９０度の扇形である４つの第１部分薄膜層１１０ａ〜１１０ｄに分割されており、支持基板４の中心の回りに第１部分薄膜層１１０ａ〜１１０ｄが相互に接するように配列されて構成されている。上記化合物半導体は、ＳｉＣ、酸化ガリウム及びＧａＮのうちから選択可能である。また、化合物半導体基板７５は、第１部分薄膜層１１０ａ〜１１０ｄの表面上にエピタキシャル層５が形成された基板とすることができる。
化合物半導体基板７５のサイズは特に問わないが、例えば、直径１０インチ、１２インチ等とすることができる。
また、化合物半導体基板７５には、第１部分薄膜層１１０ａ〜１１０ｄの境界線部を視認させるためのマーキングを備えることができる。このマーキングにより、第１部分薄膜層１１０ａ〜１１０ｄの境界線部（エピタキシャル層５の接合線部５１）を、半導体素子の形成に際してスクライブラインに当てることができ、無駄のない半導体基板として利用することができる。 A bonded substrate formed based on the bonded substrate 74 as described above can be used as the final compound semiconductor substrate 75. The compound semiconductor substrate 75 is a compound semiconductor substrate in which a first thin film layer 110 made of a single crystal of a compound semiconductor is bonded to a support substrate 4, and the first thin film layer 110 is divided into two or more first partial thin film layers. The first partial thin film layers are arranged so as to be in contact with each other.
FIG. 13 is a schematic top view and cross-sectional view of the compound semiconductor substrate 75. In this example, the first thin film layer 110 is divided into four first partial thin film layers 110 a to 110 d whose surfaces are fan-shaped with a central angle of 90 degrees, and the first partial thin film layer is arranged around the center of the support substrate 4. 110a to 110d are arranged to be in contact with each other. The compound semiconductor can be selected from SiC, gallium oxide, and GaN. The compound semiconductor substrate 75 can be a substrate in which the epitaxial layer 5 is formed on the surfaces of the first partial thin film layers 110a to 110d.
The size of the compound semiconductor substrate 75 is not particularly limited, but may be, for example, 10 inches or 12 inches in diameter.
Further, the compound semiconductor substrate 75 can be provided with markings for visually recognizing the boundary portions of the first partial thin film layers 110a to 110d. By this marking, the boundary line part (the joint line part 51 of the epitaxial layer 5) of the first partial thin film layers 110a to 110d can be applied to the scribe line when forming the semiconductor element, and used as a lean semiconductor substrate. Can do.

本実施形態に係る化合物半導体基板及びその製造方法により、大口径化が難しいワイドバンドギャップ基板の大口径化を可能にすることができる。この化合物半導体基板は、４枚からなる第１部分薄膜層１１０の境界線部５１をスクライブラインとすることにより無駄のないように利用することができる。９個、１６個等の第１部分薄膜層が配列されて第１薄膜層１１０が構成されている場合には、それらの境界線部を任意の素子サイズのスクライブラインに充当することは困難になる。すなわち、１つの境界線部はスクライブラインに当てることができるが、他の境界線部はピッチが合わなくなり、スクライブラインに当てることができない。例えば９個の第１部分薄膜層が組み合わされて（図５参照）第１薄膜層１１０が形成されている場合には、縦１列、横１行だけがスクライブラインと一致しないので無駄はごく一部となる。更に無駄を減らすためには、素子サイズに合わせて第１部分基板１２の大きさを設定するようにすることができる。
以上においては、６インチの化合物半導体基板を用いて、８インチ又は１０インチの種基板を構成する例を示したが、４インチの化合物半導体基板を用いて、６インチの種基板を構成することも、全く同様に可能である。また、化合物半導体基板として、主としてＳｉＣ基板の例を述べたが、ＧａＮ、酸化ガリウムなどのワイドバンドギャップ材料にも同様に適用することができる。
最終的な支持基板（第３支持基板４）は、多結晶ＳｉＣ基板に限らず、水素層での剥離に必要な温度以上の高い耐熱性があればよく、例えば、サファイア基板でも、Ｓｉ基板でもよい。
仮設の支持基板（第１支持基板２）は、無アルカリガラスのみならず透明基板であれば、第１部分基板との接合に光硬化型接着剤を使うことができる。その他、接着剤を使う場合には、材料を問わない。Ｓｉ基板を使い捨ての仮設支持基板として用いることも可能である。 With the compound semiconductor substrate and the manufacturing method thereof according to the present embodiment, it is possible to increase the diameter of a wide band gap substrate that is difficult to increase in diameter. This compound semiconductor substrate can be used without waste by using the boundary line portion 51 of the four first partial thin film layers 110 as a scribe line. If the first thin film layer 110 is configured by arranging nine, sixteen, etc. first partial thin film layers, it is difficult to apply the boundary line portion to a scribe line of an arbitrary element size. Become. That is, one boundary line part can be applied to the scribe line, but the other boundary line part cannot be applied to the scribe line because the pitch does not match. For example, when nine first partial thin film layers are combined (see FIG. 5) to form the first thin film layer 110, only one column and one row do not coincide with the scribe line, so that waste is extremely high. Become part. In order to further reduce waste, the size of the first partial substrate 12 can be set in accordance with the element size.
In the above, an example in which a 6-inch compound semiconductor substrate is used to form an 8-inch or 10-inch seed substrate has been shown. However, a 4-inch compound semiconductor substrate is used to form a 6-inch seed substrate. Is possible in exactly the same way. Moreover, although the example of the SiC substrate was mainly described as the compound semiconductor substrate, it can be similarly applied to wide band gap materials such as GaN and gallium oxide.
The final support substrate (third support substrate 4) is not limited to a polycrystalline SiC substrate, and may have a high heat resistance higher than the temperature necessary for peeling in the hydrogen layer. For example, a sapphire substrate or a Si substrate may be used. Good.
If the temporary support substrate (first support substrate 2) is not only alkali-free glass but also a transparent substrate, a photo-curable adhesive can be used for bonding to the first partial substrate. In addition, a material is not ask | required when using an adhesive agent. It is also possible to use a Si substrate as a disposable temporary support substrate.

ＳｉＣ等を用いた高電圧駆動素子は、車においてはハイブリッド車の普及、電気自動車の普及に伴ってますます重要度が増している。家庭においてはスマートグリッドの普及に伴って家電製品の電動化やエネルギー管理のために高電圧素子の役割が重要になってくる。本発明により、大口径且つ高品質の化合物半導体基板が製造可能になり、ワイドバンドギャップ素子の低コスト化に貢献することができる。   High-voltage drive elements using SiC or the like are becoming more and more important in vehicles with the spread of hybrid vehicles and electric vehicles. In homes, the role of high-voltage elements becomes important for the electrification and energy management of home appliances with the spread of smart grids. According to the present invention, a large-diameter and high-quality compound semiconductor substrate can be manufactured, which can contribute to cost reduction of a wide band gap device.

１；第１基板、１１、１２；第１部分基板、１１０；第１薄膜層（第１部分薄膜層）、２、２１、２２；第１支持基板、３；第２支持基板、４；支持基板（第３支持基板）、５；エピタキシャル層、７１；第１接合基板、７２；第２接合基板、７３；第３接合基板、７４；接合基板、７５；化合物半導体基板。   DESCRIPTION OF SYMBOLS 1; 1st board | substrate, 11, 12; 1st partial board | substrate, 110; 1st thin film layer (1st partial thin film layer) 2, 21, 22; 1st support board | substrate, 3; 2nd support board | substrate, 4; Substrate (third support substrate), 5; epitaxial layer, 71; first bonded substrate, 72; second bonded substrate, 73; third bonded substrate, 74; bonded substrate, 75;

Claims (11)

化合物半導体の単結晶からなる円形の第１基板から少なくともその周縁部の一部を除去し、前記第１基板の中心を含む部分を第１部分基板として形成する部分基板形成工程と、
前記第１基板よりも直径の大きい第１支持基板上に、２以上の前記第１部分基板を配列して接合した第１接合基板を形成する第１接合工程と、
を含むことを特徴とする化合物半導体基板の製造方法。 A partial substrate forming step of removing at least a part of a peripheral portion from a circular first substrate made of a single crystal of a compound semiconductor and forming a portion including the center of the first substrate as a first partial substrate;
A first bonding step of forming a first bonding substrate in which two or more first partial substrates are arranged and bonded on a first support substrate having a diameter larger than that of the first substrate;
A method for producing a compound semiconductor substrate, comprising: 前記部分基板形成工程において、前記第１基板を、その中心からの距離が半径以下である基準点において直交し且つ前記基準点を通る直径に対して等角となる２つの直線により切断し、前記中心を含む部分を第１部分基板として形成し、
前記第１接合工程において、前記第１支持基板上に、前記第１支持基板の略中心に前記基準点を対応させ且つ前記直線で切断された部分が相互に接するように４つの前記第１部分基板を配列して接合する、請求項１記載の化合物半導体基板の製造方法。 In the partial substrate forming step, the first substrate is cut by two straight lines that are orthogonal to a reference point whose distance from the center is equal to or less than the radius and are equiangular with the diameter passing through the reference point, Forming a portion including the center as a first partial substrate;
In the first bonding step, the four first portions are arranged on the first support substrate so that the reference points correspond to the approximate center of the first support substrate and the portions cut by the straight line are in contact with each other. The method of manufacturing a compound semiconductor substrate according to claim 1, wherein the substrates are arranged and bonded. 前記部分基板形成工程において、前記第１部分基板は、更に前記基準点を通る直径上で直交する２つの直線によって切断され、四辺形に形成される請求項２記載の化合物半導体基板の製造方法。   3. The method of manufacturing a compound semiconductor substrate according to claim 2, wherein in the partial substrate forming step, the first partial substrate is further cut by two straight lines orthogonal to each other on a diameter passing through the reference point to form a quadrilateral. 前記第１接合工程において、前記第１支持基板上に、ｎ２個（ｎは２以上の自然数）の前記第１部分基板を相互に辺が接するように配列して接合する請求項３記載の化合物半導体基板の製造方法。 In the first joining step, the first supporting substrate, n 2 pieces (n is a natural number of 2 or more) of claim 3 wherein the joining are arranged as mutual edges contact the first portion substrate A method of manufacturing a compound semiconductor substrate. 前記第１接合工程において、前記第１支持基板上に、前記第１支持基板の略中心に前記基準点を対応させて４つの前記第１部分基板を配列して接合する請求項４記載の化合物半導体基板の製造方法。   5. The compound according to claim 4, wherein, in the first bonding step, four first partial substrates are arranged and bonded on the first support substrate so that the reference point corresponds to the approximate center of the first support substrate. A method for manufacturing a semiconductor substrate. 前記第１支持基板上に配列して接合された前記第１部分基板の表面に、第２支持基板を接合する第２接合工程と、
前記第１支持基板を除去することにより第２接合基板を形成する第１除去工程と、
を含む請求項１乃至５のいずれかに記載の化合物半導体基板の製造方法。 A second bonding step of bonding a second support substrate to the surface of the first partial substrate arrayed and bonded on the first support substrate;
A first removal step of forming a second bonded substrate by removing the first support substrate;
The manufacturing method of the compound semiconductor substrate in any one of Claims 1 thru | or 5 containing these. 前記第１接合基板又は前記第２接合基板の前記第１部分基板の表面から所定の深さに水素層を形成する水素層形成工程と、
前記第１部分基板の前記表面に第３支持基板を接合する第３接合工程と、
前記第１部分基板を前記水素層において分離することにより、前記第３支持基板上に前記化合物半導体の単結晶からなる第１薄膜層が形成された第３接合基板を得る分離工程と、
を含む請求項６記載の化合物半導体基板の製造方法。 A hydrogen layer forming step of forming a hydrogen layer at a predetermined depth from the surface of the first partial substrate of the first bonding substrate or the second bonding substrate;
A third bonding step of bonding a third support substrate to the surface of the first partial substrate;
Separating the first partial substrate in the hydrogen layer to obtain a third bonding substrate in which a first thin film layer made of a single crystal of the compound semiconductor is formed on the third support substrate;
The manufacturing method of the compound semiconductor substrate of Claim 6 containing this. 前記化合物半導体はＳｉＣ、酸化ガリウム及びＧａＮのうちの１つである請求項１乃至７のいずれかに記載の化合物半導体基板の製造方法。   The method of manufacturing a compound semiconductor substrate according to claim 1, wherein the compound semiconductor is one of SiC, gallium oxide, and GaN. 化合物半導体の単結晶からなる第１薄膜層が支持基板上に接合された化合物半導体基板であって、
前記第１薄膜層は２以上の第１部分薄膜層に分割されており、各前記第１部分薄膜層が相互に接するように配列されていることを特徴とする化合物半導体基板。 A compound semiconductor substrate in which a first thin film layer made of a single crystal of a compound semiconductor is bonded on a support substrate,
The compound semiconductor substrate, wherein the first thin film layer is divided into two or more first partial thin film layers, and the first partial thin film layers are arranged in contact with each other. 前記第１薄膜層は表面が中心角９０度の扇形である４つの第１部分薄膜層に分割されており、前記支持基板の中心の回りに前記第１部分薄膜層が相互に接するように配列されている請求項９記載の化合物半導体基板。   The first thin film layer is divided into four first partial thin film layers having a fan-shaped surface with a central angle of 90 degrees, and arranged so that the first partial thin film layers are in contact with each other around the center of the support substrate. The compound semiconductor substrate according to claim 9. 前記化合物半導体はＳｉＣ、酸化ガリウム及びＧａＮのうちの１つである請求項９又は１０に記載の化合物半導体基板。   The compound semiconductor substrate according to claim 9 or 10, wherein the compound semiconductor is one of SiC, gallium oxide, and GaN.
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