CN110660766A - 半导体器件和形成半导体器件的方法 - Google Patents
半导体器件和形成半导体器件的方法 Download PDFInfo
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- CN110660766A CN110660766A CN201910575233.7A CN201910575233A CN110660766A CN 110660766 A CN110660766 A CN 110660766A CN 201910575233 A CN201910575233 A CN 201910575233A CN 110660766 A CN110660766 A CN 110660766A
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Abstract
半导体器件包括位于第一衬底上方的第一互连结构、位于第一互连结构上方的第一接合层、设置在第一接合层的第一区域中的多个第一接合焊盘,第一接合焊盘具有第一间距以及设置在第一接合层的第二区域中的多个第二接合焊盘,第二区域在第一接合层的第一边缘和第一区域之间延伸,第二接合焊盘具有第一间距,多个第二接合焊盘包括多对相邻的第二接合焊盘,其中,每个相应对的第二接合焊盘通过第一金属线连接。本申请的实施例还涉及形成半导体器件的方法。
Description
技术领域
本申请的实施例涉及半导体器件和形成半导体器件的方法。
背景技术
在晶圆至晶圆接合技术中,已经发展了多种方法来将两个封装组件(诸如晶圆)接合在一起。一些晶圆接合方法包括熔融接合、共晶接合、直接金属接合、混合接合等。在熔融接合中,晶圆的氧化物表面接合至另一晶圆的氧化物表面或硅表面。在共晶接合中,将两种共晶材料放在一起,并且施加高压和高温。因此共晶材料熔化。当熔化的共晶材料固化时,晶圆接合在一起。在直接金属至金属接合中,两个金属焊盘在升高的温度下彼此压靠,并且金属焊盘的相互扩散使得金属焊盘接合。在混合接合中,两个晶圆的金属焊盘通过直接金属至金属接合而彼此接合,并且两个晶圆的一个的氧化物表面接合至另一晶圆的氧化物表面或硅表面。
发明内容
本发明的实施例提供了一种半导体器件,包括:第一互连结构,位于第一衬底上方;第一接合层,位于所述第一互连结构上方;多个第一接合焊盘,设置在所述第一接合层的第一区域中,所述第一接合焊盘具有第一间距;以及多个第二接合焊盘,设置在所述第一接合层的第二区域中,所述第二区域在所述第一接合层的第一边缘和所述第一区域之间延伸,所述第二接合焊盘具有所述第一间距,所述多个第二接合焊盘包括多对相邻的第二接合焊盘,其中,每个相应对的第二接合焊盘通过第一金属线连接。
本发明的另一实施例提供了一种形成半导体器件的方法,包括:在半导体衬底上方沉积介电层;在所述介电层中蚀刻第一接合焊盘开口和第二接合焊盘开口,其中,所述第一接合焊盘开口与所述半导体衬底的一个或多个侧壁相邻,其中,每个第二接合焊盘开口与至少一个第一接合焊盘开口相邻;在所述介电层中蚀刻沟槽,每个沟槽均在所述至少一个第一接合焊盘开口和至少一个第二接合焊盘开口之间延伸;在所述第一接合焊盘开口内沉积导电材料以形成第一接合焊盘,在所述第二接合焊盘开口内沉积导电材料,以形成第二接合焊盘,并且在所述沟槽内形成导电材料以形成所述第一接合焊盘和所述第二接合焊盘之间的电连接;以及使用平坦化工艺去除过量的导电材料。
本发明的又一实施例提供了一种形成半导体器件的方法,包括:形成第一半导体器件,包括:在第一衬底上形成互连结构;在所述互连结构上形成第一接合层;以及在所述第一接合层中形成第一接合焊盘,其中,所述第一多个第一接合焊盘包括由多条第一导线并联连接的多组相邻的第一接合焊盘;形成第二半导体器件,包括:在第二衬底上形成第二接合层;以及在所述第二接合层中形成第二接合焊盘,其中,所述第一多个第二接合焊盘包括由多条第二导线并联连接的多组相邻的第二接合焊盘;以及将所述第一接合层接合至所述第二接合层,将所述第一接合层接合至所述第二接合层包括将所述第一多个第一接合焊盘接合至所述第一多个第二接合焊盘。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1A至图1B示出了根据一些实施例的用于形成封装结构的工艺中的中间步骤的截面图。
图2A至图2B示出了根据一些实施例的用于形成另一封装结构的工艺中的中间步骤的截面图和平面图。
图3A至图3E示出了根据一些实施例的具有接合结构的半导体器件的截面图和平面图。
图4A至图4D示出了根据一些实施例的用于形成半导体器件中的接合结构的工艺中的中间步骤的截面图。
图5A至图5B示出了根据一些实施例的具有接合结构的半导体器件的截面图和平面图。
图6A至图6E示出了根据一些实施例的用于形成半导体器件中的接合结构的工艺中的中间步骤的截面图。
图7A至图7H示出了根据一些实施例的用于形成封装结构的工艺中的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
图1A至图1B示出了根据一些实施例的示例性半导体器件100和示例性晶圆200。随后可以例如使用拾取和放置工艺将半导体器件100和晶圆200接合在一起,或以形成封装器件的一部分。半导体器件100包括衬底102和形成衬底102上方的部件。衬底102可以是掺杂(例如,掺杂有p型或n型掺杂剂)或未掺杂的半导体衬底,诸如块状半导体、绝缘体上半导体(SOI)衬底等。通常,SOI衬底包括形成在绝缘层上的半导体材料层。绝缘层可以是例如埋氧(BOX)层、氧化硅层等。绝缘层设置在通常为硅或玻璃衬底的衬底上。可以使用诸如多层或梯度衬底的其它衬底。在一些实施例中,衬底的半导体材料可以包括硅;锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。如图1A所示,衬底102可以具有介于约100μm和约800μm之间的厚度T1,并且可以具有介于约5000μm和约60000μm之间的尺寸(即,长度或宽度)L1。
在一些实施例中,半导体器件100可以是诸如存储器件、逻辑器件、功率器件、这些的组合等的半导体器件,其被设计为与封装件内的其它器件一起工作,其它器件包括晶圆200内的器件或结构。然而,可以使用任何合适的功能。在一些实施例中,在衬底102的顶面上形成集成电路器件。集成电路器件可以包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。此处未示出集成电路器件的细节。在一些实施例中,半导体器件100用于形成中介层。在这样的实施例中,在衬底102上不形成诸如晶体管或二极管的有源器件。可以(或可以不)在半导体器件100中形成的诸如电容器、电阻器、电感器等的无源器件。在半导体器件100是中介层的实施例中,衬底102也可以是介电衬底。此外,可以形成通孔(未示出)以穿透衬底102,以互连衬底102的相对侧上的组件。
半导体器件100还包括设置在形成在衬底102的一侧上的接合层106内的多个接合焊盘104。接合焊盘104可以由导电材料形成,并且可以电连接至半导体器件100内的集成电路器件、金属线、互连件、通孔或其它部件。在一些情况下,一个或多个金属层(未示出)可以设置在衬底102和接合层106之间。在一些实施例中,接合焊盘104可以具有介于约5μm和约25μm之间的初始(即,在接合或安装至接合头之前)间距P1。在一些实施例中,接合焊盘可以设置在衬底102的两侧上。
晶圆200包括衬底202、介电层206和接合焊盘204。衬底202可以类似于如上所述的半导体器件100的衬底102,或可以与衬底102不同。介电层206或接合焊盘204可以分别类似于半导体器件100的表面接合层106或接合焊盘104,或可以不同。晶圆200的接合焊盘204可以对应于半导体器件100的接合焊盘104。例如,在将半导体器件100接合至晶圆200之后,相应的接合焊盘104和接合焊盘204可以制成半导体器件100和晶圆200之间的电连接。
图1B示出了在减薄(例如,通过化学机械抛光(CMP)工艺)并且安装至接合头150之后的图1A中所示的半导体器件100。例如,接合头150可以用于将半导体100接合至晶圆200,以作为拾取和放置工艺的一部分。在一些情况下,在安装至接合头150之前,可以将半导体器件100减薄至介于约7μm和约100μm之间的厚度T2。在一些情况下,将半导体器件100安装至接合头150可以使得半导体器件100弯曲成弯曲形状,如图1B所示。作为说明性实例,在图1A中,接合层106的外表面151具有相对水平的形状,但是在图1B中,接合层106的外表面151具有弯曲形状。在一些实施例中,接合头150被配置为产生半导体器件100的翘曲。
在一些情况下,半导体器件100的翘曲导致接合层106的外表面151扩展,这也可能增加一些或所有接合焊盘104的间距。例如,由于半导体器件100在安装至接合头150(图1B所示)时的翘曲,接合焊盘104可以具有翘曲间距P2,该翘曲间距P2大于未安装的半导体器件100(图1A中所示)的初始间距P1。在一些情况下,翘曲半导体器件100的一些区域可以具有与半导体器件100的其它区域不同的间距。例如,更靠近翘曲半导体器件100的边缘的区域可以比更靠近中心的区域具有更大的间距。对于接合焊盘104的间距从初始间距P1增加至翘曲间距P2的情况,半导体器件100的一些或所有接合焊盘104可能不能与晶圆202的相应的接合焊盘204精确对准。在一些情况下,相应的接合焊盘之间的未对准可能导致增加的电阻或开路连接。这种未对准可能更接近半导体器件100的边缘。例如,如图1B所示,半导体器件100的中心附近的相应接合焊盘之间的未对准D1小于半导体器件100的边缘附近的相应接合焊盘之间的未对准D2。在一些情况下,半导体器件100的翘曲可能导致相应接合焊盘之间的未对准多达约3000nm。在一些情况下,在接合之前相应接合焊盘的未对准(例如,图1B)可以与接合后的未对准不同(例如,图3A)。
转至图2A至图2B,根据一些实施例示出了半导体器件100和晶圆200。半导体器件100和晶圆200可以类似于上面参考图1A至图1B描述的那些。在图2A中,半导体器件100示出为安装至接合头150,但是为了清楚起见,未示出半导体器件100的翘曲。图2B示出了半导体器件100的平面图,如图2A所示的视图B-B表示的。图2A示出了穿过如图2B所示的截面A-A的截面图。图2A至图2B示出了半导体器件100的接合焊盘的间距由于半导体器件100的翘曲而增加,如前所述。
在一些实施例中,半导体器件100包括内部区域112和外部区域114,内部区域112包括内部接合焊盘105,外部区域114包括接合结构120。在一些实施例中,接合结构120的每个均包括通过并联连接件电连接在一起的两个或多个外部接合焊盘107,下面将更详细地描述。通过连接外部区域114中的多个外部接合焊盘107,可以减少由于接合未对准(诸如上面参考图1B所描述的)引起的电阻效应。内部接合焊盘105和/或外部接合焊盘107可以类似于先前描述的接合焊盘104。在一些实施例中,外部区域114中的接合结构120或外部接合焊盘107的初始间距(在一个或两个垂直方向上)可以与内部区域112的内部接合焊盘105的初始间距(在一个或两个垂直方向上)大致相同。在一些实施例中,外部区域114或内部区域112可以都包括内部接合焊盘105和外部接合焊盘107。在一些实施例中,晶圆200还可以包括内部区域212和外部区域214,内部区域212具有内部接合焊盘205,并且外部区域214具有外部接合结构220和外部接合焊盘207。内部区域212、内部接合焊盘205、外部区域214或外部接合结构220可以类似于参考半导体器件100描述的相应部件。
图2B中所示的半导体器件100具有总宽度W1和总长度L1。作为说明性实例,外部区域114被示出为从半导体器件100的边缘向内延伸宽度W2和长度L2的区域。在一些实施例中,外部区域114的宽度W2或长度L2可以被限定为总宽度W1或总长度L1的分数。例如,宽度W2或长度L2可以分别限定为总宽度W1或总长度L1的约5%和约20%之间,诸如小于约10%。例如,宽度W2可以是总宽度W1的约10%,但是可以使用其它分数值。宽度W2占总宽度W1的分数可以与总长度L1的长度L2的分数相同,或宽度W2可以与长度L2具有不同的分数值。在一些情况下,宽度W2或长度L2的距离或分数值可以基于预期膨胀量或预期未对准量来确定。例如,在一些情况下,由于未对准引起的诸如增加的电阻的问题在宽度W2内可能是最严重的,该宽度W2是总宽度W1的约10%,但是在其它情况下可以使用其它距离或分数值。外部区域114还可以从半导体器件100的相对或相邻边缘延伸不同的距离。
图2B示出的外部区域114包括两行外部接合焊盘107(在宽度W2内)和两列外部接合焊盘107(在长度L2内),但是其它实施例可以在宽度W2内具有一行或多于两行的外部接合焊盘107或在长度L4内可以具有一列或多于两列的外部接合焊盘107。在一些情况下,宽度W2或长度L2可以基于外部接合焊盘107的行数或列数或基于初始间距的倍数来限定。在一些情况下,外部区域114的尺寸由由于安装至接合头150而引起的半导体器件100的翘曲确定。在一些实施例中,内部区域112和外部区域114之间的边界可以具有矩形以外的形状,诸如十字形、椭圆形等。
转至图3A至图3E,根据一些实施例示出了接合的半导体结构300。在图3A至图3E所示的实施例中,外部接合结构的电连接的外部接合焊盘之间的并联连接件形成在与外部接合焊盘相同的层中。接合的半导体结构300包括接合至晶圆200的半导体器件100。半导体器件100和晶圆200可以类似于上面参考图2A至图2B描述的那些。接合的半导体结构300包括内部区域312和外部区域314,其可以类似于先前描述的内部区域112或外部区域114。在内部区域312中,半导体器件100和晶圆200通过半导体器件100的内部接合焊盘105和晶圆200的内部接合焊盘205电连接。在外部区域314中,半导体器件100和晶圆200通过半导体器件100的外部接合结构120和晶圆200的外部接合结构220电连接。图3A示出了接合的半导体结构300的截面图。图3B至图3E示出了接合的半导体结构300的示例性实施例的平面图,该平面图包括内部区域312的具有示例性内部接合焊盘105和内部接合焊盘205的部分并且包括外部区域314的具有示例性外部接合结构120和外部接合结构220的部分。图3A至图3E示出了半导体器件100和晶圆200由于半导体器件100的翘曲(如先前描述的)而在接合之后具有未对准的情况。
如图3B至图3E所示,半导体器件100的外部接合结构120包括通过一个或多个并联连接件121连接的两个外部接合焊盘107,并且晶圆200的外部接合结构220包括通过一个或多个并联连接件221连接的两个外部接合焊盘207。如图3A至图3E所示,并联连接件121可以与外部焊盘107设置在相同的层中,并且并联连接件221可以与外部焊盘207设置在相同的层中。在一些实施例中,并联连接件121(或221)是连接相邻对的外部接合焊盘107(或207)的金属线。外部接合焊盘107可以具有与内部接合焊盘105相同的初始间距,并且外部接合焊盘207可以具有与内部接合焊盘205相同的初始间距。并联连接件121(或221)的宽度W3可以小于、约等于或大于外部接合焊盘107(或207)的尺寸。例如,图3B示出的并联连接件121的宽度W3小于外部接合焊盘107的直径。在一些实施例中,并联连接件121(或221)可以具有介于约500nm和约3500nm之间的宽度W3。图3B示出了具有矩形形状的并联连接件121(和并联连接件221),但是在其它实施例中,并联连接件121(或221)沿着其长度可以具有多于一个的宽度W3或者具有不同的形状,诸如弯曲形状、梯形形状、具有一个或多个锥形部分的形状、不规则形状或其它形状。
在图3A至图3E所示的实施例中,外部接合焊盘107和并联连接件121都设置在接合层106的外部层中。外部接合焊盘107和并联连接件121的顶面基本共面并且包括未由接合层106覆盖的部分。通过这种方式,外部接合焊盘107和并联连接件121都可以用于外部接合结构120,以在半导体器件100接合至晶圆200时形成电连接件。例如,晶圆200的外部接合结构220可以包括设置在介电层206的外部层中的外部接合焊盘207和并联连接件221,以制成与外部接合结构120的电连接。在一些实施例中,半导体器件100的外部接合结构120接合至晶圆200的相应接合部件(诸如外部接合结构220、接合焊盘或其它类型的部件)以形成电连接。通过使用除了多个外部接合焊盘107(或207)的表面之外的并联连接件121(或221)的表面用于半导体器件100和晶圆200之间的一些接合电连接,可以增加接合的电连接件的重叠接触面积,这可能降低接合的电连接件的接触电阻。另外,如果存在未对准(诸如图3A至图3E中所示的示例性未对准),则外部接合结构120(或220)的增加的面积可以允许增加重叠接触面积。通过这种方式,由于未对准引起的接合的电连接件的接触电阻可以在半导体器件100的边缘附近(未对准可能更明显的位置)减小。
图3C至图3E示出了外部接合结构的另外的示例性实施例。半导体器件100的外部接合结构320A至320H可以类似于先前描述的外部接合结构120。为清楚起见,晶圆200的外部接合结构未标记,但是可以类似于外部接合结构120或320A至320H。在一些实施例中,半导体器件100上的外部接合结构120可以与它们接合至的晶圆200上的相应外部接合结构220具有不同的配置。图3B至图3E中所示的实施例是非限制性和说明性实例,并且未示出的其它配置、布置或特征的组合均旨在本发明的范围内。
图3C示出了示例性外部接合结构320A和示例性外部接合结构320B。外部接合结构320A类似于外部接合结构120,除了并联连接件121的宽度与外部接合焊盘107的直径大致相同之外。外部接合结构320B类似于外部接合结构120,除了相邻的外部接合焊盘107通过两个并联连接件121连接之外。图3D示出了外部接合结构320C和外部接合结构320D。外部接合结构320C包括电连接在一起的三个外部接合焊盘107,其中,并联连接件121在每对相邻的外部接合焊盘107之间延伸。外部接合结构320D类似于外部接合结构320C,除了相邻的外部接合焊盘107之间的并联连接件121具有不同的宽度之外。在其它实施例中,连接多个外部接合焊盘107的并联连接件121可以具有不同的形状,或不同数量的并联连接件121可以在相邻的外部接合焊盘107的不同连接对之间延伸。
图3E示出了外部区域314的拐角,其包括示例性外部接合结构320E至320H。例如,外部区域314的拐角可以靠近半导体器件100的拐角。外部接合结构320E包括具有锥形形状的并联连接件121,其中,并联连接件在一个外部接合焊盘107处比在相对的外部接合焊盘107处具有更大的宽度。外部接合结构320F包括具有锥形形状的并联连接件121,其中,并联连接件121的中心比并联连接件121的任一端具有更小的宽度。这些是示例性的,并且具有锥形部分或具有不同宽度的部分的其它形状的并联连接件121也是可能的。外部接合结构320G类似于所描述的其它外部接合结构,除了连接的外部接合焊盘107沿着第一边缘设置并且垂直于沿着第二边缘设置的连接的外部接合焊盘107(例如,在外部接合结构中320E至320F中)定向。通过这种方式,外部接合焊盘107可以在同一器件上以不同的取向连接。例如,每对连接的外部接合焊盘107的取向可以由半导体器件100在安装至接合头150之后的预期翘曲来确定。在一些情况下,器件的连接的外部接合焊盘107可以全部具有相同的取向。外部接合结构320H包括三个外部接合焊盘107,其通过具有两个不同取向的并联连接件121连接。在一些情况下,如果未对准沿着多于一个方向,则具有以不同取向连接的外部接合焊盘107可以有助于改进电连接。
图4A至图4D示出了根据一些实施例的半导体器件400中的接合结构的形成中的中间阶段的截面图。半导体器件400可以类似于先前描述的半导体器件100或晶圆200。如图4A至图4D所示,半导体器件400可以具有内部区域412和外部区域414,其可以类似于先前描述的内部区域112和外部区域114。半导体器件400包括衬底402,在衬底402上可以形成可选的互连结构408。衬底402可以类似于先前描述的衬底102。互连结构408可以包括一层或多层,诸如层间介电(ILD)层,其电连接至存在于衬底402中的部件,诸如有源器件、无源器件、导线等。互连结构408可以包括导电部件,诸如金属线410或通孔411。
互连结构408可以由一种或多种介电材料的一层或多层形成。在一些实施例中,互连结构408的层由具有低于约3.0的k值的低k介电材料或具有小于约2.5的k值的超低k(ELK)介电材料形成。在一些实施例中,互连结构408的层由氧化硅、氮化硅、碳化硅(SiC)、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)等形成。在一些实施例中,互连结构408可以包括其它层,诸如蚀刻停止层或扩散阻挡层(未示出)。
可以使用单镶嵌和/或双镶嵌工艺、先通孔工艺、先金属工艺或其它工艺来形成互连结构408的金属线410或通孔411。在一些实施例中,形成互连结构的层,并且使用可接受的光刻和蚀刻技术在其中形成开口。扩散阻挡层(未示出)可以形成在开口中并且可以包括诸如TaN、Ta、TiN、Ti、CoW等的材料,并且可以通过诸如CVD、ALD等的沉积工艺形成在开口中。导电材料可以在开口中由铜、铝、镍、钨、钴、银、它们的组合等形成,并且可以通过电化学镀工艺、CVD、ALD、PVD等或它们的组合形成在开口中的扩散阻挡层上方。在形成扩散阻挡层和导电材料之后,可以通过诸如CMP的平坦化工艺去除过量的扩散阻挡层和导电材料,从而在该层的开口中留下金属线410。然后可以重复该工艺以在其中形成互连结构408和金属线410和通孔411的多个层。
转至图4B,在互连结构408上方形成接合层406。接合层406可以类似于先前描述的接合层106。接合层406可以由介电材料形成,并且可以是诸如氧化硅、SiON、SiN等的含硅材料,或可以是另一类型的介电材料。接合层406可以通过诸如CVD、PECVD、PVD、ALD等的沉积工艺或它们的组合形成。在一些实施例中,接合层406形成为具有介于约900nm和约8000nm之间的厚度。
转至图4C,在接合层406中形成焊盘开口416。焊盘开口416的示例性焊盘开口416A和416B在图4C中标记,并且在下面更详细地描述。可以使用可接受的光刻和蚀刻技术形成焊盘开口416。在实施例中,光刻工艺可以包括在接合层406上方形成光刻胶(未示出),用对应于焊盘开口416的开口图案化光刻胶,使焊盘开口416延伸穿过光刻胶并进入接合层406,并且然后去除光刻胶。光刻胶可以是单层光刻胶、双层光刻胶、三层光刻胶等。实施蚀刻工艺,从而使得焊盘开口416从接合层406的顶部延伸到接合层406的中间点。可以使用时间模式来实施将焊盘开口416蚀刻到这样的深度,并且可以在蚀刻已经实施预定时间段之后停止。在一些实施例中,接合层406可以包括中间蚀刻停止层,其用于确定焊盘开口416的蚀刻深度。还可以预期其它蚀刻和停止点检测技术。
如图4C所示,焊盘开口416包括形成在内部区域412中的内部焊盘开口416A和形成在外部区域414中的外部焊盘开口416B。内部焊盘开口416A对应于将形成内部接合焊盘的位置,并且外部焊盘开口416B对应于将形成外部接合结构420的位置,如下所述。在一些实施例中,外部焊盘开口416B可以包括随后在其中形成外部接合焊盘407的凹槽以及随后在其中形成并联连接件421的沟槽,如下所述。外部焊盘开口416的其它配置是可能的。在一些实施例中,内部焊盘开口416A可以均匀地间隔开一段距离,该距离对应于随后形成的内部接合焊盘的间距。
可以在接合层406中形成通孔开口418,如图4C所示。通孔开口418形成在焊盘开口416的底部,并且从焊盘开口416的底部延伸至接合层406的底面,从而暴露金属线410。可以使用可接受的光刻和蚀刻技术形成通孔开口418。光刻工艺可以包括在接合层406上方和焊盘开口416中形成光刻胶(未示出),用对应于通孔开口418的开口图案化光刻胶,使通孔开口418延伸穿过光刻胶和接合层406,并且然后去除光刻胶。光刻胶可以是单层光刻胶、双层光刻胶、三层光刻胶等。可以在互连结构408和接合层406之间形成蚀刻停止层(未示出)。在这样的实施例中,通孔开口418可以在形成之后暴露蚀刻停止层(未示出)。然后可以在另一蚀刻工艺中去除蚀刻停止层的部分以暴露互连结构408的金属线410和通孔411。焊盘开口416的宽度大于通孔开口418的宽度。
在图4D中,在通孔开口418中形成通孔413,在焊盘开口416A中形成内部接合焊盘405,并且在焊盘开口416B中形成外部接合结构420。内部接合焊盘405可以类似于先前描述的内部接合焊盘105。外部接合结构420可以包括外部接合焊盘407和并联连接件421,并且可以类似于先前描述的外部接合结构120。通孔413、内部接合焊盘405或外部接合结构420可以由包括金属或金属合金的导电材料形成,金属或金属合金诸如铜、银、金、钨、钴、铝、它们的合金等。在一些实施例中,通孔413、内部接合焊盘405或外部接合结构420的形成包括在焊盘开口416和通孔开口418中沉积薄晶种层(未示出),薄晶种层可以包括铜或铜合金,并且使用例如ECP或化学镀填充焊盘开口416和通孔开口418的其余部分。可以使用诸如CMP的平坦化工艺从接合层406的顶面去除过量的导电材料和晶种层。在一些情况下,具有与内部接合焊盘405的间距大致相同的间距的外部接合焊盘407可以允许横跨接合层406的更均匀的平坦化。还可以包含沉积方法。内部接合焊盘405或外部接合结构420可以经由通孔413电连接至互连结构408。图4A至图4D中所示的工艺表示可以用于形成外部接合结构420的示例性工艺,并且在其它实施例中,可以使用其它工艺和技术,诸如镶嵌工艺、双镶嵌工艺或其它工艺。在一些实施例中,上面参考图2A至图3E描述的或下面参考图7A至图7H描述的内部接合焊盘或外部接合结构可以使用图4A至图4D所示的工艺形成或使用不同的工艺形成。
转至图5A至图5B,根据一些实施例示出了接合的半导体结构500。在图5A至图5B所示的实施例中,外部接合结构的电连接的外部接合焊盘之间的并联连接件形成在与外部接合焊盘不同的层中。接合的半导体结构500包括接合至晶圆200的半导体器件100。半导体器件100和晶圆200可以类似于上面参考图2A至图2B描述的那些。接合的半导体结构500包括内部区域512和外部区域514,其可以类似于先前描述的内部区域112或外部区域114。在内部区域512中,半导体器件100和晶圆200通过半导体器件100的内部接合焊盘105和晶圆200的内部接合焊盘205电连接。在外部区域514中,半导体器件100和晶圆200通过半导体器件100的外部接合结构120和晶圆200的外部接合结构220电连接。图5A示出了接合的半导体结构500的截面图,并且图5B示出了接合的半导体结构500的一些实施例的平面图。图5A至图5B示出了由于半导体器件100的翘曲(如前所述)而在接合之后具有未对准的半导体器件100和晶圆200。
如图5A至图5B所示,半导体器件100的外部接合结构120包括通过一个或多个并联连接件121连接的两个外部接合焊盘107,并且晶圆200的外部接合结构220包括通过一个或多个并联连接件221连接的两个外部接合焊盘207。如图5A至图5B所示,并联连接件121可以设置在与外部焊盘107不同的层中,并且通过通孔连接至外部焊盘107,并且并联连接件221可以设置在与外部接合焊盘207不同的层中,并且通过通孔连接至外部接合焊盘207。半导体器件100的外部接合结构120的描述也可以应用于晶圆200的外部接合结构220。外部接合焊盘107可以具有与内部接合焊盘105相同的间距,并且外部接合焊盘207可以具有与内部接合焊盘205相同的间距。并联连接件121(或221)的宽度W4可以小于、大致等于或大于外部接合焊盘107的尺寸。例如,图5B示出的并联连接件121的宽度W4小于外部接合焊盘107的直径。在一些实施例中,并联连接件121可以具有介于约500nm和约3500nm之间的宽度W4或介于约7000nm和约12000nm之间的长度L5。图5B示出了具有矩形形状的并联连接件121(和并联连接件221),但是在其它实施例中,并联连接件121(或221)可以沿其长度具有多于一个的宽度W4或者具有不同的形状,诸如弯曲形状、梯形形状、具有一个或多个锥形部分的形状、不规则形状或其它形状。例如,并联连接件121和外部接合焊盘107可以具有类似于先前参考图3B至图3E描述的配置或布置,除了并联连接件121设置在与外部接合焊盘不同的层中。在一些实施例中,接合的半导体器件可以包括在与外部接合焊盘相同的层中具有并联连接件的外部接合结构,以及在与外部接合焊盘不同的层中具有并联连接件的外部接合结构。在一些实施例中,外部接合结构可以在与外部接合焊盘相同的层中设置有一个或多个并联连接件,并且在与外部接合焊盘不同的层中设置有一个或多个并联连接件。
在图5A至图5B所示的实施例中,外部接合焊盘107和并联连接件121设置在接合层106的外部层中。外部接合焊盘107和并联连接件121的顶面基本共面并且包括未由接合层106覆盖的部分。通过这种方式,当半导体器件100接合至晶圆200时,外接合焊盘107和并联连接件121都可以用于外部接合结构120以形成电连接。例如,晶圆200的外部接合结构220可以包括设置在介电层206的外部层中的外部接合焊盘207和并联连接件221,以制成与外部接合结构120的电连接。在一些实施例中,半导体器件100的外部接合结构120接合至晶圆200的相应接合部件(诸如外部接合结构220、接合焊盘或其它类型的部件)以形成电连接。
通过使用并联连接件121电连接多个外部接合焊盘107,可以增加接合的电连接件的接触面积,如果存在未对准,这可以降低接合的电连接件的接触电阻。通过这种方式,如果存在未对准,则可以减小半导体器件的边缘附近由于未对准引起的接合的电连接件的接触电阻。另外,通过使并联连接件121设置在与外部接合焊盘107不同的层中,外部接合焊盘107的间距和分布可以类似于内部接合焊盘105的间距,并且因此半导体器件100的整个接合表面可以具有更均匀的表面特征分布。在一些情况下,通过这种方式,更均匀的表面特征分布可以允许更均匀的平面度,例如,在平坦化工艺之后,这可以允许改进表面之间的接合。因此,本文的实施例可以允许改进接合器件之间的电连接而不会显着降低接合质量。
图6A至图6E示出了根据一些实施例的半导体器件600中的接合结构的形成中的中间阶段的截面图。半导体器件600可以类似于先前描述的半导体器件100或晶圆200。如图6A至图6E所示,半导体器件600可以具有内部区域612和外部区域614,其可以类似于先前描述的内部区域112和外部区域114。半导体器件600包括其上形成有互连结构608的衬底602。衬底602可以类似于先前描述的衬底102。互连结构608可以类似于先前描述的互连结构408。互连结构608可以包括导电部件,诸如金属线610或通孔611。在一些实施例中,互连结构608包括一个或多个并联连接件621。并联连接件621可以类似于先前在图5A至图5B中描述的并联连接件121。在一些情况下,并联连接件621类似于金属线610。
互连结构608的金属线610、通孔611或并联连接件621可以使用与先前参考互连结构408描述的那些类似的技术形成,诸如使用单和/或双镶嵌工艺。在一些情况下,可以使用与金属线610不同的技术形成并联连接件621。在一些实施例中,形成包含厚度在约900nm和约1800nm之间的并联连接件621的层。在一些实施例中,并联连接件621形成在与所示的互连结构608不同的层中,并且一些并联连接件621可以形成在与其它并联连接件621不同的层中。
转至图6B,在互连结构608上方形成接合层606。接合层606可以类似于先前描述的接合层106。在一些实施例中,形成的接合层606具有介于约900nm和约8000nm之间的厚度。转至图6C,在接合层606中形成焊盘开口616。焊盘开口616的示例性焊盘开口616A和616B在图6C中标记并且在下面更详细地描述。焊盘开口616可以使用与先前关于焊盘开口416描述的那些类似的技术形成。如图6C所示,焊盘开口616包括形成在内部区域612中的内部焊盘开口616A和形成在外部区域614中的外部焊盘开口616B。内部焊盘开口616A可以类似于外部焊盘开口616B,并且在一些实施例中可以具有在约2000nm和约3500nm之间的宽度。内部焊盘开口616A对应于将形成内部焊盘的位置,并且外部焊盘开口616B对应于将形成外部焊盘的位置,如下所述。内部焊盘开口616A和外部焊盘开口616B可以均匀地间隔开一段距离,该距离对应于随后形成的内部接合焊盘的间距。
转至图6D,可以在接合层606中形成通孔开口618。通孔开口618形成在焊盘开口616的底部,并且从焊盘开口616的底部延伸至接合层606的底面,从而暴露并联连接件621或一些金属线610。可以使用类似于先前参考通孔开口418描述的技术形成通孔开口618。通孔开口618可以形成在内部焊盘开口616A或外部焊盘开口616B内。作为说明性实例,图6D示出了形成在外部焊盘开口616B中的三个通孔开口618,但是其它数量的通孔开口618可以形成在内部焊盘开口616A或外部焊盘开口616B内。通孔开口618的宽度可以与外部焊盘开口616B的宽度相同或小于外部焊盘开口616B的宽度。
在图6E中,在通孔开口618中形成通孔622,并且在焊盘开口616A中形成内部接合焊盘605,并且在焊盘开口616B中形成外部接合焊盘607。内部接合焊盘605可以类似于先前描述的内部接合焊盘105。外部接合结构620可以包括外部接合焊盘607、通孔622和并联连接件621,并且可以类似于先前描述的外部接合结构120。通孔622、内部接合焊盘605或外部接合焊盘607可以使用与先前参考图4D描述的技术类似的技术形成。通孔622形成外部接合焊盘607和并联连接件621之间,或内部接合焊盘605和互连结构608之间(未示出)的电连接。在一些情况下,具有与内部接合焊盘605的间距大致相同的间距的外部接合焊盘607可以允许横跨接合层606更均匀的平坦化。内部接合焊盘605或外部接合结构620可以通过通孔611电连接至互连结构608。图6A至图6E中所示的工艺表示可用于形成外部接合结构620的示例性工艺,并且可以其它实施例中使用其它工艺和技术,诸如镶嵌工艺、双镶嵌工艺或其它工艺。在一些实施例中,上面参考图2A至图3E描述的或下面参考图7A至图7H描述的内部接合焊盘或外部接合结构可以使用图6A至图6E中所示的工艺形成或者使用不同的工艺形成。
图7A至图7H示出了根据一些实施例的封装器件700的形成中的中间阶段的截面图。在一些实施例中,封装器件700可以是集成扇出(InFO)封装件。在图7A中,将顶部器件702放置在封装组件710上。顶部器件702可以类似于半导体器件100,并且封装组件710可以类似于先前描述的晶圆200,但是在不同的实施例中,顶部器件702或封装组件710可以不同。顶部器件702包括至少部分地形成在接合层703中的内部接合焊盘706和外部接合结构708,并且封装组件710包括至少部分地形成在接合层713中的内部接合焊盘716和外部接合结构718。接合层703或接合层713可以类似于先前描述的接合层106、406或606。内部接合焊盘706或内部接合焊盘716可以类似于先前描述的内部接合焊盘105、405或605。外部接合结构708或外部接合结构718可以类似于先前描述的外部接合结构120、420或620。顶部器件702可以使用拾取和放置工艺或其它工艺放置,并且在一些实施例中可以使用接合头150放置。在图7A中,顶部器件702被示出为安装到接合头150,但是为了清楚起见,未示出顶部器件702的翘曲。可以在放置之前减薄顶部器件702。
在图7B中,使用例如直接接合或混合接合将顶部器件702接合至封装组件710。在实施接合之前,可以对顶部器件702或封装组件710实施表面处理。在一些实施例中,表面处理包括等离子体处理。等离子体处理可以在真空环境(例如,真空室,未示出)中实施。用于产生等离子体的工艺气体可以是含氢气体,其包括含氢气(H2)和氩气(Ar)的第一气体、含H2和氮气(N2)的第二气体或含H2和氦气(He)的第三气体。等离子体处理也可以使用纯的或基本纯的H2、Ar或N2作为工艺气体来实施,其处理内部接合焊盘706和716以及外部接合结构708和718以及接合层703和713的表面。顶部器件702和封装组件710可以用相同的表面处理工艺处理,或者用不同的表面处理工艺处理。在一些实施例中,顶部器件702和/或封装组件710可以在表面处理之后被清洁。清洁可以包括实施化学清洁和去离子水清洁/冲洗。
接下来,可以利用顶部器件702和封装组件710实施预接合工艺。顶部器件702和封装组件710对准,其中,顶部器件702的内部接合焊盘706与封装组件710的内部接合焊盘716对准,并且顶部器件702的外部接合结构708与封装组件710的外部接合结构718对准。在对准之后,顶部器件702和封装组件710彼此压靠。在一些实施例中,压力可小于约5牛顿每管芯,但是也可使用更大或更小的力。预接合工艺可以在室温下实施(例如,在约21℃至约25℃的温度下),但是可以使用更高的温度。例如,预接合时间可以短于约1分钟。
在预接合之后,顶部器件702的接合层703和封装组件710的接合层713彼此接合。顶部器件702和封装组件710的组合在下文中称为接合对750。可以在随后的退火步骤中增强接合对750的接合。例如,接合对750可以在约300℃至约400℃的温度下退火。退火可以实施例如约1小时至约2小时的时间段。在退火期间,接合焊盘706和716以及外部接合结构708和718中的金属可以彼此扩散,从而也形成金属至金属键。因此,顶部器件702和封装组件710之间的产生的接合可以是混合接合。
如图7C所示,然后分割每个接合对750。例如,可以使用一个或多个锯片分割接合对750。然而,也可以使用任何合适的分割方法,包括激光烧蚀或一个或多个湿蚀刻。在一些情况下,可以在分割之前减薄顶部器件702和/或封装组件710。
图7D示出了载体衬底721,其具有粘合剂层723和位于粘合剂层723上方的聚合物层725。在一些实施例中,载体衬底721包括例如诸如玻璃或氧化硅的硅基材料,或诸如氧化铝的其它材料、任何这些材料的组合等。载体衬底721可以是平坦的,以适应诸如接合对750的半导体器件的附接。粘合剂层723放置在载体衬底721上,以有助于上面的结构(例如,聚合物层725)的粘合。在一些实施例中,粘合剂层723可以包括光热转换(LTHC)材料或紫外胶,当暴露于紫外光时其失去其粘合性。然而,也可以使用其它类型的粘合剂,诸如压敏粘合剂、可辐射固化粘合剂、环氧树脂、这些的组合等。粘合剂层723可以以半液体或凝胶形式放置在载体衬底721上,其在压力下易于变形。
聚合物层725放置在粘合剂层723上方并且用于为例如接合对750提供保护。在一些实施例中,聚合物层725可以是聚苯并恶唑(PBO),但是可以可选地利用任何合适的材料,诸如聚酰亚胺或聚酰亚胺衍生物等。聚合物层725可以使用例如旋涂工艺放置至约2μm至约15μm之间(诸如约5μm)的厚度,但是可以可选地使用任何合适的方法和厚度。接合对750附接在聚合物层725上。在一些实施例中,接合对750可以使用例如拾取和放置工艺放置。然而,可以使用任何合适的放置接合对750的方法。
在一些实施例中,在聚合物层725上方形成诸如介电通孔(TDV)727的通孔。在一些实施例中,首先在聚合物层725上方形成晶种层(未示出)。晶种层是导电材料的薄层,其有助于在随后的工艺步骤中形成较厚的层。在一些实施例中,晶种层可以包括约厚的钛层,以及随后的厚的铜层。可以使用诸如溅射、蒸发或PECVD工艺的工艺来产生晶种层,这取决于期望的材料。一旦形成晶种层,则可以在晶种层上方形成并且图案化光刻胶(未示出)。然后在图案化的光刻胶内形成TDV 727。在一些实施例中,TDV 727包括一种或多种导电材料,诸如铜、钨、其它导电金属等,并且可以例如通过电镀、化学镀等形成。在一些实施例中,使用电镀工艺,其中,将晶种层和光刻胶浸没或浸入电镀溶液中。一旦使用光刻胶和晶种层形成TDV 727,则可以使用合适的去除工艺去除光刻胶。在一些实施例中,可以使用等离子体灰化工艺来去除光刻胶,由此可以增加光刻胶的温度直至光刻胶经历热分解并且可以被去除。然而,可以可选地使用任何其它合适的工艺,诸如湿剥离。光刻胶的去除可以暴露下面的晶种层的部分。一旦形成TDV 727,则然后例如使用湿或干蚀刻工艺去除晶种层的暴露部分。TDV 727可以形成为介于约180μm和约200μm之间的高度,其临界尺寸为约190μm,并且间距为约300μm。
图7E示出了利用密封剂729密封接合对750和TDV 727。密封剂729可以是模塑料,诸如树脂、聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、这些的组合等。图7F示出了密封剂729的减薄,以暴露TDV 727和接合对750。可以例如使用CMP工艺或其它工艺来实施减薄。
图7G示出了密封剂729上方的具有一层或多层的再分布结构1000的形成。在一些实施例中,可以通过在密封剂729上方初始形成第一再分布钝化层1001来形成再分布结构1000。在一些实施例中,第一再分布钝化层1001可以是聚苯并恶唑(PBO),但是也可以使用任何合适的材料,诸如聚酰亚胺或聚酰亚胺衍生物,诸如低温固化的聚酰亚胺。可以使用例如旋涂工艺将第一再分布钝化层1001放置到约5μm和约17μm之间(诸如约7μm)的厚度,但是可以可选地使用任何合适的方法和厚度。
一旦形成第一再分布钝化层1001,则可以穿过第一再分布钝化层1001形成第一再分布通孔1003,以制成至接合对750和TDV 727的电连接。在一些实施例中,可以通过使用镶嵌工艺、双镶嵌工艺或其它工艺来形成第一再分布通孔1003。在形成第一再分布通孔1003之后,在第一再分布通孔1003上方形成与第一再分布通孔1003电连接的第一再分布层1005。在一些实施例中,可以通过诸如CVD或溅射的合适的形成工艺初始形成钛铜合金的晶种层(未示出)来形成第一再分布层1005。然后可以形成光刻胶(也未示出)以覆盖晶种层,并且然后可以图案化光刻胶以暴露晶种层的位于第一再分布层1005期望所在的位置的那些部分。
一旦形成并且图案化光刻胶,则可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。导电材料可以形成为具有介于约1μm和约10μm之间(诸如约4μm)的厚度。然而,虽然所讨论的材料和方法适合于形成导电材料,但这些材料仅仅是示例性的。诸如AlCu或Au的任何其它合适的材料,以及诸如CVD或PVD的任何其它合适的形成工艺可以可选地用于形成第一再分布层1005。
在形成第一再分布层1005之后,可以形成并且图案化第二再分布钝化层1007,以帮助隔离第一再分布层1005。在一些实施例中,第二再分布钝化层1007可以类似于第一再分布钝化层1001,诸如通过为正性PBO,或者可以与第一再分布钝化层1001不同,诸如通过为负性材料,诸如低温固化的聚酰亚胺。第二再分布钝化层1007可以放置为约7μm的厚度。一旦放置,则可以图案化第二再分布钝化层1007以使用例如光刻掩模和蚀刻工艺形成开口,或者如果第二再分布钝化层1007的材料是光敏的,则暴露和显影第二再分布钝化层1007的材料。然而,可以使用任何合适的图案化的材料和方法。
在图案化第二再分布钝化层1007之后,可以形成第二再分布层1009以延伸穿过形成在第二再分布钝化层1007内的开口并且制成与第一再分布层1005的电连接。在一些实施例中,可以使用与第一再分布层1005类似的材料和工艺来形成第二再分布层1009。例如,可以通过图案化的光刻胶施加和覆盖晶种层,可以将诸如铜的导电材料施加到晶种层上,可以去除图案化的光刻胶,并且可以使用导电材料作为掩模来蚀刻晶种层。在一些实施例中,第二再分布层1009形成为约4μm的厚度。然而,可以使用任何合适的材料或制造工艺。
在形成第二再分布层1009之后,在第二再分布层1009上方施加第三再分布钝化层1011,以帮助隔离和保护第二再分布层1009。在一些实施例中,第三再分布钝化层1011可以由与第二再分布钝化层1007类似的材料和类似的方式形成至约7μm的厚度。例如,第三再分布钝化层1011可以由PBO或低温固化的聚酰亚胺形成,其已经如上关于第二再分布钝化层1007所述施加和图案化。然而,可以使用任何合适的材料或制造工艺。
在图案化第三再分布钝化层1011之后,可以形成第三再分布层1013以延伸穿过形成在第三再分布钝化层1011内的开口并且制成与第二再分布层1009的电连接。在一些实施例中,可以使用与第一再分布层1005类似的材料和工艺来形成第三再分布层1013。例如,可以通过图案化的光刻胶施加和覆盖晶种层,可以将诸如铜的导电材料施加到晶种层上,可以去除图案化的光刻胶,并且可以使用导电材料作为掩模来蚀刻晶种层。在一些实施例中,第三再分布层1013形成为约5μm的厚度。然而,可以使用任何合适的材料或制造工艺。
在形成第三再分布层1013之后,在第三再分布层1013上方形成第四再分布钝化层1015,以帮助隔离和保护第三再分布层1013。在一些实施例中,第四再分布钝化层1015可以由与第二再分布钝化层1007类似的材料和类似的方式形成。例如,第四再分布钝化层1015可以由PBO或低温固化的聚酰亚胺形成,其已经如上参考第二再分布钝化层1007描述的施加和图案化。在一些实施例中,第四再分布钝化层1015形成为约8μm的厚度。然而,可以使用任何合适的材料或制造工艺。
在其它实施例中,再分布结构1000的再分布通孔和再分布层可以使用诸如双镶嵌工艺的镶嵌工艺形成。例如,可以在密封剂729上方形成第一再分布钝化层。然后使用一个或多个光刻步骤图案化第一再分布钝化层,以在第一再分布钝化层内形成用于通孔的开口和用于导线的开口。可以在用于通孔的开口和用于导线的开口中形成导电材料,以形成第一再分布通孔和第一再分布层。可以在第一再分布钝化层上方形成附加的再分布钝化层,并且可以在附加的再分布钝化层中形成另外的再分布通孔和导线的组,如针对第一再分布钝化层所描述的,从而形成再分布结构1000。这个或其它技术可以用于形成再分布结构1000。
图7G另外示出了凸块下金属1019和第三外部连接件1017的形成以制成与第三再分布层1013的电连接。在一些实施例中,凸块下金属1019的每个均可以包括三层导电材料,诸如钛层、铜层和镍层。然而,本领域普通技术人员将认识到,存在适合于形成凸块下金属1019的许多合适的材料和层布置,诸如铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于凸块下金属1019的任何合适的材料或材料层均完全旨在包括在实施例的范围内。
在一些实施例中,通过在第三再分布层1013上方并且沿着穿过第四再分布钝化层1015的开口的内部形成每个层来产生凸块下金属1019。可以使用诸如电化学镀的镀工艺来实施每个层的形成,但是可以使用其它形成工艺,诸如溅射、蒸发或PECVD工艺,这取决于所需的材料。凸块下金属1019可以形成为具有介于约0.7μm和约10μm之间(诸如约5μm)的厚度。
在一些实施例中,第三外部连接件1017可以放置在凸块下金属1019上,并且可以是包括诸如焊料的共晶材料的球栅阵列(BGA),但是可以可选地使用任何合适的材料。在第三外部连接件1017是焊球的一些实施例中,第三外部连接件1017可以使用诸如直接落球工艺的落球方法形成。在另一实施例中,焊球可以通过首先通过诸如蒸发、电镀、印刷、焊料转移的任何合适的方法形成锡层来形成,并且然后实施回流,以将材料成形为期望的凸块形状。一旦形成了第三外部连接件1017,则可以实施测试以确保该结构适合于用于进一步处理。
然后图案化聚合物层725以暴露TDV 727。在一些实施例中,可以使用例如激光钻孔方法图案化聚合物层725。在这种方法中,首先在聚合物层725上方沉积保护层,诸如光热转换(LTHC)层或水溶性保护膜(hogomax)层(图7G中未单独示出)。一旦受到保护,则将激光导向聚合物层725的需要被去除的那些部分以暴露下面的TDV 727。在激光钻孔工艺期间,钻孔能量可以在从0.1mJ至约30mJ的范围内,并且钻孔角度相对于聚合物层725的法线为约0度(垂直于聚合物层725)至约85度。在一些实施例中,图案化可以形成为在TDV 727上方形成具有介于约100μm和约300μm之间(诸如约200μm)的宽度的开口。
在另一实施例中,可以通过首先将光刻胶(图7G中未单独示出)施加到聚合物层725,并且然后将光刻胶暴露于图案化的能量源(例如,图案化的光源)以引起化学反应,从而引起光刻胶的暴露于图案化光源的那些部分的物理变化来图案化聚合物层725。然后将显影剂施加到曝光的光刻胶以利用物理变化并且根据期望的图案选择性地去除光刻胶的曝光部分或光刻胶的未曝光部分,并且利用例如,干蚀刻工艺去除下面的聚合物层725的曝光部分。然而,可以使用用于图案化聚合物层725的任何其它合适的方法。
图7H示出了封装件1100通过聚合物层725与TDV 727的接合。在接合封装件1100之前,从聚合物层725去除载体衬底721和粘合剂层723。也图案化聚合物层725以暴露TDV727。在一些实施例中,封装件1100可以包括附加衬底、附加半导体器件、内部连接件、中介层等。附加半导体器件可以包括设计用于预期目的的一个或多个半导体器件,预期目的诸如存储器管芯(例如,DRAM管芯)、逻辑管芯、中央处理单元(CPU)管芯、这些的组合等。在一些实施例中,根据特定功能的需要,一个或多个附加半导体器件包括集成电路器件,诸如晶体管、电容器、电感器、电阻器、第一金属层(未示出)等。在一些实施例中,一个或多个附加半导体器件被设计和制造成与接合对750结合或同时工作。密封剂1103可以用于密封和保护封装件1100。
在一些实施例中,外部连接件1101可以形成为在封装件1100和例如TDV 727之间提供外部连接。外部连接件1101可以是诸如微凸块或可控塌陷芯片连接(C4)凸块的接触凸块,并且可以包括诸如锡的材料或诸如银或铜的其它合适的材料。在外部连接件1101是锡焊料凸块的一些实施例中,外部连接件1101可以通过首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等的任何合适的方法形成厚度为例如约100μm的锡层来形成。一旦在结构上形成锡层,则实施回流以将材料成形为期望的凸块形状。
一旦形成外部连接件1101,则将外部连接1101与TDV 727对准并且放置在TDV 727上方,并且实施接合。例如,在外部连接1101是焊料凸块的一些实施例中,接合工艺可以包括回流工艺,由此第四外部连接件1101的温度升高至外部连接件1101将液化和流动的点,从而使得一旦外部连接件1101重新固化,就将封装件1100接合至TDV 727。
实施例可以实现许多优势。在一些实施例中,器件边缘附近的接合焊盘并联连接。通过对单个电连接件使用多个连接的接合焊盘,电连接件的可用接合面积增加。增加的接合面积可以降低接合工艺期间由于接合焊盘的未对准或器件的翘曲而引起的接触电阻。此外,连接的接合焊盘可以形成为具有与其它未连接的接合焊盘相同的间距,其它未连接的接合焊盘诸如器件中心附近的那些。通过使形成在器件上的接合焊盘保持恒定的间距,可以实现更大的工艺均匀性。例如,在平坦化工艺之后,更均匀的接合焊盘间距可以产生更平坦的表面。在一些实施例中,连接的接合焊盘可用于接合器件之间的电源或接地电连接。
在实施例中,半导体器件包括位于第一衬底上方的第一互连结构、位于第一互连结构上方的第一接合层、设置在第一接合层的第一区域中的多个第一接合焊盘,第一接合焊盘具有第一间距以及设置在第一接合层的第二区域中的多个第二接合焊盘,第二区域在第一接合层的第一边缘和第一区域之间延伸,第二接合焊盘具有第一间距,多个第二接合焊盘包括多对相邻的第二接合焊盘,其中,每个相应对的第二接合焊盘通过第一金属线连接。在实施例中,第一金属线设置在与第二焊盘相同的层中。在实施例中,第一金属线设置在互连结构中,并且经由设置在接合层中的通孔连接至每个相应对的第二接合焊盘。在实施例中,半导体器件包括位于第二衬底上方的第二接合层和设置在第二接合层中的多个第三接合焊盘,包括多对相邻的第三接合焊盘,其中,每个相应对的第三接合焊盘通过第二金属线连接,并且其中,第三接合焊盘接合至第二接合焊盘。在实施例中,第三接合焊盘的间距小于第二接合焊盘的间距。在实施例中,第二区域在第一接合层的第二边缘和第一区域之间延伸。在实施例中,邻近第一边缘的成对的相邻第二接合焊盘的取向垂直于邻近第二边缘的成对的相邻第二接合焊盘。在实施例中,第二区域从接合层的第一边缘延伸一段距离,该距离是从接合层的第一边缘至接合层的相对边缘的距离的约10%。在实施例中,第二区域从接合层的第一边缘延伸第一距离并且从接合层的第二边缘延伸第二距离,第一距离与第二距离不同。
在实施例中,方法包括在半导体衬底上方沉积介电层,在介电层中蚀刻多个接合焊盘开口,接合焊盘开口具有第一间距,在介电层中蚀刻多个第二开口,第二开口在多个接合焊盘开口的相应的第一接合焊盘开口和第二接合焊盘开口之间延伸,其中,第一接合焊盘开口与半导体衬底的一个或多个侧壁相邻,在多个接合焊盘开口内并且在多个第二开口内沉积导电材料,并且使用平坦化工艺去除过量的导电材料。在实施例中,接合焊盘开口具有第一直径,并且其中,第二开口具有约等于第一直径的宽度。在实施例中,该方法包括在介电层中蚀刻多个第三开口,第三开口从接合焊盘开口的底面延伸至介电层的底面,并且还包括在第三开口内沉积导电材料。在实施例中,该方法还包括在半导体衬底上方形成多个层间介电(ILD)层,其中,介电层形成在多个ILD层上方。在实施例中,该方法还包括将介电层接合至包括接合焊盘的器件衬底,并且将导电材料接合至器件衬底的接合焊盘。在实施例中,第一接合焊盘和第二接合焊盘之间的第二开口的取向取决于第一接合焊盘的位置。
在实施例中,方法包括形成第一半导体器件,该第一半导体器件包括在第一衬底上形成互连结构,在互连结构上形成第一接合层,以及在第一接合层中形成第一接合焊盘,其中,第一多个第一接合层接合焊盘包括由多条第一导线并联连接的多组相邻的第一接合焊盘,形成第二半导体器件,形成第二半导体器件包括在第二衬底上形成第二接合层,以及在第二接合层中形成第二接合焊盘,其中,第一多个第二接合焊盘包括由多条第二导线并联连接的多组相邻的第二接合焊盘,以及将第一接合层接合至第二接合层,将第一接合层接合至第二接合层包括将第一多个第一接合焊盘接合至第一多个第二接合焊盘。在实施例中,该方法包括在互连结构内形成多条第一导线。在实施例中,该方法还包括在第一接合层内形成多条第一导线。在实施例中,第一接合焊盘具有与第二接合焊盘不同的间距。在实施例中,第一多个第一接合焊盘邻近第一接合层的边缘设置。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种半导体器件,包括:
第一互连结构,位于第一衬底上方;
第一接合层,位于所述第一互连结构上方;
多个第一接合焊盘,设置在所述第一接合层的第一区域中,所述第一接合焊盘具有第一间距;以及
多个第二接合焊盘,设置在所述第一接合层的第二区域中,所述第二区域在所述第一接合层的第一边缘和所述第一区域之间延伸,所述第二接合焊盘具有所述第一间距,所述多个第二接合焊盘包括多对相邻的第二接合焊盘,其中,每个相应对的第二接合焊盘通过第一金属线连接。
2.根据权利要求1所述的半导体器件,其中,所述第一金属线设置在与所述第二焊盘相同的层中。
3.根据权利要求1所述的半导体器件,其中,所述第一金属线设置在所述互连结构中,并且经由设置在所述接合层中的通孔连接至所述每个相应对的第二接合焊盘。
4.根据权利要求1所述的半导体器件,包括:
第二接合层,位于所述第二衬底上方;以及
多个第三接合焊盘,设置在所述第二接合层中,所述多个第三接合焊盘包括多对相邻的第三接合焊盘,其中,每个相应对的第三接合焊盘通过第二金属线连接,并且其中,所述第三接合焊盘接合至所述第二接合焊盘。
5.根据权利要求4所述的半导体器件,其中,所述第三接合焊盘的间距小于所述第二接合焊盘的间距。
6.根据权利要求1所述的半导体器件,其中,所述第二区域在所述第一接合层的第二边缘和所述第一区域之间延伸。
7.根据权利要求6所述的半导体器件,其中,邻近所述第一边缘的成对的相邻第二接合焊盘的取向垂直于邻近所述第二边缘的成对的相邻第二接合焊盘。
8.根据权利要求1所述的半导体器件,其中,所述第二区域从所述接合层的第一边缘延伸一段距离,所述一段距离是从所述接合层的第一边缘至所述接合层的相对边缘的距离的10%。
9.一种形成半导体器件的方法,包括:
在半导体衬底上方沉积介电层;
在所述介电层中蚀刻第一接合焊盘开口和第二接合焊盘开口,其中,所述第一接合焊盘开口与所述半导体衬底的一个或多个侧壁相邻,其中,每个第二接合焊盘开口与至少一个第一接合焊盘开口相邻;
在所述介电层中蚀刻沟槽,每个沟槽均在所述至少一个第一接合焊盘开口和至少一个第二接合焊盘开口之间延伸;
在所述第一接合焊盘开口内沉积导电材料以形成第一接合焊盘,在所述第二接合焊盘开口内沉积导电材料,以形成第二接合焊盘,并且在所述沟槽内形成导电材料以形成所述第一接合焊盘和所述第二接合焊盘之间的电连接;以及
使用平坦化工艺去除过量的导电材料。
10.一种形成半导体器件的方法,包括:
形成第一半导体器件,包括:
在第一衬底上形成互连结构;
在所述互连结构上形成第一接合层;以及
在所述第一接合层中形成第一接合焊盘,其中,所述第一多个第一接合焊盘包括由多条第一导线并联连接的多组相邻的第一接合焊盘;
形成第二半导体器件,包括:
在第二衬底上形成第二接合层;以及
在所述第二接合层中形成第二接合焊盘,其中,所述第一多个第二接合焊盘包括由多条第二导线并联连接的多组相邻的第二接合焊盘;以及
将所述第一接合层接合至所述第二接合层,将所述第一接合层接合至所述第二接合层包括将所述第一多个第一接合焊盘接合至所述第一多个第二接合焊盘。
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