CN210272373U

CN210272373U - High electron mobility transistor with high voltage endurance capability

Info

Publication number: CN210272373U
Application number: CN201921452016.0U
Authority: CN
Inventors: 黎子兰
Original assignee: Guangdong Zhineng Technology Co Ltd
Current assignee: Guangdong Zhineng Technology Co Ltd
Priority date: 2019-08-30
Filing date: 2019-08-30
Publication date: 2020-04-07
Anticipated expiration: 2029-08-30

Abstract

The present invention relates to a semiconductor power device, and more particularly, to a high electron mobility transistor having a high withstand voltage capability. A high electron mobility transistor with high withstand voltage capability, which includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer, and a substrate; the P-type nitride semiconductor layer is located between the barrier layer and the substrate, which is insufficient to substantially deplete the two-dimensional electron gas in the channel except for the gate stack, and the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas.

Description

High electron mobility transistor with high voltage endurance capability

Technical Field

The present invention relates to a semiconductor power device, and particularly, to a high withstand voltage High Electron Mobility Transistor (HEMT).

Background

Group III nitride semiconductors are an important new semiconductor material, mainly including AlN, GaN, InN, and compounds of these materials such as AlGaN, InGaN, AlInGaN, and the like. Because of the advantages of direct band gap, wide forbidden band, high breakdown electric field intensity and the like, the III group nitride semiconductor represented by GaN has wide application prospect in the fields of light-emitting devices, power electronics, radio frequency devices and the like.

One important device type of group III nitride semiconductor is the High Electron Mobility Transistor (HEMT), which has great promise in the power semiconductor field. Due to the existence of spontaneous polarization and piezoelectric polarization effect, the interface of GaN and AlGaN on the (0001) plane has strong polarization positive charge. The presence of these polarized positive charges attracts and results in the generation of a two-dimensional electron gas at the interface. These two-dimensional electron gases have high carrier concentration and high carrier mobility, and are core components for manufacturing High Electron Mobility Transistors (HEMTs).

Fig. 1 is a conventional HEMT structure. The two-dimensional electron gas conducts current between the source and the drain. The gate electrode controls the switching of the device. It is noted that the source, drain and gate electrodes are all located on the same side of the device in this configuration. When the device is in the off state, both the source and gate are at low voltage (typically within ± 20V), but the drain electrode may be at a voltage of tens to hundreds or even kilovolts. Such high voltages are applied to the device, resulting in a high electric field inside the device. On the other hand, the electric field distribution within these devices is not uniform, and the local electric field strength can far exceed the average electric field strength. These localized high electric field strengths may approach or even exceed the breakdown field strengths of the materials used in the device, leading to device breakdown, leakage or reliability problems. Therefore, it is very critical to prevent the occurrence of high-intensity local electric field or to reduce the intensity of local electric field to improve the overall performance and reliability of the device.

The gate electrode edge (shown) is often very high in electric field strength, which is in the vicinity of the gate stack of the weakest and most core device, and this tends to cause gate leakage, gate breakdown and low reliability at high electric field, which is of particular concern. One common way to reduce the local electric field is to use a field plate (field plate) structure. These field plate structures change the distribution of the electric field and can reduce the local over-high electric field. However, the field plate structure usually uses a metal material, and still has the problem of point discharge, and the spike of the electric field still exists in a local part.

In addition, a high-density two-dimensional electron gas conduction channel is formed when the material preparation of the Al Ga N/Ga N heterojunction is completed, so that the conventional Al Ga N/Ga N HEMT device is a depletion type (threshold voltage Vth is less than 0), can be in an off state only by applying negative bias to a grid, and is a normally-on (normal on) device. However, in the field of power switching devices, normally off (normal off) devices are highly desirable. GaN enhanced device technology has attracted great attention by researchers. Through years of development, the method for realizing the enhanced device mainly comprises the technologies of a thin barrier layer, a groove gate, fluorine ion implantation under the gate and the like. The utility model discloses the application can also be through the local or whole two-dimensional electron gas that exhausts grid stack department of P-GaN layer doping modulation technique and realize enhancement type device when promoting the pressure resistance of device.

SUMMERY OF THE UTILITY MODEL

The basic principle of the utility model is that through introducing P-type nitride semiconductor layer, adjust electric field distribution and improve HEMT's device withstand voltage ability and realize the enhancement type device through doping modulation technique.

The P-type nitride semiconductor layer is positioned below the two-dimensional electron gas and far away from electrodes such as a grid and a drain. If the barrier layer of the two-dimensional electron gas is vertical with respect to the substrate, the P-type nitride semiconductor layer may be located on the side of the barrier layer.

When the device is in the off state, the two-dimensional electron gas is depleted, leaving a positive charge at the base of the channel. Holes in the P-type nitride semiconductor layer move under the action of a positive electric field of the drain electrode, negative charges of the substrate are left in partial areas, the negative charges effectively counteract the influence of positive charges at the channel, the strength of a local high electric field is reduced, the electric field distribution is improved, and the performance and the reliability of the device are improved.

In one aspect, the present invention provides a HEMT having a high withstand voltage capability, comprising a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer, a nucleation layer (a part of devices of a substrate material may not be included), and a substrate device structure; the doping concentration spatial distribution of the P-nitride semiconductor layer is adjusted when the P-type nitride semiconductor layer is epitaxially grown, the P-type nitride semiconductor layer is insufficient to significantly deplete the two-dimensional electron gas in the channel except for the gate stack, the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the drain electrode is in electrical contact with the two-dimensional electron gas. The P-type nitride semiconductor layer is at least partially located in a region between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and under 0 bias, except for the gate stack region, the two-dimensional electron gas concentration of the channel depleted by the P-type nitride semiconductor layer is less than 80% of the two-dimensional electron gas concentration of the channel without P-type doping in the P-type nitride semiconductor layer, that is, at least 20% of the two-dimensional electron gas is retained.

Further, the present invention can also insert a low doped or non-intentionally doped nitride semiconductor layer between the barrier layer and the P-type nitride semiconductor layer of the HEMT, so as to reduce the effect of electron mobility degradation and the like at the two-dimensional electron gas channel due to scattering of the doped atoms.

Further, the utility model discloses well connected mode of electrode can be for among the HEMT: the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas, and the separate body electrode is in electrical contact with the P-type nitride semiconductor layer. The utility model discloses the independent control mode who does benefit to source electrode potential and P-type nitride semiconductor layer's working potential independent control, especially source electrode potential fix when 0 potential point, can come independent control according to the required operating voltage of shutoff channel or stable operating voltage, this is also the utility model discloses the independent control mode that provides for the first time is favorable to the stability of enhancement device, high-efficient work.

Further, the part of the body electrode of the HEMT in the utility model, which is in contact with the P-type nitride semiconductor layer, is a high doping concentration area, which is beneficial to ohmic contact.

Furthermore, the utility model discloses in set up one deck insulating layer on HEMT's the substrate, the insulating layer opening part forms the nucleation layer, then through the mode growth of selecting district/side direction epitaxy contain the epitaxial layer structure including P-type nitride semiconductor layer; or growing a nucleation layer on the substrate, forming an insulating layer on the nucleation layer, exposing the nucleation layer through the opening of the insulating layer, and growing an epitaxial layer structure containing the P-type nitride semiconductor layer in a selective area/lateral epitaxial mode.

Under certain substrate (e.g., Al2O3 substrate) and process conditions, the nucleation layer may be selectively grown on the exposed substrate without growing on the insulating layer. However, when a silicon substrate is used, AlN is generally required as a nucleation layer and the selectivity of AlN is poor. At this time, AlN on the insulating layer may be etched/removed after the growth of the nucleus layer is completed. On the other hand, since AlN grown on the insulating layer is polycrystalline or amorphous, under appropriate growth conditions, the subsequent nitride semiconductor layer of GaN or the like cannot be grown on such polycrystalline AlN but only on the single-crystal AlN nucleation layer at the opening of the substrate. In this case, it is not necessary to remove AlN on the insulating layer and continue selective/lateral epitaxial growth of the subsequent nitride semiconductor layer structure. Under certain growth conditions, such as with chlorine-based gases, little or no AlN deposition on the insulating layer may result, failing to form a nucleation growth mechanism for subsequent nitride epitaxial layers on the insulating layer. I.e. no significant subsequent nitride growth is observed in other areas than in the nucleation zone. In this case, the subsequent growth may be performed without removing AlN on the insulating layer. The nucleation layer may also be produced first and then covered with the insulating layer and exposed.

Further, the utility model discloses well HEMT is when growing P-type nitride semiconductor layer, and P-type nitride semiconductor layer doping concentration controllable change when election district/lateral epitaxy grows, and P-type nitride semiconductor layer light doping or not doping when election district/lateral epitaxy grows the part that is close to predetermineeing the drain electrode, after election district/lateral epitaxy grows, gets rid of partial upper surface nitride semiconductor layer through planarization or etching process, epitaxial formation barrier layer structure or channel layer and barrier layer structure again.

Further, the utility model discloses well HEMT regrows the low doping of one deck or undoped semiconductor layer after growing P-type nitride semiconductor layer, realizes that the channel layer of P-type nitride semiconductor layer upper surface is undoped to avoid producing adverse effect to the energy band of channel layer, device work.

Further, in the present invention, before the growth of the P-type nitride semiconductor layer, the HEMT forms a buffer layer above the nucleation layer, and the buffer layer may be a layer made of a highly doped P-type nitride semiconductor material; after the P-type nitride semiconductor layer is grown, a highly doped P-type nitride semiconductor layer region is formed over the nucleation layer to facilitate ohmic contact with the associated electrode.

Further, the HEMT of the present invention can form a P-type nitride semiconductor layer by adjusting the doping concentration, wherein the first region of the P-type nitride semiconductor layer, the first region of the strong P-type nitride semiconductor layer, and the second region of the P-type nitride semiconductor layer are formed in sequence, and the first region of the strong P-type nitride semiconductor layer is located below the gate electrode, and can deplete the two-dimensional electron gas in at least a partial region of the channel layer below the gate electrode by 95% or more under 0 bias.

Further, the HEMT of the present invention may be configured such that, when forming the P-type nitride semiconductor layer, the first region of the strong P-type nitride semiconductor layer, and the second region of the P-type nitride semiconductor layer are sequentially formed, wherein the first region of the strong P-type nitride semiconductor layer is located between the source electrode and the gate electrode, and the two-dimensional electron gas in the channel layer below the gate electrode is depleted by 80% or more under a bias of 0.

Further, the utility model provides a HEMT, can be through doping concentration's adjustment, when forming P-type nitride semiconductor layer, form strong P-type nitride semiconductor layer first region in proper order, P-type nitride semiconductor layer first region, strong P-type nitride semiconductor layer second region, wherein strong P-type nitride semiconductor layer first region is located the source electrode below, strong P-type nitride semiconductor layer second region is located the gate below and can be under 0 bias with two-dimensional electron gas depletion more than 95% in the channel layer of gate electrode below.

Further, the HEMT of the present invention adopts a precursor mixed atmosphere containing hydrogen and/or chlorine when the P-type nitride semiconductor layer is epitaxially grown in the selective/lateral direction, and controls the concentration distribution of the P-type nitride semiconductor layer grown by controlling the amount of the P-type dopant at different stages of the epitaxial growth, so as to facilitate the adjustment of the electric field distribution.

Further, in the HEMT of the present invention, after the barrier layer is formed, a gate insulating layer may be added under the gate electrode to reduce the off-state leakage current of the gate.

Further, the utility model discloses well HEMT is after forming the barrier layer, and normal position growth SiNx passivation layer, that is to say do not take out the epitaxial wafer after the deposit barrier layer directly in same equipment normal position SiNx passivation layer that redeposits again, this SiNx passivation layer can protect the barrier layer surface effectively and have very high quality, and the barrier layer/SiNx interface defect state that obtains like this is less. The in-situ SiNx layer can passivate the surface of the barrier layer and can also be used as a gate dielectric layer at a gate stack, so that the in-situ grown SiNx layer has double functions of a gate lower dielectric layer and a surface passivation layer.

The P-type nitride semiconductor layer of the utility model is formed by selective area/lateral epitaxy, the P-type doping concentration can be adjusted according to the requirement to the doped carrier gas atmosphere proportion in the growth process, and the electric field distribution is adjusted by the P-type doping, so that the high-quality P-type doping and the space adjustment of the two-dimensional electron gas can be obtained; non-uniform distribution of P-type impurities (typically required to have a doping concentration of 2x 10) by local ion implantation is avoided¹⁸cm^-3Above, the effective concentration after annealing activation is 2x10¹⁷cm^-3The channel can be effectively shut off, a large number of inactivated doping atoms become electron scattering centers, channel current is reduced, transconductance is influenced), and a significant carrier scattering effect brought by the electron scattering centers, and carrier scattering and a certain leakage channel are generated due to irrecoverability of partial high-temperature annealing of ion injection damage. It is very beneficial to achieve high quality P-type doping and control of hole distribution. Based on other patent applications, the utility model combines the lateral/selective area epitaxy technique and the P-type doping electric field distribution adjusting technique, so that high-quality P-type doping and space adjustment thereof can be obtained, the voltage endurance capability of HEMT is improved,and enhancement devices can be realized by doping modulation. The problems that the source electrode and the drain electrode of the conventional HEMT are only in electric contact with two-dimensional electron gas, the potential of the P-type nitride semiconductor layer cannot be controlled and modulated, and the operation of the electron gas in each doped region cannot be differentially controlled, so that the voltage resistance of the device performance is weak are solved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is appreciated that the following drawings depict only certain embodiments of the invention and are therefore not to be considered limiting of its scope. For a person skilled in the art, it is possible to derive other relevant figures from these figures without inventive effort.

Fig. 1 is a typical HEMT structure provided in the background art;

fig. 2-5 illustrate HEMT structures provided in embodiments of the present invention;

fig. 6-10 are schematic diagrams illustrating a process of forming a HEMT structure according to an embodiment of the present invention;

fig. 11-14 are HEMT structures according to embodiments of the present invention.

Detailed Description

The technical solution in the embodiment of the present invention will be described below with reference to the accompanying drawings in the embodiment of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance. "Upper and lower" and the like indicate relative positional relationships and do not indicate that they are directly adjacent to each other.

In the HEMT of the present invention, the doping concentration of the strong doping generally means a doping concentration of 2E18/cm3 or more, and may even be as high as 5E19/cm3 or more. The doping concentration of the light doping is generally below 2E18/cm3, and is generally in the order of 2E17/cm 3. In HEMTs, strong doping or light doping is opposed, depending on the two-dimensional electron gas concentration at the channel layer/barrier layer interface.

Referring to fig. 2, fig. 2 is a schematic diagram of a HEMT according to an embodiment of the present invention. The structure is that a nucleation layer 202 is formed on a substrate 201 (part of devices made of specific substrate materials can not contain the nucleation layer), a P-type nitride semiconductor layer 203 is formed on the nucleation layer 202 in an epitaxial mode, a barrier layer 204 is formed on the P-type nitride semiconductor layer 203, the P-type nitride semiconductor layer 203 is in contact with the barrier layer 204 and forms a heterojunction structure, two-dimensional electron gas is formed at an interface, a source electrode 205 is electrically connected with the two-dimensional electron gas and the P-type nitride semiconductor layer 203, normally, the potential of the source electrode 205 is fixed, a drain electrode 206 is in contact with the two-dimensional electron gas, and a gate electrode 207 is positioned above the barrier layer. The P-type nitride semiconductor layer 203 is a weak P-type, and the hole concentration or P-type impurity concentration thereof is low, so that the two-dimensional electron gas at the interface between the barrier layer 204 and the P-type nitride semiconductor layer 203 is not seriously exhausted, that is, the two-dimensional electron gas with high concentration exists at the interface between the P-type nitride semiconductor layer 203 and the barrier layer; when turned on, the HEMT is realized by controlling different voltages of the gate and the drain. By selecting a suitable gate electrode material, it is also possible to deplete part or all of the two-dimensional electron gas at the gate stack to achieve a normally-off device, while maintaining a high concentration of the two-dimensional electron gas in other regions to achieve good turn-on characteristics. The P-type nitride semiconductor layer is at least partially located in regions between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and except for the gate stack region, the two-dimensional electron gas concentration of the channel depleted by the P-type nitride semiconductor layer is less than 80% of the two-dimensional electron gas concentration of the channel without the P-type nitride semiconductor layer, that is, at least 20% of the two-dimensional electron gas is retained.

Wherein the essential requirement of the source electrode is to form ohmic contact with the two-dimensional electron gas and the P-type nitride semiconductor layer 203. The source electrode portion in contact with the two-dimensional electron gas and the source electrode portion in contact with the P-type nitride semiconductor layer 203 at this time may be the same material or different materials. The drain electrode is usually at a higher voltage, and if the drain electrode is in contact with the P-type nitride semiconductor layer, a larger leakage current is caused during operation, so that the device is unstable and even fails. Therefore, in the device structure of the present invention, the drain electrode is prevented from being electrically connected to the P-type nitride semiconductor layer, and the drain electrode is inserted only into the barrier layer to be electrically connected to the two-dimensional electron gas.

Gate electrode 207 is a schottky contact to reduce off-state leakage current.

Fig. 3 is another example of the high voltage HEMT according to the embodiment of the present invention. The structure is that a nucleating layer 302 is formed on a substrate 301, a P-type nitride semiconductor layer 303 is formed on the nucleating layer 302 in an epitaxial mode, a low-doped or non-intentionally-doped nitride semiconductor layer 304 is formed on the P-type nitride semiconductor layer 303, a barrier layer 305 is formed on the low-doped or non-intentionally-doped nitride semiconductor layer 304, the low-doped or non-intentionally-doped nitride semiconductor layer 304 and the barrier layer 305 form a heterojunction structure, two-dimensional electron gas is formed at an interface, a source electrode 306 is electrically connected with the two-dimensional electron gas and the P-type nitride semiconductor layer 303, the potential of the source electrode 306 is usually fixed, a drain electrode 307 is in contact with the two-dimensional electron gas, and a gate electrode.

Since the doping in P-type nitride semiconductor layer 303 brings about a significant carrier scattering effect, when an unintentionally doped or low-doped channel layer 304 is formed between barrier layer 305 and P-type nitride semiconductor layer 304, scattering received by a two-dimensional electron gas while flowing in the channel layer 304 can be greatly reduced.

The source electrode is connected with the P-type nitride semiconductor layer, the potential of the source electrode is usually fixed, the drain electrode is in contact with the two-dimensional electron gas above the channel layer and the channel layer, the gate electrode is positioned above the barrier layer, and the P-type nitride semiconductor layer can not obviously exhaust the two-dimensional electron gas in the channel except the gate stack; when turned on, the HEMT is realized by controlling different voltages of the gate and the drain. By selecting a suitable gate electrode material, it is also possible to deplete part or all of the two-dimensional electron gas at the gate stack to achieve a normally-off device, while maintaining a high concentration of the two-dimensional electron gas in other regions to achieve good turn-on characteristics.

Fig. 4 is another example of the high voltage HEMT according to the embodiment of the present invention. The structure is that a nucleation layer 402 is formed on a substrate 401, a P-type nitride semiconductor layer 403 is epitaxially formed on the nucleation layer 402, a layer of low-doped or unintentionally doped nitride semiconductor layer 404 is formed on the P-type nitride semiconductor layer 403 as a channel layer, a barrier layer 405 is formed on the low-doped or unintentionally doped nitride semiconductor layer 404, the low-doped or unintentionally doped nitride semiconductor layer 404 and the barrier layer 405 form a heterojunction structure, two-dimensional electron gas is formed at an interface, a source electrode 407 and a drain electrode 408 are electrically connected with the two-dimensional electron gas above the channel layer 404, and a gate electrode 409 is located above the barrier layer and is in contact with the P-type nitride semiconductor layer through a body electrode 406. The body electrode controls the potential of the P-type nitride semiconductor layer, controls the source electrode, the drain electrode and the gate electrode to realize stable work of the HEMT, and controls the potential of the independent body electrode 406, so that the rapid switching-off operation of the HEMT can be realized.

Fig. 5 is another example of the high voltage HEMT according to the embodiment of the present invention. Compared with fig. 3, the method is distinguished in that strong P-type doping is carried out only in the region of the corresponding P-type nitride semiconductor layer 503 in point connection with the source electrode 506 to form a strong P-type doped region 509, the gate electrode 508 is positioned above the barrier layer 505, the drain electrode 507 is electrically connected with two-dimensional electrons at the interface of the channel layer 504 and the barrier layer 505, and the source electrode forms good ohmic contact with the strong P-type region formed by ion implantation or epitaxial growth in the P-type nitride semiconductor layer, thereby controlling the potential of the P-type nitride semiconductor layer. When turned on, the HEMT is realized by controlling different voltage potentials of the gate electrode and the drain electrode, and a voltage potential of the P-type nitride semiconductor layer.

Wherein the formation of the strongly P-type doped region 509 comprises two modes:

after the nucleation layer 502 is formed above the substrate 501 and the P-type nitride semiconductor layer 503 is grown, a strong P-type doped region 509 can be formed by implanting P-type impurities into a local region through ions, which is beneficial to forming ohmic contact control with the P-type nitride semiconductor layer; or by using a doping modulation technique, a strong P-type doped region 509 is formed on the nucleation layer through region selection/lateral epitaxy, and then a complete P-type nitride semiconductor layer 503 is formed, so that the subsequent P-type ohmic contact quality is improved and the contact resistance is reduced. The P-type nitride semiconductor layer is lightly doped or undoped when a portion near the predetermined drain electrode is epitaxially grown in the selected region/lateral direction. After the P-type nitride semiconductor is grown, a layer of low-doped or undoped semiconductor layer is grown, and the undoped channel layer on the upper surface of the P-type nitride semiconductor layer is realized. After P-type nitride semiconductor is epitaxially grown in the selected area/side direction, a part of the upper surface nitride semiconductor layer is removed through a planarization or etching process, and then a barrier layer structure or a channel layer and a barrier layer structure are epitaxially formed, so that the situation that the two-dimensional electron gas concentration and the normal work of the HEMT are influenced due to the fact that part of energy band structures at the channel are changed due to inappropriate doping concentration can be avoided.

A local region of the P-type nitride semiconductor layer is ion-implanted with P-type impurities to form a strong P-type doped region, and such P-type doped impurities are not uniformly distributed in most cases. But under certain distribution condition, the functions of better reducing electric field peak or being more beneficial to realizing ohmic contact and the like can be realized. Typical P-type dopant impurities include P-type dopant atoms such as magnesium, zinc, etc.

The modulation of the hole carrier concentration can also reduce the activation degree of local P-type doping through local ion injection passivation impurities, so as to achieve the purpose of reducing the hole carrier concentration of a partial region, and thus, the distribution of the hole carriers can also be adjusted, and the purpose of finely adjusting the electric field distribution is achieved. Typical passivating impurities are C, N, Ar and the like.

Other related arrangements besides the basic structure of the embodiment represented by fig. 2-5 may exist, for example, a passivation layer, a cap layer, various field plate structures, an additional electrode structure for controlling the electric field uniformity of the channel, etc. are arranged above the barrier layer; a gate dielectric layer, a P-GaN layer and other structural layers can be arranged below the gate electrode; the arrangement of these related functional structures and the arrangement of the disclosed functional structures of other HEMTs are not excluded from embodiments of the present invention.

The nucleation layers and epitaxial growth of fig. 2-5 may be formed as in fig. 6-8 or otherwise feasible.

As shown in fig. 6, an insulating layer 602 is formed on a substrate 601, an opening region is formed through a mask, etching, or the like, a nucleation layer 603 is epitaxially grown at the opening region, and a P-type nitride semiconductor layer 604 is grown as a channel layer on the nucleation layer by selective/lateral epitaxy.

As shown in fig. 7, a nucleation layer 702 is epitaxially grown on a substrate 701, and then an insulating layer 703 is formed, the insulating layer is masked, etched, etc. to form an open region 704 to expose the nucleation layer 702, and then a P-type nitride semiconductor layer is epitaxially grown on the nucleation layer at the open region by a selective/lateral epitaxy method.

As shown in fig. 8, an insulating layer 802 is formed on a substrate 801, an opening region is formed through a mask, etching, and other processes, a nucleation layer 803 is epitaxially grown at the opening region, a buffer layer 804 is formed on the nucleation layer 803 to improve the crystal quality, and the buffer layer 804 may be a strong P-type doped nitride semiconductor layer region, such as a strong P-type doped strong P-GaN layer, which may also serve as a strong P-type doped region for forming a good ohmic contact with an electrode.

For silicon substrates, the nucleation layer is typically an AlN layer, which is beneficial to reduce the lattice mismatch of the substrate material and the III-nitride semiconductor material layer and to avoid the melt-back (Ga-back) effect of the Ga source. When the P-type nitride semiconductor layer is grown in a selective area/lateral epitaxy mode on the nucleating layer or the buffer layer, the gas mixture containing the precursor contains hydrogen, so that the P-type nitride semiconductor layer with good lateral growth performance through Selective Epitaxial Growth (SEG) is more favorably grown; while selective/lateral epitaxial growth is undesirable in nucleation on the insulating layer to prevent the growth quality of the P-type nitride semiconductor layer from being affected, it is necessary to control the nucleation core formation on the insulating layer and the growth of the low-quality nitride semiconductor during the growth process. Particularly, a gas mixture of chlorine can be used, the etching action of the Cl-containing atmosphere is utilized to keep a certain etching rate of the weak growth core on the insulating layer in the process, so that the weak growth core is controlled to be extremely low, the Cl-containing atmosphere does not influence the growth of the P-type nitride semiconductor layer grown at a high speed in the upper selection area/lateral epitaxy growth of the nucleation upper layer, and the selective etching action of the Cl atmosphere is utilized to be beneficial to controlling the quality of the selection area/lateral epitaxy P-type nitride semiconductor layer. In the present invention, a precursor mixed atmosphere containing hydrogen and/or chlorine is particularly used for the selection of the P-type nitride semiconductor layer grown by zone/lateral epitaxy.

In addition, different doping profiles of a weak P-type, a strong P-type or other regulatory P-type nitride semiconductor layer can be selectively formed with different dopant amounts on the entire surface of the P-type nitride semiconductor layer depending on the function. The concentration distribution of the grown P-type nitride semiconductor layer over the entire surface can be controlled by controlling the amount of P-type dopant at different stages of epitaxial growth to facilitate adjustment of electric field distribution, and high quality P-type doped nitride semiconductor layers and spatial adjustment thereof can be obtained by adjusting the electric field distribution technique.

As shown in fig. 9, an insulating layer 902 may be formed over a substrate 901, an opening region may be formed by a mask, etching, or the like, a nucleation layer 903 may be epitaxially grown in the opening region, and a P-type nitride semiconductor layer 905 may be grown as a channel layer on the nucleation layer by selective/lateral epitaxy. After the P-type nitride semiconductor layer 905 is grown, a strong P-type doped region 904 can be formed by ion-implanting P-type impurities in a local region, which is advantageous for forming ohmic contact control with the P-type nitride semiconductor layer.

As shown in fig. 10, an insulating layer 1002 is formed on a substrate 1001, an opening region is formed through a mask, etching, or other processes, a nucleation layer 1003 is epitaxially grown in the opening region, a P-type nitride semiconductor layer 1004 is grown on the nucleation layer through selective/lateral epitaxy, and then a channel layer 1005, a barrier layer 1006, a passivation layer 1007, and other structures are sequentially formed. Because the doping concentration in the channel layer is very low or no intentional doping is carried out, the ion scattering received during the two-dimensional electron gas transmission can be effectively reduced. A barrier layer 1006 is deposited and an in-situ SiN passivation layer 1007 is deposited in the same deposition apparatus. That is, after the barrier layer 1006 is deposited, the in-situ SiN passivation layer 1007 is directly deposited in the same equipment without taking out the epitaxial wafer. The SiN passivation layer effectively protects the surface of the barrier layer 1006 and is of high quality. The barrier layer/SiNx interface obtained in this way has fewer defect states. The in-situ SiNx layer can play a role in passivating the surface of the barrier layer, and can also be used as a gate dielectric layer at a gate stack position by only reserving the SiNx layer in a preset gate electrode area through an etching process.

Note that the P-type nitride semiconductor layer may be directly in contact with the barrier layer as the channel layer. However, since doping in the P-type nitride semiconductor layer brings about a significant carrier scattering effect, it is more preferable to create an unintentionally doped or lowly doped channel layer between the barrier layer and the P-type nitride semiconductor layer. Scattering of the two-dimensional electron gas when the two-dimensional electron gas flows through the channel layer can be greatly reduced. The use of an intervening channel layer is more preferred than necessary.

An insulating

layer

1102 and 1202 is formed on a

substrate

1101 and 1201, an opening area is formed through the processes of masking, etching and the like,

nucleation layers

1103 and 1203 are epitaxially grown at the opening area, strong P-type doped

areas

1110 and 1211 are formed on the

nucleation layers

1103 and 1203 through selective/lateral epitaxy, and P-type

nitride semiconductor layers

1104 and 1204 are epitaxially grown. After the P-type

nitride semiconductor layers

1104, 1204 are grown, strong P-type doped

regions

1110, 1211 can be formed by ion-implanting P-type impurities in local regions, facilitating ohmic contact of the electrodes with the P-type nitride semiconductor layers. Over the P-type

nitride semiconductor layers

1104, 1204,

channel layers

1105, 1205 are formed,

barrier layers

1106, 1206 are formed, source electrodes 1107, 1207 are formed,

gate electrodes

1109, 1209, and

drain electrodes

1108, 1208 are formed, the

drain electrodes

1108, 1208 are in electrical contact with two-dimensional electron gas over the channel layers 1105, 1205, and in the embodiment shown in fig. 12, body electrodes 1210, etc. are also included.

In the embodiment shown in fig. 11, a source electrode 1107 is connected to a strongly P-type doped region 1110 in a P-type nitride semiconductor layer through a two-dimensional electron gas, a drain electrode 1108 is in contact with the two-dimensional electron gas above a channel layer 1105, and a gate electrode 1109 is located above a barrier layer 1106. In this device structure, when the potential of the source electrode 1107 is normally fixed at 0V and normally off and on operations are performed, HEMT is realized by controlling different voltages of the gate and the drain.

In the embodiment shown in fig. 12, source electrode 1207, drain electrode 1208 are in two-dimensional electron gas contact over channel layer 1205, and gate electrode 1209 is over barrier layer 1206. A good ohmic contact is formed with the semiconductor layer of the strong P-type doped region 1211 in the P-type nitride semiconductor layer 1204 through the body electrode 1210, thereby controlling the potential of the P-type nitride semiconductor layer 1204 alone. In normally-off and on operations, the HEMT is realized by controlling different voltage potentials of the gate electrode, the source electrode, and the drain electrode, and the voltage potential of the P-type nitride semiconductor layer 1204. And by independently controlling the potential of the body electrode 406, a fast turn-off operation of the HEMT can be achieved.

In the embodiments shown in fig. 13 and 14, the functional layers are exemplary.

Insulating

layers

1302 and 1402 are formed on

substrates

1301 and 1401, an opening region is formed through the processes of masking, etching and the like,

nucleation layers

1303 and 1403 are epitaxially grown at the opening region, and P-type nitride semiconductor layers 1304 and 1404 are grown on the

nucleation layers

1303 and 1403 through selective/lateral epitaxy.

In the epitaxial growth of the P-type nitride semiconductor layers 1304, 1404, the P-type nitride semiconductor layer first regions (1304-1, 1404-1), the strong P-type nitride semiconductor layer first regions (1304-2, 1404-2), and the P-type nitride semiconductor layer second regions (1304-3, 1404-3) are formed in this order by a doping modulation technique, wherein the strong P-type nitride semiconductor layer first regions (1304-2, 1404-2) are located below the gate electrode, and can deplete the two-dimensional electron gas in the channel layer below the gate electrode 1410 by 95% or more at 0 bias.

Channel layers

1305 and 1405,

barrier layers

1306 and 1406,

gate electrodes

1310 and 1410 are formed on the barrier layers 1306 and 1406, and

drain electrodes

1309 and 1409 are provided in the barrier layers and electrically connected to two-dimensional electrons, respectively. In the embodiment shown in fig. 13, after the source electrode 1308 is subjected to masking, etching, and other processes, the channel layer 1305 is penetrated to form an electrical contact with the first region (1304-1) of the P-type nitride semiconductor layer, and the potential of the P-type nitride semiconductor layer 1304 is controlled to be consistent with that of the source electrode, for example, the potential can be fixed at 0V, and the on and off of the enhancement type HEMT can be controlled by only controlling the potentials of the gate electrode 1310 and the drain electrode 1309. In the embodiment shown in fig. 14, after the P-type nitride semiconductor layer 1404 is grown, a strong P-type doped region 1404-4 may be formed by implanting P-type impurities into a local region through ion implantation, and after the source electrode 1408 is subjected to masking, etching, and the like, the channel layer 1405 penetrates through the strong P-type doped region 1404-4 of the P-type nitride semiconductor layer to form an electrical contact, and the strong P-type doped region 1404-4 facilitates ohmic contact between the source electrode and the P-type nitride semiconductor layer, reduces on-resistance, and facilitates precise control of the potential of the P-type nitride semiconductor layer 1404. The potential of the P-type nitride semiconductor layer 1404 is controlled to be uniform with the source electrode, and can be fixed at 0V, for example, and the on and off of the enhancement type HEMT can be controlled by controlling only the potentials of the gate electrode 1410 and the drain electrode 1409.

For the embodiment shown in fig. 13 to 14, the doping concentration is low or undoped at the end of the epitaxial growth of the second region (1304-3, 1404-3) of the P-type nitride semiconductor layer, i.e., near the region where the drain electrode is intended. So as to enhance the voltage endurance capability of the device and simultaneously have good on-state current conduction capability. After the selective area/lateral epitaxial growth is completed, a part of the nitride semiconductor layer on the upper surface can be removed through a planarization or etching process, and then a barrier layer structure or a channel layer and a barrier layer structure are formed through epitaxy. So as to avoid the negative influence of doping with different concentrations on the device structure above the channel layer. And a source electrode is arranged above the P-type nitride semiconductor layer corresponding to the opening region of the nucleation layer, and the selected region/lateral epitaxial growth direction radially expands by taking the projection surface region of the source electrode as the center, so that the whole surface of the substrate is favorably paved in a high-proportion mode.

In the embodiments shown in fig. 13 to 14, the potential of the P-type nitride semiconductor layer may be controlled in such a manner that the source electrode and the drain electrode are provided only in the barrier layer and electrically connected to the two-dimensional electron gas, and the body electrode is separately provided and electrically connected to the region of the P-type nitride semiconductor layer above the nucleation layer (the strongly P-type doped region in the case of strong doping), as shown in fig. 12, to independently control the potential of the P-type nitride semiconductor layer.

The above description is only an example of the present invention and is not intended to limit the scope of the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A high electron mobility transistor with high withstand voltage capability includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer, a substrate; the P-type nitride semiconductor layer is located between the barrier layer and the substrate, which is insufficient to substantially deplete the two-dimensional electron gas in the channel except for the gate stack, and the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas.

2. The transistor of claim 1, further comprising a nucleation layer between the P-type nitride semiconductor layer and the substrate.

3. The transistor according to claim 1, wherein a low-doped or unintentionally doped nitride semiconductor layer is further interposed between the barrier layer and the P-type nitride semiconductor layer.

4. A transistor according to any one of claims 1 to 3, wherein a portion of the source electrode in contact with the P-type nitride semiconductor layer is a highly doped region, which facilitates formation of a good ohmic contact.

5. A transistor according to any of claims 1-3, characterized in that the P-type nitride semiconductor layer is grown by selective/lateral epitaxial growth.

6. The transistor of claim 5, wherein the P-type nitride semiconductor layer has a controlled variation in doping concentration during selective/lateral epitaxial growth to facilitate formation of a modulation doped P-type nitride semiconductor layer in different regions.

7. The transistor of claim 5, wherein the P-type nitride semiconductor layer is lightly doped or undoped when a portion near the intended drain electrode is epitaxially grown in the selected region/lateral direction.

8. The transistor of claim 7, wherein after the selective/lateral epitaxial growth, a part of the region in the height direction of the P-type nitride semiconductor layer is removed by a planarization or etching process.

9. A transistor according to any one of claims 1 to 3, wherein an insulating layer is provided on the substrate, the insulating layer is etched to form an open region, a nucleation layer is formed at the open region, and then an epitaxial layer structure including a P-type nitride semiconductor layer is grown by selective/lateral epitaxy; or growing a nucleation layer on the substrate, forming an insulating layer on the nucleation layer, exposing the nucleation layer through the opening of the insulating layer, and growing an epitaxial layer structure containing the P-type nitride semiconductor layer in a selective area/lateral epitaxial mode.

10. The transistor of claim 9, wherein a buffer layer is formed over the nucleation layer prior to growing the P-type nitride semiconductor layer, the buffer layer being a layer of highly doped P-type nitride semiconductor material.

11. The transistor according to any one of claims 1 to 3, wherein a concentration of a channel two-dimensional electron gas depleted in the P-type nitride semiconductor layer at 0 bias is less than 80% of a concentration of a channel two-dimensional electron gas without P-type doping in the P-type nitride semiconductor layer, except for a gate stack region.

12. A transistor according to any one of claims 1 to 3, wherein when the P-type nitride semiconductor layer is formed, a P-type nitride semiconductor layer first region, a strong P-type nitride semiconductor layer first region, and a P-type nitride semiconductor layer second region are formed in this order, wherein the P-type nitride semiconductor layer first region is located below the source electrode, the strong P-type nitride semiconductor layer first region is located below the gate electrode, and the P-type nitride semiconductor layer second region is located below the drain electrode, and the strong P-type nitride semiconductor layer first region can deplete the two-dimensional electron gas of at least a part of the region below the channel layer of the gate electrode by 95% or more at 0 bias.

13. A high electron mobility transistor with high withstand voltage capability includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer, a substrate; the P-type nitride semiconductor layer is located between the barrier layer and the substrate and is insufficient to substantially deplete the two-dimensional electron gas in the channel except for the gate stack, and the source and drain electrodes are both in electrical contact with the two-dimensional electron gas, and a separate body electrode is in electrical contact with the P-type nitride semiconductor layer.

14. The transistor of claim 13, further comprising a nucleation layer between the P-type nitride semiconductor layer and the substrate.

15. The transistor of claim 13, wherein an insulating layer is formed on the substrate, the insulating layer is etched to form an open region, a nucleation layer is formed at the open region, and then an epitaxial layer structure including a P-type nitride semiconductor layer is grown by selective/lateral epitaxy; or growing a nucleation layer on the substrate, forming an insulating layer on the nucleation layer, exposing the nucleation layer through the opening of the insulating layer, and growing an epitaxial layer structure containing the P-type nitride semiconductor layer in a selective area/lateral epitaxial mode.

16. A transistor according to any of claims 13 to 15 wherein the P-type nitride semiconductor layer has a controlled variation in doping concentration during selective/lateral epitaxial growth to facilitate formation of a modulation doped P-type nitride semiconductor layer in different regions.

17. A transistor according to any of claims 13 to 15, characterized in that the P-type nitride semiconductor layer is lightly doped or undoped when the portion near the intended drain electrode is selectively/laterally epitaxially grown.

18. A transistor according to any of claims 13-15, characterized in that after the P-type nitride semiconductor layer has been grown, a layer of low-doped or undoped semiconductor is grown, which renders the channel layer on the upper surface of the P-type nitride semiconductor layer undoped.

19. A transistor according to any of claims 13 to 15 wherein after the selective/lateral epitaxial growth, the barrier layer structure or the channel and barrier layer structures are epitaxially formed by removing a portion of the top surface nitride semiconductor layer by a planarization or etching process.

20. A transistor according to any one of claims 13 to 15, wherein in forming the P-type nitride semiconductor layer, a P-type nitride semiconductor layer first region, a strong P-type nitride semiconductor layer first region, and a P-type nitride semiconductor layer second region are formed in this order, wherein the P-type nitride semiconductor layer first region is located below the body electrode, the strong P-type nitride semiconductor layer first region is located below the gate electrode, and the P-type nitride semiconductor layer second region is located below the drain electrode, and the strong P-type nitride semiconductor layer first region can deplete the two-dimensional electron gas of at least a part of the region in the channel layer below the gate electrode by 95% or more at 0 bias.

21. The transistor according to claim 20, wherein, when forming the P-type nitride semiconductor layer, after a first region of a P-type nitride semiconductor layer, a first region of a strong P-type nitride semiconductor layer, and a second region of a P-type nitride semiconductor layer are formed in this order, and performing ion implantation in a region where the first region of the P-type nitride semiconductor layer is connected with the body electrode to form a strong P-type doped region, wherein the body electrode is connected with the strong P-type doped region to form ohmic contact, the first region of the strong P-type nitride semiconductor layer is positioned below the gate electrode, the second region of the P-type nitride semiconductor layer is positioned below the drain electrode, and the first region of the strong P-type nitride semiconductor layer can deplete more than 95% of two-dimensional electron gas in at least part of the channel layer below the gate electrode under 0 bias.

22. A transistor according to any of claims 13-15, characterized in that before growing the P-type nitride semiconductor layer, a buffer layer is formed above the nucleation layer, the buffer layer being a layer of highly doped P-type nitride semiconductor material.

23. A transistor according to any of claims 13 to 15 wherein after the growth of the P-type nitride semiconductor layer, a region of highly doped P-type nitride semiconductor layer is formed over the nucleation layer to facilitate ohmic contact with the associated electrode.

24. A transistor as claimed in claim 1 or 13, wherein a SiNx passivation layer is grown in-situ after the barrier layer is formed.

25. A transistor according to claim 1 or 13, wherein a gate insulating layer is added under the gate electrode to reduce off-state leakage current of the gate.

26. The transistor of claim 1 or 13, wherein the selective/lateral epitaxial growth nucleation layer employs a precursor mixed atmosphere containing hydrogen and/or chlorine.

27. The transistor according to claim 1 or 13, wherein a precursor mixed atmosphere containing hydrogen and/or chlorine is used for selective/lateral epitaxial growth of the P-type nitride semiconductor layer.

28. The transistor according to claim 1 or 13, wherein the P-type nitride semiconductor layer is at least partially located in a region between the source electrode and the gate electrode and between the gate electrode and the drain electrode.

29. The transistor according to claim 1 or 13, wherein a concentration of a channel two-dimensional electron gas depleted in the P-type nitride semiconductor layer at 0 bias is less than 80% of a concentration of a channel two-dimensional electron gas without P-type doping in the P-type nitride semiconductor layer, except for the gate stack region.