CN110556346B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN110556346B
CN110556346B CN201810960619.5A CN201810960619A CN110556346B CN 110556346 B CN110556346 B CN 110556346B CN 201810960619 A CN201810960619 A CN 201810960619A CN 110556346 B CN110556346 B CN 110556346B
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substrate
die
protective layer
semiconductor structure
encapsulant
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CN110556346A (zh
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余振华
郭宏瑞
蔡惠榕
张晁纶
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开半导体结构及其形成方法。所述半导体结构包括第一管芯、第二管芯、第一包封材料及保护层。第一管芯包括第一衬底。第二管芯结合到第一管芯且包括第二衬底。第一包封材料包封第一管芯。保护层设置在第一衬底的侧壁上且设置在所述第一衬底与第一包封材料之间，其中所述保护层的材料不同于第二衬底的材料及所述第一包封材料的材料。

Description

半导体结构及其形成方法
技术领域
本发明实施例涉及一种半导体结构。
背景技术
目前正在发展晶片级封装(wafer level packaging)的三维集成技术以满足对高密度集成封装的大小减小、高性能互连及异构集成(heterogeneous integration)的需求。
发明内容
本发明实施例的一种半导体结构包括第一管芯、第二管芯、第一包封材料及保护层。第一管芯包括第一衬底。第二管芯结合到第一管芯且包括第二衬底。第一包封材料包封第一管芯。保护层设置在第一衬底的侧壁上且设置在所述第一衬底与第一包封材料之间，其中所述保护层的材料不同于第二衬底的材料及所述第一包封材料的材料。
附图说明
图1是示出根据一些实施例的形成半导体结构的方法的流程图。
图2A到图2E是示出根据一些实施例的形成半导体结构的方法的示意图。
图3是示出根据一些实施例的形成半导体结构的方法的流程图。
图4A到图4C是示出根据一些实施例的形成半导体结构的方法的示意图。
图5A到图5H是示出根据一些实施例的形成半导体结构的方法的示意图。
图6A到图6E是示出根据一些实施例的形成半导体结构的方法的示意图。
图7A到图7D是示出根据一些实施例的形成半导体结构的方法的示意图。
图8是示出根据一些实施例的半导体结构的示意图。
图9A到图9G是示出根据一些实施例的形成半导体结构的方法的示意图。
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本发明。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第二特征形成在第一特征“之上”或第一特征“上”可包括其中第二特征及第一特征被形成为直接接触的实施例，且也可包括其中第二特征与第一特征之间可形成有附加特征、进而使得所述第二特征与所述第一特征可能不直接接触的实施例。另外，本发明可能在各种实例中重复使用参考编号及/或字母。此种重复是出于简洁及清晰的目的，而不是自身指示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“顶部(top)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。装置可具有其他取向(旋转90度或处于其他取向)且本文中所使用的空间相对性描述语可同样相应地进行解释。
也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(threedimensional，3D)封装或三维集成电路(3D integrated circuit，3DIC)器件进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试焊盘，以容许对3D封装或3DIC进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包含对已知良好管芯的中间验证的测试方法一起使用，以提高良率(yield)及降低成本。
图1是示出根据一些实施例的形成半导体结构的方法的流程图。图2A到图2E是示出根据一些实施例的形成半导体结构的方法的示意图。
参照图1及图2A，在步骤S10中，提供第一衬底110。在一些实施例中，第一衬底110可包括：元素半导体，例如具有晶体结构、多晶结构、非晶结构及/或其他适合结构的硅或锗；化合物半导体，包括碳化硅(silicon carbide)、砷化镓(gallium arsenic)、磷化镓(gallium phosphide)、磷化铟(indium phosphide)、砷化铟(indium arsenide)及/或锑化铟(indium antimonide)；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；任何其他适合的材料；及/或它们的组合。在一些实施例中，半导体的组合可呈混合物形式或梯度形式，例如Si与Ge的比率跨越各个位置而变化的衬底。在一些实施例中，当使用蚀刻剂蚀刻第二衬底210(示出在图2C中)时，第一衬底110的材料相对于第二衬底210的材料具有低的蚀刻选择性(etching selectivity)。换句话说，可通过相同的蚀刻剂移除第一衬底110的材料及第二衬底210的材料。在一些实施例中，第一衬底110与第二衬底210可包含相同的材料。在一些实施例中，举例来说，第一衬底110及第二衬底210是硅衬底。然而，本发明并非仅限于此。在一些替代实施例中，举例来说，第一衬底110与第二衬底210可具有不同的材料。
在一些实施例中，第一衬底110包括第一介电层112及位于第一介电层112之上的第一焊盘116。提供第一介电层112及第一焊盘116中的至少一者以用于结合。在一些实施例中，第一介电层112包含例如氧化硅(SiOx)、氮氧化硅(SiOxNy)、掺杂氟的氮氧化硅(SiOxNyFz)、任何其他适合的材料及/或它们的组合。在一些实施例中，第一介电层112包括单一介电层或多个介电层。在一些实施例中，举例来说，第一介电层112的厚度介于0.7微米(um)到1um之间。
在一些实施例中，在第一介电层112的开口114中形成第一焊盘116。在一些实施例中，第一焊盘116中具有凹陷118，换句话说，开口114不被第一焊盘116填满。在一些实施例中，举例来说，第一焊盘116为U形。然而，在一些替代实施例中，第一焊盘116可填满开口114或从开口114突出。在一些实施例中，可通过在开口114的侧壁与底表面上共形地形成导电材料来形成具有凹陷118的第一焊盘116。在一些替代实施例中，可通过在开口114中填充导电材料且移除导电图案的一部分来形成具有凹陷118的第一焊盘116。在一些实施例中，第一焊盘116是由例如铜(Cu)、铜合金、铝(Al)、铝合金、镍(Ni)、镍合金、任何其他适合的材料及/或它们的组合等导电材料制成。第一焊盘116包括单一金属层或多个金属层。在一些实施例中，可通过沉积工艺(deposition process)、电镀工艺(electroplating process)、任何其他适合的工艺及/或它们的组合来形成第一焊盘116。在一些实施例中，可在第一焊盘116旁边形成扩散障壁层120。在一些实施例中，第一焊盘116的顶表面与第一介电层112的顶表面实质上共面。在一些实施例中，举例来说，第一焊盘116的厚度介于0.1um到0.3um之间，且凹陷118的深度介于0.4um到0.9um之间。
在一些实施例中，在第一衬底110与第一介电层112之间进一步形成介电层122及导电层124。在一些实施例中，举例来说，介电层122包含例如氧化硅(SiO2)、氮化硅(SiNx)、任何其他适合的材料及/或它们的组合等低介电常数(低k)材料。介电层122包括单一介电层或多个介电层。举例来说，介电层122及导电层124的厚度介于0.7um到1um之间。导电层124形成在介电层122中，且第一焊盘116电连接到导电层124。在一些实施例中，导电层124的顶表面与介电层122的顶表面实质上共面。在一些实施例中，举例来说，第一焊盘116的宽度小于导电层124的宽度。然而，在一些替代实施例中，举例来说，第一焊盘116的宽度可等于或大于导电层124的宽度。导电层124是由例如铜(Cu)、铜合金、铝(Al)、铝合金、任何其他适合的材料及/或它们的组合等导电材料制成。在一些替代实施例中，可在导电层124旁边形成扩散障壁层(未示出)。
在一些实施例中，第一衬底110可包括位于其上的更多个介电层及更多个导电层。另外，第一衬底110可包括例如逻辑器件等多个集成有源器件。逻辑器件包括应用处理器(application processor，AP)、***芯片(system on chip，SoC)或类似物。在一些实施例中，***芯片(SoC)包括调制解调器模块。基于工艺要求，可使用例如存储器件、金属氧化物半导体场效晶体管(metal oxide semiconductor field effect transistor，MOSFET)器件、互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)器件及/或双极结晶体管(bipolar junction transistor，BJT)器件等其他类型的有源器件。
参照图1及图2B，在步骤S20中，形成保护层130以覆盖第一衬底110的暴露表面。在一些实施例中，举例来说，在第一衬底110的侧壁110a及表面110b上形成保护层130。在一些实施例中，在第一衬底110的相对两表面上形成第一介电层112与保护层130。举例来说，在第一衬底110的顶表面上形成第一介电层112，且在第一衬底110的底表面上形成保护层130。在一些实施例中，第一衬底110的暴露表面被保护层130完全覆盖，即第一衬底110不被暴露出。在一些实施例中，保护层130直接接触第一衬底110。举例来说，保护层130为U形。在一些实施例中，位于侧壁110a上的保护层130的顶表面与第一衬底110的顶表面及介电层122的底表面实质上齐平。然而，本发明并非仅限于此。在一些替代实施例中，保护层130的顶表面可低于或高于第一衬底110的顶表面。换句话说，第一衬底110的侧壁110a的一部分可被暴露出，或者介电层112、122中的至少一者的一部分可被保护层130覆盖。在一些替代实施例中，可仅在第一衬底110的侧壁110a或底表面110b上形成保护层130。
在一些实施例中，保护层130的材料不同于第二衬底210的材料。在一些实施例中，举例来说，当使用蚀刻剂蚀刻第二衬底210时，第二衬底210的材料相对于保护层130的材料的蚀刻选择性大于20。在一些实施例中，举例来说，当使用蚀刻剂蚀刻硅时，保护层130的材料相对于硅具有蚀刻选择性。在一些实施例中，保护层130可包含氧化硅(SiO2)、氮化硅(SiNx)、氮氧化硅(SiOxNy)、碳化硅(SiC)、任何其他适合的材料或它们的组合。在一些实施例中，保护层130可包含氧化硅(SiO2)或氮化硅(SiNx)，且可通过例如物理气相沉积(physical vapor deposition，PVD)工艺、化学气相沉积(chemical vapor deposition，CVD)工艺、等离子体增强型化学气相沉积(plasma-enhanced chemical vapordeposition，PECVD)工艺、电化学沉积(electrochemical deposition，ECD)工艺、分子束外延(molecular beam epitaxy，MBE)工艺或原子层沉积(atomic layer deposition，ALD)工艺等沉积工艺形成保护层130。在一些替代实施例中，保护层130可包含模塑化合物(molding compound)，且可通过模塑工艺(molding process)形成保护层130。在一些替代实施例中，保护层130可为玻璃衬底，且可通过粘合剂将第一衬底110粘合到保护层130。在一些实施例中，举例来说，保护层130的厚度介于502纳米(nm)到2um之间。
参照图1及图2C，在步骤S30中，提供第二衬底210，且保护层130的材料不同于第二衬底210的材料。在一些实施例中，如以上所提及，当使用蚀刻剂蚀刻第二衬底210时，第一衬底110的材料相对于第二衬底210的材料具有低的蚀刻选择性。在一些实施例中，第二衬底210包括第二介电层212及位于第二介电层212之上的第二焊盘214。提供第二介电层212及第二焊盘214中的至少一者以用于结合。在一些实施例中，举例来说，第二焊盘214填满第二介电层212的开口，且因此第二介电层212的顶表面与第二焊盘214的顶表面共面。在一些实施例中，举例来说，第二介电层212及第二焊盘214的厚度介于0.7um到1um之间。在一些实施例中，在第二衬底210与第二介电层212之间进一步设置介电层216及导电层218。导电层218设置在介电层216中且电连接至第二焊盘214。第二衬底210的材料、第二介电层212的材料、第二焊盘214的材料、介电层216的材料及导电层218的材料可分别相似于第一衬底110的材料、第一介电层112的材料、第一焊盘116的材料、介电层122的材料及导电层124的材料，且因此本文中不再予以赘述。在一些实施例中，第二衬底210的材料、第二介电层212的材料、第二焊盘214的材料、介电层216的材料及导电层218的材料可各自相同于或不同于第一衬底110的材料、第一介电层112的材料、第一焊盘116的材料、介电层122的材料及导电层124的材料。在一些实施例中，举例来说，第一介电层112的材料可不同于第二介电层212的材料。然而，在一些替代实施例中，第一介电层112的材料可相同于第二介电层212的材料。
在一些实施例中，在第二焊盘214上进一步形成凸块220以进行结合。在一些实施例中，凸块220在第二衬底210之上设置在第二介电层212上且从第二介电层212突出。在一些实施例中，举例来说，凸块220的宽度小于第一焊盘116的凹陷118的宽度。在一些实施例中，凸块220是例如锡-银(SnAg)焊料凸块等无铅(lead free，LF)凸块。在一些替代实施例中，举例来说，可在凸块220与第二焊盘214之间形成例如镍(Ni)层等至少一个导电层。
参照图1及图2D，在步骤S40中，对第一衬底110与第二衬底210进行结合。在一些实施例中，将第二衬底210翻转，且通过第一介电层112与第二介电层212对第一衬底110与第二衬底210进行结合。在一些实施例中，第一衬底110与第二衬底210面对面地对齐，其中第一衬底110的前侧(例如，第一介电层112侧)面对第二衬底210的前侧(例如，第二介电层212侧)。在一些实施例中，在第一衬底110的相对两侧上形成保护层130与第二衬底210。在一些实施例中，举例来说，第一衬底110及第二衬底210是芯片对芯片结合(chip to chipbonding)。在一些替代实施例中，举例来说，第一衬底110及第二衬底210是芯片对晶片结合(chip to wafer bonding)或晶片对晶片结合(wafer to wafer bonding)。
在一些实施例中，第一衬底110的第一焊盘116还结合到第二衬底210的凸块220。换句话说，可通过例如混合结合(hybrid bonding)对第一衬底110与第二衬底210进行结合。在一些实施例中，将突出凸块220***第一焊盘116的凹陷118中以接触第一焊盘116，且可在凸块220与第一焊盘116之间形成金属间化合物(intermetallic compound，IMC)层(未示出)。在一些实施例中，由于凸块220的大小被设计成小于第一焊盘116的凹陷118的大小，因此在对第一衬底110与第二衬底210进行结合之后在凸块220与第一焊盘116的内侧壁116a之间会形成间隙126。在一些实施例中，间隙126可被IMC层局部填充或者被IMC层填满。在一些实施例中，由于存在大小差异，因此凸块220可轻易地结合到第一焊盘116，且凸块220与第一焊盘116的对齐工艺的窗口(window)增大。另外，第一衬底110的第一焊盘116凹陷且第二衬底210的凸块220突出，且因此它们可更紧地结合在一起。应注意，第一衬底110与第二衬底210被例示成具有相同的直径，但本发明并非仅限于此。在一些替代实施例(未示出)中，第一衬底110与第二衬底210可具有不同的直径。在一些实施例中，举例来说，保护层130的侧壁可与第二衬底210的侧壁在水平方向上分离开一距离。在一些替代实施例中，举例来说，保护层130的侧壁可与第二衬底210的侧壁对齐。
参照图1及图2E，在步骤S50中，在由保护层130保护第一衬底110的同时，通过蚀刻工艺EP来薄化第二衬底210。在一些实施例中，第一衬底110的材料与第二衬底210的材料对于蚀刻工艺EP的蚀刻剂具有相似的材料特性。在一些实施例中，当使用蚀刻剂蚀刻第二衬底210时，第一衬底110的材料相对于第二衬底210的材料实质上不具有蚀刻选择性。然而，由于第一衬底110由保护层130保护，因此第一衬底110免于受到损伤。在一些实施例中，举例来说，蚀刻工艺EP为湿法蚀刻工艺(wet etching process)。在一些实施例中，举例来说，蚀刻工艺EP为硅湿法蚀刻工艺(silicon wet etching process)。在硅湿法蚀刻工艺中，举例来说，蚀刻剂是氢氧化钾(KOH)或四甲基氢氧化铵(tetramethylammonium hydroxide，TMAH)的混合物，且可在介于80℃到100℃之间的温度下执行所述蚀刻工艺。在一些实施例中，在薄化工艺之后，第二衬底210的厚度可介于10um到40um之间。在一些实施例中，不需要在薄化第二衬底210之后移除保护层130。换句话说，保护层130被保留下来。
在薄化工艺之后，可对图2E所示结构执行例如包封工艺(encapsulatingprocess)及电连接形成工艺(forming process of electrical connection)等封装过程以形成封装。在一些替代实施例中，如果第一衬底110及第二衬底210中的至少一者是晶片，则可在封装过程之前执行切割工艺(dicing process)或单体化工艺(singulationprocess)。
一般来说，使用例如化学机械抛光(chemical mechanical polishing，CMP)等研磨工艺(grinding process)来薄化经结合结构的顶部衬底。然而，研磨工艺可能对例如经结合结构的焊盘等内部结构造成损伤。在一些实施例中，通过形成保护层130以覆盖经结合结构的底部衬底(即，第一衬底110)，例如湿法蚀刻工艺等蚀刻工艺仅移除经结合结构的顶部衬底(即，第二衬底210)的一部分而不损伤所述底部衬底的衬底。换句话说，尽管湿法蚀刻工艺是各向同性蚀刻工艺(isotropic etching process)，然而通过使用保护层，非期望蚀刻得到防止，且蚀刻方向被控制成朝向顶部衬底的一个方向。换句话说，通过形成保护层以及利用所述保护层及衬底相对于用于移除所述衬底的蚀刻剂的蚀刻选择性，可对经结合结构中的各衬底中薄的一者应用化学方法，且可防止因研磨工艺而施加机械力且因此损伤到所述经结合结构。另外，由于保护层可被保留在经结合结构中，因此不需要移除所述保护层。因此，保护层的形成将不会显著地增加制造半导体结构的成本或时间。
图3是示出根据一些实施例的形成半导体结构的方法的流程图。图4A到图4C是示出根据一些实施例的形成半导体结构的方法的示意图。
参照图3及图4A，在步骤S100中，通过第一焊盘116与第二焊盘214对第一衬底110与第二衬底210进行结合，且在第一衬底110的暴露表面上设置保护层130。在一些实施例中，除提供第一衬底110及第二衬底210但不提供介电层112、122、212、216以外，经结合结构及保护层130相似于图2D所示经结合结构及保护层130。换句话说，暴露出位于第一焊盘116、第二焊盘214、导电层124、218及凸块220旁边的扩散障壁层120的侧壁。在一些实施例中，举例来说，第一衬底110及第二衬底210是通过金属对金属结合(metal to metalbonding)进行结合。在一些实施例中，在对第一焊盘116与第二焊盘214进行结合之后，在凸块220与第一焊盘116的内侧壁116a之间会形成间隙126。
参照图3及图4B，在步骤S110中，在第一衬底110与第二衬底210之间形成介电材料230以包封第一焊盘116及第二焊盘214。在一些实施例中，经结合结构包括第一衬底110、第二衬底210、保护层130及介电材料230。在一些实施例中，将介电材料230形成为包封第一焊盘116、第二焊盘214及导电层124、218。另外，间隙126被介电材料230填满。在一些实施例中，介电材料230可包含氧化硅(SiOx)、氮氧化硅(SiOxNy)、掺杂氟的氮氧化硅(SiOxNyFz)、任何其他适合的材料及/或它们的组合。在一些实施例中，介电材料230可包括：模塑化合物，例如环氧模塑化合物(epoxy molding compound)；底部填充胶(underfill)；聚合物材料，例如苯并环丁烯(benzocyclobutene，BCB)聚合物、聚酰亚胺(polyimide，PI)及聚苯并恶唑(polybenzoxazole，PBO)；任何其他适合的材料；或者它们的组合。在一些实施例中，可通过沉积工艺、模塑工艺、底部填充胶工艺、任何其他适合的工艺或它们的组合来形成介电材料230。
参照图3及图4C，在步骤S120中，在由保护层130保护第一衬底110的同时，通过蚀刻工艺EP来薄化第二衬底210。在一些实施例中，蚀刻工艺EP相似于图2E中所述的蚀刻工艺EP，且本文中不再予以赘述。
图5A到图5H是示出根据一些实施例的形成半导体结构的方法的示意图。参照图5A，将包括衬底310的芯片(或管芯)C1结合到包括衬底410的晶片W。在一些实施例中，芯片C1还包括介电层312、位于介电层312中的多个焊盘314及位于焊盘314上的多个导电柱316。在一些实施例中，提供介电层312及焊盘314以用于结合。在一些实施例中，举例来说，芯片C1可为例如动态随机存取存储器(dynamic random access memory，DRAM)等任何适合的存储器芯片。在一些实施例中，举例来说，芯片C1还可包括位于衬底310与介电层312之间及衬底310与焊盘314之间的介电层、导电层及/或集成有源器件。在一些实施例中，衬底310、介电层312及焊盘314相似于衬底110、介电层112及焊盘116，且本文中不再予以赘述。
在一些实施例中，晶片W还包括介电层412及位于介电层412中的多个焊盘414。在一些实施例中，提供介电层412及焊盘414以用于结合。在一些实施例中，在晶片W上形成多个导电柱416以电连接焊盘414。举例来说，导电柱416可为铜柱。在一些实施例中，举例来说，晶片W还可包括位于衬底410与介电层412之间及衬底410与焊盘414之间的介电层、导电层及/或集成有源器件。在一些实施例中，衬底410、介电层412及焊盘414相似于衬底210、介电层212及焊盘214，且本文中不再予以赘述。
在一些实施例中，将芯片C1结合到晶片W的芯片区域410a中的一者以形成经结合结构。通过焊盘314及焊盘414将芯片C1结合到晶片W。在一些实施例中，举例来说，所述结合是芯片对晶片结合，且会形成晶片上芯片(chip-on-wafer，CoW)结构。在一些实施例中，将芯片C1设置在芯片区域410a中的各导电柱416之间。
参照图5B，形成保护层330以包封芯片C1。在一些实施例中，保护层330设置在芯片C1的暴露表面上，所述暴露表面是衬底310的侧壁310a及表面310b。在一些实施例中，保护层330形成在芯片C1之间且在晶片W之上覆盖芯片C1及导电柱416。在一些实施例中，保护层330相似于保护层130，且本文中不再予以赘述。在一些实施例中，保护层330包含例如模塑化合物(例如，环氧模塑化合物(EMC))、模塑底部填充胶、树脂、环氧树脂及/或类似物等包封材料，且可通过模塑工艺形成保护层330。
参照图5C，在由保护层330保护芯片C1的衬底310的同时，通过蚀刻工艺EP来薄化晶片W的衬底410。在一些实施例中，举例来说，芯片C1被保护层330完全覆盖。在一些实施例中，尽管当使用蚀刻剂蚀刻衬底410时芯片C1的衬底310相对于晶片W的衬底410具有相似的蚀刻选择性，然而由于衬底310由保护层330保护，因此芯片C1的衬底310不因蚀刻工艺EP而受到损伤。
参照图5D，切割图5C所示经结合结构以形成经结合单元502。在一些实施例中，经结合单元502包括芯片C1、从晶片W的芯片区域410a切割出的芯片(或管芯)C2及位于芯片C1上的保护层330。在一些实施例中，举例来说，经结合单元502是小外廓集成电路(smalloutline integrated circuit，SOIC)封装。
参照图5E，将经结合单元502放置到载体504上。在一些实施例中，依序地在载体504之上堆叠剥离层506及介电层508，并在介电层508之上形成多个导电杆510。将经结合单元502安装到上面形成有导电杆510的介电层508上。
参照图5F，将经结合单元502包封在包封材料512中，且对包封材料512及保护层330进行研磨。在一些实施例中，在介电层508上形成包封材料512以包封导电杆510及经结合单元502。在一些实施例中，包封材料512的材料可相同于或不同于保护层330的材料。在一些实施例中，包封材料512可包含模塑化合物、模塑底部填充胶、树脂、环氧树脂及/或类似物。
在一些实施例中，对包封材料512及保护层330进行研磨直到导电柱316、416的顶表面及导电杆510的顶表面被暴露出为止。在一些实施例中，举例来说，所述研磨工艺可为机械研磨、化学机械研磨(CMP)或另一适合的机制。在一些实施例中，举例来说，在研磨之后，保护层330的一些部分被移除，且剩余的保护层330设置在芯片C1的衬底310的侧壁上且设置在衬底310与包封材料512之间。
参照图5G，在包封材料512及经结合单元502之上形成电连接到经结合单元502的重布线路结构514。在一些实施例中，重布线路结构514形成在导电杆510的顶表面、包封材料512的顶表面、保护层330的顶表面及导电柱416的顶表面上以电连接经结合单元502的导电柱416与导电杆510。在一些实施例中，重布线路结构514包括交替堆叠的多个层间介电层及多个重布线导电图案。在形成重布线路结构514之后，在重布线路结构514上形成多个导电端子516。在一些实施例中，举例来说，导电端子516可为球栅阵列封装(ball gridarray，BGA)。
参照图5H，将图5G所示所形成结构从载体504剥离。在一些实施例中，将介电层508从剥离层506剥离，进而使得介电层508与载体504分离。在一些实施例中，将介电层508图案化成使得形成多个接触开口518以局部暴露出导电杆510。在此处，封装的形成过程实质上完成。在一些替代实施例中，可在接触开口518中放置多个导电端子(未示出)以电连接重布线路结构514与导电杆510。
在一些实施例中，在载体上安装晶片的衬底之前，通过蚀刻工艺而非研磨工艺来薄化晶片的所述衬底。因此，防止因研磨工艺而对经结合单元的内部结构造成损伤。因此，由经结合结构形成的封装的性质可得到改善。另外，在一些实施例中，保护层可用作芯片(即，芯片C1)旁边的包封体且因此所述包封体不是额外形成的，且制造半导体结构的成本或时间不会增加。
图6A到图6E是示出根据一些实施例的形成半导体结构的方法的示意图。图6A到图6E所示方法相似于图5A到图5H所示方法，主要差异在于在芯片的暴露表面上且在所述芯片与包封材料之间额外形成保护层。参照图6A，在芯片C1的暴露表面上形成保护层330a。在一些实施例中，在衬底310的侧壁310a及表面310b上设置保护层330a。接着，将芯片C1结合到晶片W，且保护层330包封上面具有保护层330a的芯片C1。在一些实施例中，保护层330a的材料相似于图2B所示保护层130的材料，且保护层330a的材料不同于保护层330的材料。在一些实施例中，保护层330包含例如模塑化合物(例如，环氧模塑化合物(EMC))、模塑底部填充胶、树脂、环氧树脂及/或类似物等包封材料，且可通过模塑工艺形成保护层330。
参照图6B，在由保护层330a及保护层330保护芯片C1的衬底310的同时，通过蚀刻工艺EP来薄化晶片W的衬底410。参照图6C，切割图6B所示经结合结构以形成经结合单元502，将经结合单元502放置在载体504上，且通过包封材料512包封经结合单元502。参照图6D，对保护层330a、保护层330及包封材料512进行研磨直到导电柱316、416的顶表面及导电杆510的顶表面被暴露出为止。在一些实施例中，在研磨之后，保护层330a位于芯片C1的侧壁上且位于芯片C1与保护层330之间。参照图6E，在保护层330、330a的顶表面、包封材料512的顶表面及导电杆510的顶表面上形成重布线路结构514。接着，将所形成结构从载体504剥离，且形成介电层508中的多个导电端子516及多个接触开口518，以形成封装。
图7A到图7D是示出根据一些实施例的形成半导体结构的方法的示意图。参照图7A，对第一芯片C1与第二芯片C2进行结合以形成经结合单元502，并在芯片C1上形成保护层330。在一些实施例中，芯片C1包括衬底310、介电层312及位于介电层312中的多个焊盘314。在一些实施例中，芯片C2包括衬底410、介电层412、位于介电层412中的多个焊盘414及电连接到焊盘414上的多个穿孔418。在一些实施例中，在衬底310的侧壁310a上形成保护层330，且暴露出衬底310的表面310b。在一些实施例中，保护层330的材料相似于图2B所示保护层130的材料。在一些实施例中，保护层330的材料包含例如模塑化合物(例如，环氧模塑化合物(EMC))、模塑底部填充胶、树脂、环氧树脂及/或类似物等包封材料，且可通过模塑工艺形成保护层330。在一些实施例中，可通过以下方式形成具有保护层330的经结合单元502：将多个芯片C1结合到包括多个芯片C2的晶片以形成经结合结构；形成保护材料以包封芯片C1；可选地研磨保护材料以形成保护层；以及切割经结合结构。
参照图7B，将经结合单元502放置在上面形成有多个导电杆510的载体504上。在一些实施例中，将芯片C1设置在芯片C2与载体504之间。
参照图7C，将经结合单元502包封(模塑)在包封材料512中。在一些实施例中，将保护层330在芯片C2下面设置在芯片C1与包封材料512之间。接着，通过蚀刻工艺EP来薄化芯片C2的衬底410直到穿孔418的顶表面被暴露出为止。在一些实施例中，蚀刻工艺EP为湿法蚀刻工艺。在薄化工艺期间，芯片C1的衬底310由保护层330及包封材料512保护，且因此衬底310不会因在蚀刻工艺EP中所使用的蚀刻剂而受到损伤。在此之后，对包封材料512进行研磨直到导电杆510的顶表面被暴露出且与芯片C2的顶表面共面为止。
参照图7D，在包封材料512的顶表面及导电杆510的顶表面上形成重布线路结构514。接着，将所形成结构从载体504剥离，且形成介电层508中的多个导电端子516及多个接触开口518，以形成封装。
应注意，保护层330被例示成单层，但本发明并非仅限于此。在一些替代实施例中，如图8中所示，在保护层330与芯片C1之间形成另一保护层330a。换句话说，所述保护层包括例如保护层330等第一层及例如保护层330a等第二层。在一些实施例中，在芯片C1中的每一者上形成保护层330a，且在结合到芯片C2(或包括多个芯片C2的晶片)之后，形成保护层330以包封芯片C1，且可选地对保护层330及保护层330a进行研磨以形成所述保护层。在一些实施例中，保护层330a的材料相似于图2B所示保护层130的材料，且保护层330a的材料不同于保护层330的材料。在一些实施例中，保护层330包含例如模塑化合物(例如，环氧模塑化合物(EMC))、模塑底部填充胶、树脂、环氧树脂及/或类似物等包封材料，且可通过模塑工艺形成保护层330。
在一些实施例中，通过蚀刻工艺而非研磨工艺来薄化安装在载体上的芯片的衬底。因此，防止因研磨工艺而对经结合单元的内部结构造成损伤。因此，由经结合结构形成的封装的性质可得到改善。另外，在一些实施例中，保护层可用作芯片(即，芯片C1)旁边的包封体且因此所述包封体不是额外形成的，且制造半导体结构的成本或时间不会增加。
图9A到图9G是示出根据一些实施例的形成半导体结构的方法的示意图。参照图9A，提供晶片W。晶片W包括衬底410、介电层420、位于介电层420中的多个导电图案422及形成在衬底410中且电连接到导电图案422的多个穿孔418。另外，晶片W还包括多个导电图案424及介电层426，且导电图案424形成在介电层426中且被介电层426覆盖以电连接到导电图案422。
参照图9B，将晶片W放置在载体428上，且对衬底410进行研磨直到穿孔418被暴露出为止。在一些实施例中，介电层426设置在载体428与衬底410之间，且晶片W的表面被载体428覆盖。举例来说，载体428是玻璃衬底。接着，在穿孔418中的一些穿孔418上形成电连接到所述一些穿孔418的位于介电层430中的多个焊盘414，且在介电层430上形成介电层412。
参照图9C，将芯片C1结合到晶片W，且在晶片W之上形成包封材料500以包封芯片C1。芯片C1包括衬底310、介电层312及多个焊盘314。另外，芯片C1还包括凸块318，凸块318形成在焊盘314上且从介电层312突出。
参照图9D，通过蚀刻工艺EP来薄化芯片C1的衬底310。在一些实施例中，在蚀刻工艺EP期间，晶片W的表面被载体428覆盖。在一些实施例中，尽管当使用蚀刻剂蚀刻芯片C1的衬底310时晶片W的衬底410相对于芯片C1的衬底310具有相似的蚀刻选择性，然而由于衬底410由载体428保护，因此晶片W的衬底410不因蚀刻工艺EP而受到损伤。换句话说，在一些实施例中，在薄化工艺期间，将载体428用作保护层。
参照图9E，切割图9D所示经结合结构以形成多个经结合单元502，并将所述多个经结合单元502从载体428剥离。经结合单元502包括芯片C1、覆盖芯片C1的包封材料500及从晶片W切割出的芯片C2。接着，将经结合单元502放置在上面形成有多个导电杆510的载体504上。在一些实施例中，将芯片C1设置在芯片C2与载体504之间。
参照图9F，将经结合单元502包封(模塑)在包封材料512中，并对包封材料512及介电层426进行研磨直到导电图案424的顶表面及导电杆510的顶表面被暴露出为止。
参照图9G，在导电杆510的顶表面、包封材料512的顶表面及导电图案424的顶表面上形成重布线路结构514。接着，将所形成结构从载体504剥离，且形成介电层508中的多个导电端子516及多个接触开口518，以形成封装。
在一些实施例中，使用载体作为晶片的衬底的保护层，通过蚀刻工艺而非研磨工艺来薄化结合到所述晶片的芯片的衬底。因此，防止因研磨工艺而对经结合结构的内部结构造成损伤。因此，由经结合结构形成的封装的性质可得到改善。另外，由于载体用作保护层，因此所述保护层不是额外形成的，且制造半导体结构的成本或时间不会增加。
一种半导体结构包括第一管芯、第二管芯、第一包封材料及保护层。第一管芯包括第一衬底。第二管芯结合到第一管芯且包括第二衬底。第一包封材料包封第一管芯。保护层设置在第一衬底的侧壁上且设置在所述第一衬底与第一包封材料之间，其中所述保护层的材料不同于第二衬底的材料及所述第一包封材料的材料。
根据一些实施例，其中所述第一衬底及所述第二衬底是硅衬底。
根据一些实施例，其中所述保护层的所述材料包含氧化硅、氮化硅或它们的组合。
根据一些实施例，其中所述保护层还设置在所述第一衬底的表面上，且所述表面与上面设置有所述第二管芯的表面相对。
根据一些实施例，其中所述保护层直接接触所述第一衬底。
根据一些实施例，还包括包封所述第一管芯及所述第二管芯的第二包封材料，其中所述第一包封材料设置在所述第二包封材料与所述保护层之间。
一种形成半导体结构的方法包括以下步骤。提供第一衬底。形成保护层，以覆盖所述第一衬底的暴露表面。提供第二衬底，其中所述保护层的材料不同于所述第二衬底的材料。对所述第一衬底与所述第二衬底进行结合。在由所述保护层保护所述第一衬底的同时，通过蚀刻工艺来薄化所述第二衬底。
根据一些实施例，其中所述蚀刻工艺是湿法蚀刻工艺。
根据一些实施例，其中形成所述保护层包括在所述第一衬底的表面上形成所述保护层，且所述表面与上面设置有所述第二衬底的表面相对。
根据一些实施例，其中所述保护层是载体。
根据一些实施例，其中所述保护层形成在所述第一衬底的侧壁上。
根据一些实施例，其中所述第一衬底包括位于所述第一衬底之上的第一焊盘，所述第二衬底包括位于所述第二衬底之上的第二焊盘，且所述第一衬底与所述第二衬底通过所述第一焊盘与所述第二焊盘进行结合。
根据一些实施例，在所述结合步骤之后，所述方法还包括：在所述第一衬底与所述第二衬底之间形成介电材料以包封所述第一焊盘及所述第二焊盘。
根据一些实施例，其中所述第一焊盘包括凹陷，所述第二衬底还包括凸块，所述凸块电连接到所述第二焊盘，且在所述结合步骤中，所述方法还包括将所述凸块***到所述凹陷中以电连接到所述第一焊盘。
一种形成半导体结构的方法包括以下步骤。提供第一管芯，其中所述第一管芯包括第一衬底。在所述第一衬底的暴露表面上形成保护层。提供晶片，其中所述晶片包括第二衬底及多个管芯区域，其中所述保护层的材料不同于所述第二衬底的材料。将所述第一管芯结合到所述晶片的所述多个管芯区域中的一者，以形成经结合结构。在由所述保护层保护所述第一衬底的同时，通过蚀刻工艺来薄化所述第二衬底。切割所述经结合结构以形成经结合单元，其中所述经结合单元包括所述第一管芯及从所述晶片的所述多个管芯区域中的一者切割出的第二管芯。将所述经结合单元放置到载体上。形成包封材料以包封所述经结合单元。对所述包封材料及所述经结合单元执行平坦化工艺。将所述经结合单元从所述载体剥离。
根据一些实施例，其中所述保护层形成在所述第一衬底的侧壁及表面上，且所述表面与上面设置有所述第二管芯的表面相对。
根据一些实施例，其中所述第二管芯设置在所述第一管芯与所述载体之间，且执行所述平坦化工艺包括移除所述经结合单元的所述第一衬底的所述表面上的所述保护层。
根据一些实施例，其中所述第一管芯设置在所述第二管芯与所述载体之间，且所述平坦化工艺与所述薄化工艺是通过所述蚀刻工艺对所述第二管芯的所述第二衬底的表面及所述包封材料的表面同时执行的。
根据一些实施例，其中所述保护层的材料包含包封材料。
根据一些实施例，其中所述保护层包括第一侧及位于所述第一层与所述第一管芯之间的第二层，且所述第一层的材料与所述第二层的材料不相同。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (35)

1.一种半导体结构，包括：
第一管芯，包括第一衬底；
第二管芯，经由所述第二管芯的表面的第一部分结合到所述第一管芯且包括第二衬底；
第一包封材料，包括模塑化合物，包封所述第一管芯且与所述第二管芯的所述表面的第二部分接触，其中所述第二管芯的所述表面的所述第一部分与所述第二部分为所述第二管芯的相同表面的不同部分，所述第二管芯的相同表面为所述第二管芯的上表面或下表面；以及
保护层，设置在所述第一衬底的侧壁上且设置在所述第一衬底与所述第一包封材料之间，且不延伸至所述第二管芯上，其中所述保护层的材料不同于所述第二衬底的材料及所述第一包封材料的材料。
2.根据权利要求1所述的半导体结构，其中所述第一衬底以及所述第二衬底是硅衬底。
3.根据权利要求1所述的半导体结构，其中所述保护层的所述材料包含氧化硅、氮化硅或它们的组合。
4.根据权利要求1所述的半导体结构，其中所述保护层直接接触所述第一衬底。
5.根据权利要求1所述的半导体结构，还包括包封所述第一管芯以及所述第二管芯的第二包封材料，其中所述第一包封材料设置在所述第二包封材料以及所述保护层之间。
6.一种半导体结构，包括：
第一管芯，包括第一衬底及设置在其上的第一焊盘，所述第一焊盘包括内部分以及高于所述内部分且环绕所述内部分的外部分；
第二管芯，包括第二衬底及设置在其上的凸块，其中所述凸块结合所述内部分以及被所述外部分环绕；
保护层，包覆所述第一衬底的侧壁及与所述侧壁连接的所述第一衬底的下表面，且不延伸至所述第二管芯的侧壁上；以及
介电材料，设置在所述第一衬底以及所述第二衬底之间以包封所述第一焊盘以及所述凸块。
7.根据权利要求6所述的半导体结构，其中所述保护层直接接触所述第一衬底。
8.根据权利要求6所述的半导体结构，其中所述保护层的材料不同于所述第二衬底的材料。
9.根据权利要求6所述的半导体结构，其中所述保护层的上表面实质上齐平于所述第一衬底以及所述介电材料的界面。
10.根据权利要求6所述的半导体结构，其中所述介电材料设置在所述第一焊盘的所述外部分以及所述凸块之间。
11.根据权利要求6所述的半导体结构，还包括设置在所述第二衬底以及所述凸块之间的第二焊盘。
12.根据权利要求6所述的半导体结构，其中所述凸块直接接触所述第一焊盘的所述内部分。
13.一种半导体结构，包括：
第一管芯，包括第一衬底；
第二管芯，经由所述第二管芯的下表面结合至所述第一管芯的上表面且包括第二衬底；
保护层，设置在所述第一衬底的侧壁上；
第一包封材料，包括模塑化合物，包封所述第一管芯以及所述保护层且与所述第二管芯的所述下表面接触，其中所述保护层的材料不同于所述第一包封材料的材料；
重布线路结构，其中所述第一管芯设置在所述重布线路结构与所述第二管芯之间；以及
多个导电柱，设置在所述第一包封材料中且位于所述重布线路结构与所述第二管芯之间，且电连接到所述重布线路结构与所述第二管芯，其中所述第一管芯、所述保护层以及所述导电柱的上表面实质上齐平且所述第一管芯、所述保护层以及所述导电柱的下表面实质上齐平。
14.根据权利要求13所述的半导体结构，其中所述保护层直接接触所述第一衬底。
15.根据权利要求13所述的半导体结构，其中所述保护层的所述上表面与所述下表面实质上齐平于所述第一包封材料的上表面与下表面。
16.根据权利要求13所述的半导体结构，还包括第二包封材料，所述第二包封材料包封所述第一管芯以及所述第二管芯，其中所述第一包封材料设置于所述第二包封材料以及所述保护层之间。
17.根据权利要求16所述的半导体结构，其中所述保护层的所述上表面实质上齐平于所述第一包封材料以及所述第二包封材料的上表面。
18.根据权利要求13所述的半导体结构，其中所述第一包封材料直接接触所述第二管芯。
19.根据权利要求13所述的半导体结构，其中所述保护层的材料不同于所述第二衬底的材料。
20.一种形成半导体结构的方法，包括：
提供包括第一焊盘的第一衬底，所述第一焊盘包括凹陷；
形成保护层，以覆盖所述第一衬底的第一表面；
提供第二衬底，所述第二衬底包括第二焊盘及电连接到所述第二焊盘的凸块，其中所述保护层的材料不同于所述第二衬底的材料；
通过将所述凸块***到所述凹陷中以电连接到所述第一焊盘，使所述第一衬底通过与所述第一表面相对的第二表面与所述第二衬底进行结合，其中所述第一表面为所述第一衬底的上表面及下表面中的一者，所述第二表面为所述第一衬底的所述上表面及所述下表面中的另一者；以及
在由所述保护层保护所述第一衬底的所述第一表面的同时，通过刻蚀工艺来薄化所述第二衬底。
21.根据权利要求20所述的方法，其中所述刻蚀工艺是湿法刻蚀工艺。
22.根据权利要求20所述的方法，其中所述保护层是载体。
23.根据权利要求20所述的方法，其中所述保护层还形成在所述第一衬底的侧壁上。
24.根据权利要求20所述的方法，其中在所述结合步骤之后，所述方法还包括：在所述第一衬底与所述第二衬底之间形成介电材料以包封所述第一焊盘及所述第二焊盘。
25.根据权利要求20所述的方法，其中在对所述第一衬底与所述第二衬底进行结合之前形成所述保护层。
26.一种形成半导体结构的方法，包括：
提供第一管芯，其中所述第一管芯包括第一衬底；
在所述第一衬底的侧壁及第一表面上形成保护层；
提供晶片，其中所述晶片包括第二衬底及多个管芯区域，其中所述保护层的材料不同于所述第二衬底的材料；
将所述第一管芯的与所述第一表面相对的第二表面结合到所述晶片的所述多个管芯区域中的一者，以形成经结合结构，其中所述第一表面为所述第一衬底的上表面及下表面中的一者，所述第二表面为所述第一衬底的所述上表面及所述下表面中的另一者；
在由所述保护层保护所述第一衬底的同时，通过刻蚀工艺来薄化所述第二衬底；
切割所述经结合结构以形成经结合单元，其中所述经结合单元包括所述第一管芯及从所述晶片的所述多个管芯区域中的一者切割出的第二管芯；
将所述经结合单元放置到载体上；
形成包封材料以包封所述经结合单元；
对所述包封材料及所述经结合单元执行平坦化工艺；以及
将所述经结合单元从所述载体剥离。
27.根据权利要求26所述的方法，其中所述第二管芯设置在所述第一管芯与所述载体之间，且执行所述平坦化工艺包括移除所述经结合单元的所述第一衬底的所述表面上的所述保护层。
28.根据权利要求26所述的方法，其中所述保护层的材料包含包封材料。
29.根据权利要求26所述的方法，其中所述保护层包括第一层及位于所述第一层与所述第一管芯之间的第二层，且所述第一层的材料与所述第二层的材料不相同。
30.一种形成半导体结构的方法，包括：
结合第一管芯与第二管芯，所述第一管芯包括第一衬底且通过所述第一管芯的第一表面与所述第二管芯结合，所述第二管芯包括第二衬底；
在所述第一衬底的侧壁及第二表面上形成保护层，其中所述第一表面为所述第一衬底的上表面及下表面中的一者，所述第二表面为所述第一衬底的所述上表面及所述下表面中的另一者；
以第一包封材料包封所述第一管芯及所述保护层，其中所述第一包封材料包括模塑化合物，所述保护层的材料不同于所述第二衬底以及所述第一包封材料的材料；以及
在由所述保护层与所述第一包封材料保护所述第一衬底的同时，薄化所述第二衬底。
31.根据权利要求30所述的方法，其中所述第一衬底及所述第二衬底是硅衬底。
32.根据权利要求30所述的方法，其中所述保护层的所述材料包含氧化硅、氮化硅或它们的组合。
33.根据权利要求30所述的方法，其中所述保护层直接接触所述第一衬底。
34.根据权利要求30所述的方法，还包括形成包封所述第一管芯及所述第二管芯的第二包封材料，其中所述第一包封材料设置在所述第二包封材料与所述保护层之间。
35.根据权利要求30所述的方法还包括将所述第一管芯及所述第二管芯彼此结合的结构放置到载体上，以及在由所述保护层保护所述第一衬底的所述侧壁的同时，通过刻蚀工艺来薄化所述第二衬底，其中所述第一管芯设置于所述第二管芯与所述载体之间。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI765944B (zh) 2016-12-14 2022-06-01 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列（ｆｐｇａ）積體電路晶片組成之邏輯驅動器
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11309278B2 (en) * 2018-10-29 2022-04-19 Applied Materials, Inc. Methods for bonding substrates
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11031361B2 (en) * 2019-07-31 2021-06-08 Advanced Semiconductor Engineering, Inc. Semiconductor bonding structure and method of manufacturing the same
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11600562B2 (en) * 2020-10-21 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and method of manufacturing the same
US11908838B2 (en) * 2021-08-26 2024-02-20 Taiwan Semiconductor Manufacturing Company Limited Three-dimensional device structure including embedded integrated passive device and methods of making the same
CN116741787A (zh) * 2023-08-11 2023-09-12 中芯越州集成电路制造(绍兴)有限公司 半导体器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130328174A1 (en) * 2012-06-06 2013-12-12 International Business Machines Corporation Edge Protection of Bonded Wafers During Wafer Thinning
CN105374693A (zh) * 2014-08-22 2016-03-02 台湾积体电路制造股份有限公司 半导体封装件及其形成方法
CN105981160A (zh) * 2014-04-23 2016-09-28 索尼公司 半导体装置及其制造方法

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI272654B (en) * 2003-07-18 2007-02-01 Asia Pacific Microsystems Inc Method for keeping the precision of photolithography alignment after wafer bonding
US9231012B2 (en) * 2007-08-01 2016-01-05 Visera Technologies Company Limited Image sensor package
US8064224B2 (en) * 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
TWI573201B (zh) * 2008-07-18 2017-03-01 聯測總部私人有限公司 封裝結構性元件
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8426961B2 (en) * 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
KR101711048B1 (ko) * 2010-10-07 2017-03-02 삼성전자 주식회사 차폐막을 포함하는 반도체 장치 및 제조 방법
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8263435B2 (en) * 2010-10-28 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US8994048B2 (en) * 2010-12-09 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integration
KR101719636B1 (ko) * 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
KR101800440B1 (ko) * 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
TWI467526B (zh) * 2012-01-20 2015-01-01 Innocom Tech Shenzhen Co Ltd 觸控顯示裝置及其製造方法
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
KR20130123682A (ko) * 2012-05-03 2013-11-13 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9190380B2 (en) * 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
KR102190382B1 (ko) * 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
US8729714B1 (en) * 2012-12-31 2014-05-20 Intel Mobile Communications GmbH Flip-chip wafer level package and methods thereof
KR20140091950A (ko) * 2013-01-14 2014-07-23 삼성전자주식회사 반도체 장치의 제조 방법
US9299649B2 (en) * 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8993380B2 (en) * 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9224696B2 (en) * 2013-12-03 2015-12-29 United Microelectronics Corporation Integrated semiconductor device and method for fabricating the same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
JP2015176958A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置及びその製造方法
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9595496B2 (en) * 2014-11-07 2017-03-14 Qualcomm Incorporated Integrated device package comprising silicon bridge in an encapsulation layer
US9768134B2 (en) * 2015-01-29 2017-09-19 Micron Technology, Inc. Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects
KR101640341B1 (ko) * 2015-02-04 2016-07-15 앰코 테크놀로지 코리아 주식회사 반도체 패키지
CN104655334B (zh) * 2015-02-16 2017-05-03 迈尔森电子（天津）有限公司 Mems压力传感器及其形成方法
CN104634487B (zh) * 2015-02-16 2017-05-31 迈尔森电子（天津）有限公司 Mems压力传感器及其形成方法
US9583451B2 (en) * 2015-06-19 2017-02-28 International Business Machines Corporation Conductive pillar shaped for solder confinement
US10008439B2 (en) * 2015-07-09 2018-06-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Thin recon interposer package without TSV for fine input/output pitch fan-out
US9761533B2 (en) * 2015-10-16 2017-09-12 Xilinx, Inc. Interposer-less stack die interconnect
US10163856B2 (en) * 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
KR102508551B1 (ko) * 2015-12-11 2023-03-13 에스케이하이닉스 주식회사 웨이퍼 레벨 패키지 및 제조 방법
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US10170397B2 (en) * 2016-07-07 2019-01-01 Vanguard International Semiconductor Corporation Semiconductor devices, via structures and methods for forming the same
US10062654B2 (en) * 2016-07-20 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US10833052B2 (en) * 2016-10-06 2020-11-10 Micron Technology, Inc. Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods
CN108172551B (zh) * 2016-11-29 2022-04-29 Pep创新私人有限公司 芯片封装方法及封装结构
CN108217581B (zh) * 2017-01-20 2021-03-16 迈尔森电子（天津）有限公司 一种mems压电传感器及其制作方法
US10290611B2 (en) * 2017-07-27 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130328174A1 (en) * 2012-06-06 2013-12-12 International Business Machines Corporation Edge Protection of Bonded Wafers During Wafer Thinning
CN105981160A (zh) * 2014-04-23 2016-09-28 索尼公司 半导体装置及其制造方法
CN105374693A (zh) * 2014-08-22 2016-03-02 台湾积体电路制造股份有限公司 半导体封装件及其形成方法

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