CN110471876A - A kind of ultrahigh speed serial data channel system - Google Patents
A kind of ultrahigh speed serial data channel system Download PDFInfo
- Publication number
- CN110471876A CN110471876A CN201910543659.4A CN201910543659A CN110471876A CN 110471876 A CN110471876 A CN 110471876A CN 201910543659 A CN201910543659 A CN 201910543659A CN 110471876 A CN110471876 A CN 110471876A
- Authority
- CN
- China
- Prior art keywords
- encoder
- data
- serial
- decoder
- bit parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention proposes a kind of ultrahigh speed serial data channel systems may be implemented handling capacity extension by the way that two-way 8B/10B encoder is arranged in the first serial transceiver；By the way that quick clock module is arranged, it can realize that 20B data with the output of 10B data, are avoided using higher clock frequency and timing condition by high-low-position；By the way that clock module, the first register, the second register and third register are arranged in the second serial transceiver, it can be exported simultaneously by the first 8B/10B decoder of clock module and the 2nd 8B/10B decoder, it can guarantee the accurate of 16B output data, the first 8B/10B decoder and the 2nd 8B/10B decoder have time enough decoding simultaneously, sequence problem will not be generated, while data throughput can be improved.
Description
Technical field
The present invention relates to field of channel coding more particularly to a kind of ultrahigh speed serial data channel systems.
Background technique
With advancing at utmost speed for information technology, the especially development of high-speed transmission interface technology, traditional parallel interface skill
Art is due to encountering the bottleneck in speed, therefore, it is difficult to further develop instead High Speed Serial technology, currently, mainly
Serial link system for fiber optic communication is gradually replacing traditional parallel link system and becomes high speed interface skill
The mainstream of art, and technology of Low Voltage Differential Signaling LVDS is widely used in various high speed serialization occasions.Currently, by serially leading to
Road transceiver realizes high-speed serial communication, and in communication process, serial-port transceiver needs encode the information of transmission,
By increasing redundancy symbol in initial data, signal integrity on transmission channel is improved, this method is by sacrificing bandwidth
Or transmission rate exchanges reliability for, therefore, when guaranteeing the reliability of communication, just not can guarantee its bandwidth or transmission speed
A kind of rate, therefore, to solve the above problems, the present invention proposes ultrahigh speed serial data channel system, it is ensured that data transmission
Reliability and bandwidth balancing.
Summary of the invention
In view of this, the invention proposes the present invention to propose a kind of ultrahigh speed serial data channel system, it is ensured that number
According to transmission reliability and bandwidth balancing.
The technical scheme of the present invention is realized as follows: the present invention provides a kind of ultrahigh speed serial data channel system,
It includes host, multipath high-speed differential serial lane and multiple DSDDR memories, and high-speed differential serial channel includes first serial
Transceiver and the second serial transceiver, and the input with the input terminal of the first serial transceiver and the second serial transceiver respectively
Hold the RAM memory being electrically connected；
Host sends parallel data, and accesses one, several or all DSDDR memories；
RAM memory storage coding and decoded corresponding relationship, provide known encoding and decoding relationship；
The parallel data that first serial transceiver sends host, and according to the progress of encoding and decoding relationship in RAM memory
Coding, output difference signal, and differential signal is exported to the second serial transceiver；
Second serial transceiver receives the differential signal of the first serial transceiver output, and solves according to compiling in RAM memory
Code relationship is decoded；
Host is electrically connected with the first serial transceiver input terminal in multi-path serial channel respectively by parallel bus, multichannel
The output end of the first serial transceiver passes through the in difference write bus and multi-path serial channel second serial transmitting-receiving in serial-port
The input terminal of device, which corresponds, to be electrically connected, in multi-path serial channel the output end of the second serial transceiver by universal serial bus with
The input terminal of multiple DSDDR memories, which corresponds, to be electrically connected.
On the basis of above technical scheme, it is preferred that the first serial transceiver includes receiver, the first 8B/10B coding
Device, the 2nd 8B/10B encoder, quick clock module, the first CRC check, the second CRC check, serializer and difference output buffering
Device；
16 data that receiver receiving host is sent, and be divided into 16 data and be divided into most-significant byte data and least-significant byte data,
Most-significant byte data are sent into the first 8B/10B encoder and the first CRC check, least-significant byte data are sent to the 2nd 8B/10B encoder
With the second CRC check, the first CRC check carries out check value calculating to 8 bit parallel datas, and sends check value to the first 8B/
10B encoder, the first 8B/10B encoder is according to encoding and decoding relationship in RAM memory to 8 bit parallel datas of input and verification
Value is successively encoded, increase redundant code, and export 10 bit parallel datas to quick clock module, the second CRC check to 8 simultaneously
Row data carry out check value calculating, and send check value to the 2nd 8B/10B encoder, and the 2nd 8B/10B encoder is according to RAM
Encoding and decoding relationship successively encodes 8 bit parallel datas and check value of input in memory, increases redundant code, and export 10
Bit parallel data is to quick clock module, and quick clock module is to the first 8B/10B encoder and the 2nd 8B/10B encoder output
10 bit parallel datas carry out the quick gatings of data, make 10 bit parallel data of output data, and by 10 bit parallel datas into
To serializer, 10 bit parallel datas of 8B/10B encoder output are converted to serial data stream, then passed through by serializer for output
Differential output buffer is single-ended signal difference output.
It is further preferred that the first 8B/10B encoder includes character judgement module, control character encoder, numerical character
Encoder and selector；
Numerical character encoder includes 3B/4B encoder, polarity control module and 5B/6B encoder；
Character judgement module carries out character judgement to 8 bit parallel datas of input, if 8 bit parallel datas belong to control word
Symbol collection, then be transmitted to control character encoder for 8 bit parallel datas and encode, 10 parallel-by-bit number of control character encoder output
According to；If 8 bit parallel datas belong to numeric character set, 8 bit parallel datas are transmitted in numerical character encoder, numeric word
Encoder is accorded with according to encoding and decoding relationship in RAM memory, 8 bit parallel datas are divided into Gao Sanwei data and low five-digit number evidence, and
Gao Sanwei data are transmitted to 3B/4B encoder, it is low four volumes that 3B/4B encoder inquires format in RAM memory
Code value, by low five-digit number according to 5B/6B encoder is transmitted to, 5B/6B encoder inquires high six bit format in RAM memory
Encoded radio, selector selection output 3B/4B encoder and 5B/6B encoder output as a result, polarity control module to 3B/4B compile
The encoded radio that code device and 5B/6B encoder obtain carries out polarity judgement.
It is further preferred that the structure of the first 8B/10B encoder and the 2nd 8B/10B encoder is identical with principle.
It is further preferred that serializer is high speed time division multiple signals selector；
The every 2.5ns of high speed time division multiple signals selector generates a gating signal, the first 8B/10B encoder or the
10 bit parallel datas of two 8B/10B encoder outputs are sequentially output to obtain serial signal from a high position to low level.
It is further preferred that the second serial transceiver includes differential input buffer, deserializer, the first 8B/10B decoding
Device, the 2nd 8B/10B decoder, the first register, the second register, third register, clock module, third CRC check,
Four CRC checks and transmitter；
Differential signal is converted into single-ended signal by differential input buffer, and by single-ended signal transmission to deserializer, is unstringed
Single-ended signal is converted into 10 bit parallel datas by device, and 10 bit parallel datas are respectively fed to the first 8B/10B decoder and second
8B/10B decoder, the first 8B/10B decoder are decoded the encoded signal of the first 8B/10B encoder output, restore
8 original bit parallel datas, and by concatenated first register and the output of the second register, the 2nd 8B/10B decoder is to the
The encoded signal of two 8B/10B encoder outputs is decoded, and restores 8 original bit parallel datas, and pass through third register
Output, clock module provide the first 8B/10B decoder, the 2nd 8B/10B decoder, the first register, the second register and the
The control clock of the work clock of three registers, third register is identical as the work clock of the second register, third CRC check
It detects with the presence or absence of error code in 8 bit parallel datas that the first 8B/10B decoder solves, the 4th CRC check detects the 2nd 8B/10B
It whether there is error code in 8 bit parallel datas that decoder solves, transmitter solves the first 8B/10B decoder and the 2nd 8B/10B
8 bit parallel datas that code device solves are merged into 16 bit parallel datas, and parallel series is sent.
It is further preferred that the first 8B/10B decoder includes code stream detection module, it is electrical with code stream detection module respectively
Control character decoder module, 3B/4B decoder module and the 5B/6B decoder module of connection, and respectively with 3B/4B decoder module and
The polarity checking circuit that 5B/6B decoder module is electrically connected；
Code stream detection module receives differential output buffer output signal, and detects whether as valid data, if data are
Invalid data then returns, if data are valid data, then judges that data belong to control character collection or data character set, if number
According to being control character, then data are delivered to control character decoder module, control character decoder module is inquired in RAM memory
Corresponding original 8 digit out；If data character, the code stream detection module data are divided into two code characters of 4B and 6B, 3B/4B decoding
Module and 5B/6B decoder module inquire original 3B and 5B code character respectively in RAM memory, then to be reassembled into 8B original
Data.
It is further preferred that the structure of the first 8B/10B decoder and the 2nd 8B/10B decoder is identical with principle.
It is further preferred that deserializer is serial shift register；
The serial signal of serializer output enters serial shift register, and serial shift register is posted every 2.5ns displacement
Storage moves right one, and every ten clock cycle export 10 bit parallel datas.
A kind of ultrahigh speed serial data channel system of the invention has the advantages that compared with the existing technology
(1) in coding, increase by 2 redundancy bits symbols in initial data, the complete of signal on transmission channel can be improved
Whole property；Using 8B/10B decoding technique, error code can be examined, guarantees the reliability of signal；Using multiplexing technique in single channel
On the basis of serial-port, the high-speed communication array of multichannel is formed, improves the transmission broadband of system, and multichannel number may be implemented
According to sending and receiving simultaneously, improve the handling capacity of data, and compensate for cause because increasing redundant code width reduce lack
Point realizes data transmission credibility and wideband balance；
(2) by the way that two-way 8B/10B encoder is arranged in the first serial transceiver, handling capacity extension may be implemented；Pass through
Quick clock module is set, can realize that 20B data with the output of 10B data, are avoided using higher clock frequency by high-low-position
Rate and timing condition；
(3) it is deposited by the way that clock module, the first register, the second register and third are arranged in the second serial transceiver
Device can be exported simultaneously by the first 8B/10B decoder of clock module and the 2nd 8B/10B decoder, it is ensured that 16B output
Data it is accurate, while the first 8B/10B decoder and the 2nd 8B/10B decoder have time enough decoding, will not generate
Sequence problem, while data throughput can be improved.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of structure chart of ultrahigh speed serial data channel system of the present invention；
Fig. 2 is the structure chart of the first serial transceiver in a kind of ultrahigh speed serial data channel system of the present invention；
Fig. 3 is the structure chart of the first 8B/10B encoder in Fig. 2；
Fig. 4 is the clock frequency and phase corresponding relationship of quick clock module in Fig. 2；
Fig. 5 is the structure chart of the second serial transceiver in a kind of ultrahigh speed serial data channel system of the present invention；
Fig. 6 is the structure chart of the first 8B/10B decoder in Fig. 5；
Fig. 7 is the work clock figure of the first 8B/10B decoder and the 2nd 8B/10B decoder in Fig. 5.
Specific embodiment
Below in conjunction with embodiment of the present invention, the technical solution in embodiment of the present invention is carried out clearly and completely
Description, it is clear that described embodiment is only some embodiments of the invention, rather than whole embodiments.Base
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts all
Other embodiments shall fall within the protection scope of the present invention.
As shown in Figure 1, a kind of ultrahigh speed serial data channel system comprising host, multipath high-speed differential serial lane
With multiple DSDDR memories, high-speed differential serial channel includes the first serial transceiver and the second serial transceiver, and difference
The RAM memory being electrically connected with the first serial transceiver and the second serial transceiver input terminal.Wherein, host is by simultaneously
Row bus is electrically connected with the first serial transceiver input terminal in multi-path serial channel respectively, and first is serial in multi-path serial channel
The output end of transceiver is corresponded by the input terminal of the second serial transceiver in difference write bus and multi-path serial channel
It is electrically connected, the output end of the second serial transceiver passes through universal serial bus and multiple DSDDR memories in multi-path serial channel
Input terminal, which corresponds, to be electrically connected.
Host sends parallel data, and accesses one, several or all DSDDR memories；
RAM memory storage coding and decoded corresponding relationship, provide known encoding and decoding relationship.When known input data
And corresponding output logic, so that it may be searched using look-up table corresponding, in the present embodiment, it is defeated that address be made with incoming level
Enter, all output logical consequences can be written in RAM by corresponding address, and therefore, next each input signal is as one
A address is tabled look-up, and after finding address, the corresponding content in address is exported, completion is once tabled look-up.
The parallel data that first serial transceiver sends host, and according to the progress of encoding and decoding relationship in RAM memory
Coding, output difference signal, and differential signal is exported to the second serial transceiver；In the present embodiment, as shown in Fig. 2,
One serial transceiver includes receiver, the first 8B/10B encoder, the 2nd 8B/10B encoder, quick clock module, the first CRC
Verification, the second CRC check, serializer and differential output buffer.In the present embodiment, 16 of receiver receiving host transmission
Data, and be divided into 16 data and be divided into most-significant byte data and least-significant byte data, by most-significant byte data be sent into the first 8B/10B encoder and
First CRC check send least-significant byte data to the 2nd 8B/10B encoder and the second CRC check, and the first CRC check is to 8 parallel-by-bits
Data carry out check value calculating, and send check value to the first 8B/10B encoder, and the first 8B/10B encoder is deposited according to RAM
Encoding and decoding relationship successively encodes 8 bit parallel datas and check value of input in reservoir, increases 2bit redundant code, and export
For 10 bit parallel datas to quick clock module, the second CRC check carries out check value calculating to 8 bit parallel datas, and by check value
Send the 2nd 8B/10B encoder to, the 2nd 8B/10B encoder according to encoding and decoding relationship in RAM memory to 8 of input simultaneously
Row data and check value are successively encoded, and redundant code is increased, and export 10 bit parallel datas to quick clock module, at one
In the period of clock frequency lclk, the first 8B/10B encoder and the total 20B data of the 2nd 8B/10B encoder output to it is quick when
In clock module, due to output 20B data below and when turning string, need higher clock frequency and timing condition, therefore fast
Fast clock module had better export 10B data, therefore, to solve the above problems, present embodiments providing a kind of quickly gating
Method, wherein the clock frequency of quick clock module and phase corresponding relationship as shown in figure 4, quick clock module clock frequency
When rate lclk is low level, phase fclk controls quick clock module by rising edge and exports 10 bit parallel datas；When quick
When clock frequency lclk is high level, phase fclk controls quick clock module by rising edge and exports 10 simultaneously clock module
Row data, by above-mentioned principle, quick clock module to the first 8B/10B encoder and the 2nd 8B/10B encoder output 10
Bit parallel data carries out the quick gating of data, makes 10 bit parallel data of output data, and by 10 bit parallel datas into output
To serializer, in the present embodiment, serializer is high speed time division multiple signals selector, and every 2.5ns generates a gating signal,
10 bit parallel datas that quick clock module exports are sequentially output to obtain serial signal from a high position to low level, then pass through difference
Output buffer is single-ended signal difference output.Due to differential signal polarity equal in magnitude on the contrary, and noise is equal in magnitude but pole
Property it is identical, on differential channel common-mode noise generate coupling effect can cancel out each other, differential signal will not be had an impact,
And the amplitude of differential signal is twice of single-ended signal, and signal-to-noise ratio is high, to the anti-noise ability and strong antijamming capability of channel, and
And the transmission speed of differential signal reaches as high as 1Gbps, and the highest transmission speed of single-ended signal is 200Mbps, therefore, this
In embodiment, pass through differential signal transmission in high-speed differential serial channel.
In the present embodiment, since the structure of the first 8B/10B encoder and the 2nd 8B/10B encoder is identical with principle,
Therefore, the first 8B/10B encoder is introduced at this.In the present embodiment, as shown in figure 3, the first 8B/10B encoder includes word
Accord with judgment module, control character encoder, numerical character encoder and selector, wherein numerical character encoder includes 3B/4B
Encoder, polarity control module and 5B/6B encoder.The working principle of first 8B/10B encoder are as follows: character judgement module pair
8 bit parallel datas of input carry out character judgement, if 8 bit parallel datas belong to control character collection, in the present embodiment with K code
Represent control character, then 8 bit parallel datas be transmitted to control character encoder and encoded, control character encoder according to
Encoding and decoding relationship exports 10 bit parallel datas in RAM memory；If 8 bit parallel datas belong to numeric character set, in this implementation
Numerical character is represented with D code in example, then 8 bit parallel datas is transmitted in numerical character encoder, 8 bit parallel datas is divided into
Gao Sanwei data and low five-digit number evidence, and Gao Sanwei data are transmitted to 3B/4B encoder, low five-digit number evidence is transmitted to 5B/
6B encoder, 3B/4B encoder is using 3B input data as the input address of the look-up table in RAM memory, with 4B data work
It is encoded accordingly for 3B, and exports low four encoded radios；5B/6B encoder is using 5B as the look-up table in RAM memory
Input address using 6B as the output data of look-up table, and exports the encoded radio of Gao Liuwei, and selector selection output 3B/4B is compiled
Code device and 5B/6B encoder output as a result, the coding that polarity control module obtains 3B/4B encoder and 5B/6B encoder
Value carries out polarity judgement.
Second serial transceiver receives the differential signal of the first serial transceiver output, and solves according to compiling in RAM memory
Code relationship is decoded；In the present embodiment, as shown in figure 5, the second serial transceiver includes differential input buffer, unstrings
Device, the first 8B/10B decoder, the 2nd 8B/10B decoder, the first register, the second register, third register, clock mould
Block, third CRC check, the 4th CRC check and transmitter.The working principle of second serial transceiver is: differential input buffer
Differential signal is converted into single-ended signal, and by single-ended signal transmission to deserializer, in the present embodiment, deserializer is serial moves
Bit register, the serial signal of serializer output enter serial shift register, and serial shift register is posted every 2.5ns displacement
Storage moves right one, and every ten clock cycle export 10 bit parallel datas, and 10 bit parallel datas are respectively fed to
First 8B/10B decoder and the 2nd 8B/10B decoder, volume of the first 8B/10B decoder to the first 8B/10B encoder output
Code signal is decoded, and restores original most-significant byte parallel data, and the 2nd 8B/10B decoder is defeated to the 2nd 8B/10B encoder
Encoded signal out is decoded, and restores original least-significant byte parallel data.The first 8B/10B decoder of clock module offer,
2nd 8B/10B decoder, the first register, the second register and third register work clock.Due to quick clock module
The data of output are exported after gating according to the high-low-position of clock frequency, therefore, as shown in fig. 7, the first 8B/10B decoder
When acquiring data, its sampling period differs half period with the 2nd 8B/10B decoder, in the present embodiment, if the first 8B/
The sampling clock of 10B decoder is CLK1, and the sampling clock of the 2nd 8B/10B decoder is CLK2, in order to solve the first 8B/10B
Code device and the 2nd 8B/10B decoder export simultaneously, therefore, have connected two-stage deposit in the output end of the first 8B/10B decoder
Device, wherein the clock of the first register is CLK1, and the clock of the second register is CLK2, and the clock of third register is CLK2,
Start to acquire data when the first 8B/10B decoder is in CLK1 arrival, and is taken from RAM according to the encoding and decoding relationship that RAM is stored
Corresponding decode logic out restores original most-significant byte parallel data, and original most-significant byte parallel data is stored in first
In register, when CLK1 arrives, original most-significant byte parallel data is sent to the second register by the first register, works as CLK2
When arrival, the 2nd 8B/10B decoder starts to acquire data, and correspondence is taken out from RAM according to the encoding and decoding relationship that RAM is stored
Decode logic, restore original least-significant byte parallel data, and original least-significant byte parallel data is stored in third register
In, meanwhile, the second register sends original most-significant byte parallel data, third register by original least-significant byte data simultaneously
Row data are sent, and can guarantee the accurate of 16B output data by the output of this structure, while the first 8B/10B is decoded
Device and the 2nd 8B/10B decoder have time enough decoding, will not generate sequence problem, while data throughput can be improved
Rate.In addition, third CRC check, which detects, whether there is error code in 8 bit parallel datas that the first 8B/10B decoder solves, the 4th
CRC check detects in 8 bit parallel datas that solve of the 2nd 8B/10B decoder with the presence or absence of error code, and transmitter is by the first 8B/10B
8 bit parallel datas that decoder and the 2nd 8B/10B decoder solve are merged into 16 bit parallel datas, and parallel series is sent.
In the present embodiment, since the structure of the first 8B/10B decoder and the 2nd 8B/10B decoder is identical with principle,
Therefore, the first 8B/10B decoder is introduced at this.In the present embodiment, as shown in fig. 6, the first 8B/10B decoder includes code
Detection module is flowed, control character decoder module, 3B/4B decoder module and the 5B/6B being electrically connected respectively with code stream detection module
Decoder module, and the polarity checking circuit being electrically connected respectively with 3B/4B decoder module and 5B/6B decoder module；Specifically
Working principle are as follows: code stream detection module receives differential output buffer output signal, and detects whether as valid data, if data
It for invalid data, then returns, if data are valid data, then judges that data belong to control character collection or data character set, if
Data are control characters, then data are delivered to control character decoder module, and control character decoder module is looked into RAM memory
Ask out corresponding original 8 digit；If data character, the code stream detection module data are divided into two code characters of 4B and 6B, 3B/4B solution
Code module and 5B/6B decoder module inquire original 3B and 5B code character respectively in RAM memory, then are reassembled into 8B original
Beginning data.
The foregoing is merely better embodiments of the invention, are not intended to limit the invention, all of the invention
Within spirit and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of ultrahigh speed serial data channel system comprising host, multipath high-speed differential serial lane and multiple DSDDR are deposited
Reservoir, it is characterised in that: the high-speed differential serial channel includes the first serial transceiver and the second serial transceiver, Yi Jifen
The RAM memory not being electrically connected with the input terminal of the input terminal of the first serial transceiver and the second serial transceiver；
The host sends parallel data, and accesses one, several or all DSDDR memories；
The RAM memory storage coding and decoded corresponding relationship, provide known encoding and decoding relationship；
The parallel data that first serial transceiver sends host, and according to the progress of encoding and decoding relationship in RAM memory
Coding, output difference signal, and differential signal is exported to the second serial transceiver；
Second serial transceiver receives the differential signal of the first serial transceiver output, and solves according to compiling in RAM memory
Code relationship is decoded；
The host is electrically connected with the first serial transceiver input terminal in multi-path serial channel respectively by parallel bus, multichannel
The output end of the first serial transceiver passes through the in difference write bus and multi-path serial channel second serial transmitting-receiving in serial-port
The input terminal of device, which corresponds, to be electrically connected, in multi-path serial channel the output end of the second serial transceiver by universal serial bus with
The input terminal of multiple DSDDR memories, which corresponds, to be electrically connected.
2. a kind of ultrahigh speed serial data channel system as described in claim 1, it is characterised in that: the described first serial transmitting-receiving
Device includes receiver, the first 8B/10B encoder, the 2nd 8B/10B encoder, quick clock module, the first CRC check, second
CRC check, serializer and differential output buffer；
16 data that the receiver receiving host is sent, and be divided into 16 data and be divided into most-significant byte data and least-significant byte data,
Most-significant byte data are sent into the first 8B/10B encoder and the first CRC check, least-significant byte data are sent to the 2nd 8B/10B encoder
With the second CRC check, the first CRC check carries out check value calculating to 8 bit parallel datas, and sends check value to the first 8B/
10B encoder, the first 8B/10B encoder is according to encoding and decoding relationship in RAM memory to 8 bit parallel datas of input and verification
Value is successively encoded, increase redundant code, and export 10 bit parallel datas to quick clock module, the second CRC check to 8 simultaneously
Row data carry out check value calculating, and send check value to the 2nd 8B/10B encoder, and the 2nd 8B/10B encoder is according to RAM
Encoding and decoding relationship successively encodes 8 bit parallel datas and check value of input in memory, increases redundant code, and export 10
Bit parallel data is to quick clock module, and quick clock module is to the first 8B/10B encoder and the 2nd 8B/10B encoder output
10 bit parallel datas carry out the quick gatings of data, make 10 bit parallel data of output data, and by 10 bit parallel datas into
To serializer, 10 bit parallel datas of 8B/10B encoder output are converted to serial data stream, then passed through by serializer for output
Differential output buffer is single-ended signal difference output.
3. a kind of ultrahigh speed serial data channel system as claimed in claim 2, it is characterised in that: the first 8B/10B is compiled
Code device includes character judgement module, control character encoder, numerical character encoder and selector；
The numerical character encoder includes 3B/4B encoder, polarity control module and 5B/6B encoder；
The character judgement module carries out character judgement to 8 bit parallel datas of input, if 8 bit parallel datas belong to control word
Symbol collection, then be transmitted to control character encoder for 8 bit parallel datas and encode, 10 parallel-by-bit number of control character encoder output
According to；If 8 bit parallel datas belong to numeric character set, 8 bit parallel datas are transmitted in numerical character encoder, numeric word
Encoder is accorded with according to encoding and decoding relationship in RAM memory, 8 bit parallel datas are divided into Gao Sanwei data and low five-digit number evidence, and
Gao Sanwei data are transmitted to 3B/4B encoder, it is low four volumes that 3B/4B encoder inquires format in RAM memory
Code value, by low five-digit number according to 5B/6B encoder is transmitted to, 5B/6B encoder inquires high six bit format in RAM memory
Encoded radio, selector selection output 3B/4B encoder and 5B/6B encoder output as a result, polarity control module to 3B/4B compile
The encoded radio that code device and 5B/6B encoder obtain carries out polarity judgement.
4. a kind of ultrahigh speed serial data channel system as claimed in claim 3, it is characterised in that: the first 8B/10B is compiled
The structure of code device and the 2nd 8B/10B encoder is identical with principle.
5. a kind of ultrahigh speed serial data channel system as claimed in claim 2, it is characterised in that: the serializer is high speed
Time-division multiplex signal selector；
The every 2.5ns of the high speed time division multiple signals selector generates a gating signal, the first 8B/10B encoder or the
10 bit parallel datas of two 8B/10B encoder outputs are sequentially output to obtain serial signal from a high position to low level.
6. a kind of ultrahigh speed serial data channel system as claimed in claim 4, it is characterised in that: the described second serial transmitting-receiving
Device includes differential input buffer, deserializer, the first 8B/10B decoder, the 2nd 8B/10B decoder, the first register, second
Register, third register, clock module, third CRC check, the 4th CRC check and transmitter；
Differential signal is converted into single-ended signal by the differential input buffer, and by single-ended signal transmission to deserializer, is unstringed
Single-ended signal is converted into 10 bit parallel datas by device, and 10 bit parallel datas are respectively fed to the first 8B/10B decoder and second
8B/10B decoder, the first 8B/10B decoder are decoded the encoded signal of the first 8B/10B encoder output, restore
8 original bit parallel datas, and by concatenated first register and the output of the second register, the 2nd 8B/10B decoder is to the
The encoded signal of two 8B/10B encoder outputs is decoded, and restores 8 original bit parallel datas, and pass through third register
Output, clock module provide the first 8B/10B decoder, the 2nd 8B/10B decoder, the first register, the second register and the
The control clock of the work clock of three registers, third register is identical as the work clock of the second register, third CRC check
It detects with the presence or absence of error code in 8 bit parallel datas that the first 8B/10B decoder solves, the 4th CRC check detects the 2nd 8B/10B
It whether there is error code in 8 bit parallel datas that decoder solves, transmitter solves the first 8B/10B decoder and the 2nd 8B/10B
8 bit parallel datas that code device solves are merged into 16 bit parallel datas, and parallel series is sent.
7. a kind of ultrahigh speed serial data channel system as claimed in claim 6, it is characterised in that: the first 8B/10B solution
Code device includes code stream detection module, and control character decoder module, the 3B/4B being electrically connected respectively with code stream detection module decode mould
Block and 5B/6B decoder module, and the polarity being electrically connected respectively with 3B/4B decoder module and 5B/6B decoder module verify electricity
Road；
The code stream detection module receives differential output buffer output signal, and detects whether as valid data, if data are
Invalid data then returns, if data are valid data, then judges that data belong to control character collection or data character set, if number
According to being control character, then data are delivered to control character decoder module, control character decoder module is inquired in RAM memory
Corresponding original 8 digit out；If data character, the code stream detection module data are divided into two code characters of 4B and 6B, 3B/4B decoding
Module and 5B/6B decoder module inquire original 3B and 5B code character respectively in RAM memory, then to be reassembled into 8B original
Data.
8. a kind of ultrahigh speed serial data channel system as claimed in claim 7, it is characterised in that: the first 8B/10B solution
The structure of code device and the 2nd 8B/10B decoder is identical with principle.
9. a kind of ultrahigh speed serial data channel system as claimed in claim 6, it is characterised in that: the deserializer is serial
Shift register；
The serial signal of the serializer output enters serial shift register, and serial shift register is posted every 2.5ns displacement
Storage moves right one, and every ten clock cycle export 10 bit parallel datas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910543659.4A CN110471876A (en) | 2019-06-21 | 2019-06-21 | A kind of ultrahigh speed serial data channel system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910543659.4A CN110471876A (en) | 2019-06-21 | 2019-06-21 | A kind of ultrahigh speed serial data channel system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110471876A true CN110471876A (en) | 2019-11-19 |
Family
ID=68506963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910543659.4A Pending CN110471876A (en) | 2019-06-21 | 2019-06-21 | A kind of ultrahigh speed serial data channel system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110471876A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111342835A (en) * | 2020-02-27 | 2020-06-26 | 成都泰格微电子研究所有限责任公司 | SERDES module for JESD204B interface |
| CN112383384B (en) * | 2021-01-13 | 2021-04-06 | 成都铭科思微电子技术有限责任公司 | Large-size chip based on-chip serial data communication and communication method thereof |
| CN112988650A (en) * | 2021-05-12 | 2021-06-18 | 网络通信与安全紫金山实验室 | Communication method, device, system and storage medium |
| CN113346978A (en) * | 2021-05-24 | 2021-09-03 | 北京计算机技术及应用研究所 | Asynchronous serial LVDS high-speed stable transmission system and method |
| CN113810071A (en) * | 2021-09-13 | 2021-12-17 | 上海星秒光电科技有限公司 | Self-adaptive line sequence adjusting method, device, equipment, system and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101867452A (en) * | 2010-06-10 | 2010-10-20 | 国网电力科学研究院 | Communication method of serial real-time bus special in electricity |
| CN102340316A (en) * | 2011-09-07 | 2012-02-01 | 上海大学 | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer |
-
2019
- 2019-06-21 CN CN201910543659.4A patent/CN110471876A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101867452A (en) * | 2010-06-10 | 2010-10-20 | 国网电力科学研究院 | Communication method of serial real-time bus special in electricity |
| CN102340316A (en) * | 2011-09-07 | 2012-02-01 | 上海大学 | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer |
Non-Patent Citations (2)
| Title |
|---|
| 宋娟: "基于串行通道的高速通信方法设计与实现", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
| 王伟涛: "8b/10b架构SerDes芯片的设计与实现", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111342835A (en) * | 2020-02-27 | 2020-06-26 | 成都泰格微电子研究所有限责任公司 | SERDES module for JESD204B interface |
| CN112383384B (en) * | 2021-01-13 | 2021-04-06 | 成都铭科思微电子技术有限责任公司 | Large-size chip based on-chip serial data communication and communication method thereof |
| CN112988650A (en) * | 2021-05-12 | 2021-06-18 | 网络通信与安全紫金山实验室 | Communication method, device, system and storage medium |
| CN112988650B (en) * | 2021-05-12 | 2021-08-03 | 网络通信与安全紫金山实验室 | Communication method, device, system and storage medium |
| CN113346978A (en) * | 2021-05-24 | 2021-09-03 | 北京计算机技术及应用研究所 | Asynchronous serial LVDS high-speed stable transmission system and method |
| CN113810071A (en) * | 2021-09-13 | 2021-12-17 | 上海星秒光电科技有限公司 | Self-adaptive line sequence adjusting method, device, equipment, system and storage medium |
| CN113810071B (en) * | 2021-09-13 | 2022-07-22 | 上海星秒光电科技有限公司 | Self-adaptive line sequence adjusting method, device, equipment, system and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110471876A (en) | A kind of ultrahigh speed serial data channel system | |
| US6839862B2 (en) | Parallel data communication having skew intolerant data groups | |
| US9838234B2 (en) | Orthogonal differential vector signaling codes with embedded clock | |
| US6920576B2 (en) | Parallel data communication having multiple sync codes | |
| US6425107B1 (en) | Data encoder/decoder for a high speed serial link | |
| US7085950B2 (en) | Parallel data communication realignment of data sent in multiple groups | |
| CN101702639B (en) | Check value calculation method and device of cyclic redundancy check | |
| US20110016374A1 (en) | Serial interface devices, systems and methods | |
| CN102523436A (en) | Transmission terminal, receiving terminal, multi-channel video optical fiber transmission system and multi-channel video optical fiber transmission method | |
| US20230327806A1 (en) | Soft FEC With Parity Check | |
| US9979566B2 (en) | Hybrid forward error correction and replay technique for low latency | |
| US20240063940A1 (en) | Soft fec with parity check | |
| CN104333388A (en) | Serial communication protocol controller, character re-aligning circuit and 8b/10b decoder | |
| CN112286853B (en) | FPGA system supporting multiple protocols and data processing method | |
| CN101001199A (en) | Data processing method of high speed multidigit parallel data bus | |
| CN104380273A (en) | Adaptive offset synchronization of data based on ring buffers | |
| CN101442380B (en) | Method and apparatus for testing error rate based on high speed serial interface encoded mode | |
| US11139830B2 (en) | Bit inversion for data transmission | |
| US20110142165A1 (en) | Flexible self-adaptive differential system to improve transmission efficiency | |
| RU2408985C2 (en) | Error control device in digital transmission systems on basis of atm technology | |
| CN110213019A (en) | A kind of PCM signal coded system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191119 |
|
| RJ01 | Rejection of invention patent application after publication |