CN112988650B

CN112988650B - Communication method, device, system and storage medium

Info

Publication number: CN112988650B
Application number: CN202110514205.1A
Authority: CN
Inventors: 由镭; 李欣; 程本涛; 赵涤燹; 尤肖虎
Original assignee: China Aviation Technology International Holding Co ltd; Southeast University; Network Communication and Security Zijinshan Laboratory
Current assignee: China Aviation Technology International Holding Co ltd; Southeast University; Network Communication and Security Zijinshan Laboratory
Priority date: 2021-05-12
Filing date: 2021-05-12
Publication date: 2021-08-03
Anticipated expiration: 2041-05-12
Also published as: CN112988650A

Abstract

The invention relates to a communication method, a device, a system and a storage medium, wherein the communication method is applied to a programmable logic device, the programmable logic device comprises a virtual serial port system, the virtual serial port system is connected with an external processor and a plurality of external devices, the external processor is used for setting a configuration information table, and the configuration information table comprises channel information and configuration information; the method comprises the following steps: receiving a first control instruction output by the external processor, and switching the communication mode of the virtual serial port system to a polling mode based on the first control instruction; acquiring the configuration information table, and respectively configuring a corresponding channel for each external device based on the channel information; and performing polling access on each external device through a channel corresponding to each external device based on the configuration information. The communication method can realize the self-defined setting of data interaction with the external equipment.

Description

Communication method, device, system and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to a communication method, apparatus, system, and storage medium.

Background

At present, in the transmission process of a communication system, in order to realize transmission of certain communication data, information such as a custom frame format and the like are required, but a serial interface used by a traditional Central Processing Unit (CPU) does not have such a custom function, and cannot perform data transmission with an external device through a custom interface.

Disclosure of Invention

In view of the above, it is necessary to provide a communication method, apparatus, system and storage medium for solving the problem in the prior art that data transmission with an external device through a customized interface is impossible.

In order to achieve the above object, in one aspect, the present invention provides a communication method, including:

a communication method is applied to a programmable logic device, the programmable logic device comprises a virtual serial port system, the virtual serial port system is in communication connection with an external processor and a plurality of external devices, the external processor is used for setting a configuration information table, and the configuration information table comprises channel information and configuration information; the method comprises the following steps:

receiving a first control instruction output by the external processor, and switching the communication mode of the virtual serial port system to a polling mode based on the first control instruction;

acquiring the configuration information table, and respectively configuring a corresponding channel for each external device based on the channel information;

performing polling access on each external device through a channel corresponding to each external device based on the configuration information;

when the communication mode of the virtual serial port system is the polling mode, if a second control instruction output by the external processor is received, switching the communication mode of the virtual serial port system to a random mode based on the second control instruction;

and after the random access is finished, switching the communication mode of the virtual serial port system to the polling mode again based on the first control instruction, and continuing to perform polling access on each external device by the programmable logic device from a breakpoint of the polling access.

In one embodiment, the programmable logic device further comprises a processor for generating first communication data; the switching the communication mode of the virtual serial port system to the polling mode based on the first control instruction comprises:

generating a first mode switching instruction according to the first control instruction;

selecting to receive the first communication data based on the first mode switching instruction;

in the step of performing polling access to each of the external devices through a channel corresponding to each of the external devices, polling access to each of the external devices is performed based on the first communication data.

In one embodiment, the method further comprises:

encoding the first communication data to generate encoded first communication data;

checking the coded first communication data to generate second communication data;

and in the step of performing polling access to each of the external devices through a channel corresponding to each of the external devices, the second communication data is transmitted to the external devices.

In one embodiment, the configuration information includes a communication data format, a coding/decoding mode, or a polling mode.

In one embodiment, the method further comprises:

and when the second control instruction is received, stopping polling access to the external equipment, and storing a breakpoint of the polling access so that the external processor performs random access to the external equipment through the virtual serial port system.

In one embodiment, the switching the communication mode of the virtual serial port system to the random mode based on the second control instruction includes:

generating a second mode switching instruction according to the second control instruction;

and selectively receiving third communication data output by the external processor based on the second mode switching instruction, so that the external processor can randomly access the external device based on the third communication data.

In one embodiment, the method further comprises:

encoding the third communication data to generate encoded third communication data;

and checking the encoded third communication data to generate fourth communication data, so that the fourth communication data is sent to the external equipment in the step of random access of the external equipment by the external processor through the virtual serial port system.

In one embodiment, the method further comprises:

receiving fifth communication data sent by the external equipment, and generating sixth communication data according to the fifth communication data;

storing the sixth communication data for the external processor to read the stored sixth communication data in the random mode.

In one embodiment, the generating sixth communication data from the fifth communication data includes: decoding the fifth communication data to generate sixth communication data;

the method further comprises the following steps:

checking the sixth communication data, and judging whether the sixth communication data is checked successfully;

and if so, executing the step of storing the sixth communication data.

In one embodiment, the step of performing a verification process on the sixth communication data to determine whether the sixth communication data is successfully verified includes:

performing cyclic redundancy check calculation on the sixth communication data to generate a check code;

judging whether the check code is consistent with the original check code;

and if so, determining that the sixth communication data is successfully verified.

A communication device is applied to a programmable logic device, the programmable logic device comprises a virtual serial port system, the virtual serial port system is in communication connection with an external processor and a plurality of external devices, the external processor is used for setting a configuration information table, and the configuration information table comprises channel information and configuration information; the device comprises:

the first control instruction receiving module is used for receiving a first control instruction output by the external processor;

the polling mode switching module is used for switching the communication mode of the virtual serial port system to a polling mode based on the first control instruction;

the configuration information table acquisition module is used for acquiring the configuration information table;

the channel configuration module is used for respectively configuring a corresponding channel for each external device based on the channel information;

the polling access module is used for performing polling access on each external device through a channel corresponding to each external device based on the configuration information;

a random mode switching module, configured to switch the communication mode of the virtual serial port system to a random mode based on a second control instruction output by the external processor if the second control instruction is received when the communication mode of the virtual serial port system is the polling mode;

after the random access is finished, the polling mode switching module switches the communication mode of the virtual serial port system to the polling mode again based on the first control instruction, and the polling access module in the programmable logic device continues to perform polling access on each external device from a breakpoint of the polling access.

In one embodiment, the programmable logic device further comprises a processor for generating first communication data; the polling mode switching module comprises:

the first mode switching instruction generating unit is used for generating a first mode switching instruction according to the first control instruction; and

a first communication data receiving unit configured to select to receive the first communication data based on the first mode switching instruction;

the polling access module performs polling access to each of the external devices based on the first communication data.

In one embodiment, the method further comprises the following steps:

the first communication data coding module is used for coding the first communication data to generate coded first communication data;

the first communication data checking module is used for checking the coded first communication data to generate second communication data;

and the polling access module sends the second communication data to each external device.

In one embodiment, the system further comprises a breakpoint saving module;

when the second control instruction is received, the polling access module stops polling access to the external device, and the breakpoint saving module saves a breakpoint of the polling access so that the external processor performs random access to the external device through the virtual serial port system;

in one embodiment, the random mode switching module includes:

the second mode switching instruction unit is used for generating a second mode switching instruction according to the second control instruction;

a third communication data receiving unit, configured to selectively receive, based on the second mode switching instruction, third communication data output by the external processor, so that the external processor performs random access to the external device based on the third communication data.

In one embodiment, the method further comprises the following steps:

the third communication data coding module is used for coding the third communication data to generate coded third communication data;

and the third communication data checking module is used for checking the coded third communication data to generate fourth communication data so that the external processor can send the fourth communication data to the external equipment when randomly accessing the external equipment through the virtual serial port system.

In one embodiment, the method further comprises the following steps:

a fifth communication data receiving module, configured to receive fifth communication data sent by the external device;

a sixth communication data generation module, configured to generate sixth communication data according to the fifth communication data;

a sixth communication data storage module, configured to store the sixth communication data, so that the external processor reads the stored sixth communication data in the random mode.

In one embodiment, the sixth communication data generation module performs decoding processing on the fifth communication data to generate the sixth communication data;

the device further comprises:

the sixth communication data checking module is used for checking the sixth communication data and judging whether the sixth communication data is checked successfully;

if yes, the sixth communication data storage module stores the sixth communication data.

In one embodiment, the fifth communication data includes an original check code, and the sixth communication data check module includes:

the redundancy check unit is used for performing cyclic redundancy check calculation on the sixth communication data to generate a check code;

the check code judging unit is used for judging whether the check code is consistent with the original check code; and if so, determining that the sixth communication data is successfully verified.

A communication system, comprising: the system comprises an external processor, a programmable logic device and a plurality of external devices, wherein the programmable logic device comprises a virtual serial port system, the virtual serial port system is in communication connection with the external processor and the external devices, and the programmable logic device is used for realizing the steps of any one of the methods.

A storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of the method of any of the above.

The communication method, the device, the system and the storage medium switch the communication mode of the virtual serial port system into the polling mode after receiving a first control instruction output by the external processor, and then perform polling access on the external equipment based on a configuration information table set by the external processor; the self-defining setting of data interaction with the external equipment is realized by setting the configuration information and the channel information corresponding to the external equipment in the configuration information table, so that the FPGA can select a channel and configure a data format according to the channel information and the configuration information; meanwhile, the communication mode is switched by using the control instruction, the current communication mode is switched to the polling mode, one-to-many serial port communication between the FPGA and the external equipment can be realized, each external equipment is accessed through an independent channel, polling access is realized, and data transmission can be efficiently and reliably carried out with the external equipment.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flow chart illustrating a communication method provided in an embodiment of the present application;

FIG. 2 is a flow chart illustrating a portion of a communication method provided in another embodiment of the present application;

fig. 3 is a schematic structural diagram of an external processor, a virtual serial port system, and an external device according to an embodiment of the present disclosure;

fig. 4 is a schematic flow chart of data processing in a random mode according to an embodiment of the present application;

fig. 5 is a schematic flow chart of data processing at the receiving side according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a communication system according to an embodiment of the present application.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments is understood to mean "electrical connection", "communication connection", or the like, if there is a transfer of electrical signals or data between the connected objects.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Referring to fig. 1, fig. 1 is a flowchart illustrating a communication method applied to a programmable logic device according to an embodiment of the present application. The programmable logic device comprises a virtual serial port system. The virtual serial port system is in communication connection with the external processor and the plurality of external devices. For example, the Programmable Logic Device may be a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD). The external processor may be a CPU or a single chip Microcomputer (MCU).

The embodiment is described by taking a programmable logic device as an FPGA as an example, and the communication method provided by the embodiment can be applied to a virtual serial port system on the FPGA, and can realize one-to-many communication connection between the FPGA and an external device, and the communication method includes the following steps:

step S11: and receiving a first control instruction output by the external processor, and switching the communication mode of the virtual serial port system to a polling mode based on the first control instruction.

Specifically, the communication mode of the virtual serial port system is various, for example, the communication mode may include a polling mode, a random mode, and the like. When the communication mode of the virtual serial port system is to be switched from another mode to the polling mode, the external processor outputs a corresponding control command (referred to as a first control command). The virtual serial port system receives the first control instruction and switches the communication mode into the polling mode based on the first control instruction. In polling mode, the FPGA accesses each external device one by one. For example, if there are three external devices, which are denoted as a1-A3, in the polling mode, the FPGA accesses the external device a1 first, accesses the external device a2 after accessing the external device a1, accesses the external device A3 after accessing the external device a2, and accesses the external device a1 again after accessing the external device A3, and the process is repeated so as to realize polling access. Of course, the order in which the FPGA accesses the external devices is not limited to this.

In other examples, the external processor may also output a corresponding second control instruction, a third control instruction, or the like to switch the communication mode of the virtual serial port system to a mode other than the polling mode. For example, the external processor may output a second control instruction to the virtual serial port system, and the virtual serial port system switches its communication mode to the random mode after receiving the second control instruction. In the random mode, the external processor can randomly access any external device through the virtual serial port system, and the external processor can randomly select one external device from all the external devices to access.

Step S12: and acquiring a configuration information table, and respectively configuring corresponding channels for each external device based on the channel information.

Specifically, the configuration information table is configured by the external processor. The configuration information table includes channel information and configuration information. And the virtual serial port system configures a corresponding channel for each external device based on the channel information. The channel may be a virtual data transmission channel. The number of channels may be equal to and one-to-one with the number of external devices. In other examples, the configuration information table may further include information of an external device, and the like. The external processor can set information of the external device to be polled and accessed by the FPGA, corresponding channel information or configuration information in a configuration information table, so that the virtual serial port system can configure a corresponding channel for each external device based on the channel information, and thus, the polling and accessing of the external device are realized through each channel.

In some examples, the channel information may include device addresses, register addresses, start/end flags, or channel numbers, among other information. When the FPGA identifies the start mark, the FPGA starts a polling operation, namely, the corresponding channel is selected according to the address (including the device address and the register address) or the channel number to sequentially poll and access each external device. The FPGA may end the polling operation upon recognizing the end flag. The FPGA communicates with the external equipment through the channel corresponding to the external equipment, so that the FPGA can access the external equipment independently and do not interfere with the external equipment.

And step S13, polling and accessing each external device through the corresponding channel of each external device based on the configuration information.

Specifically, in the polling mode, the FPGA accesses each external device one by one through a channel corresponding to each external device. The access sequence, the access time interval and the like can be matched according to actual requirements.

In some examples, the configuration information may include a communication data format, a coding/decoding manner, a polling manner, or the like. The FPGA can perform data interaction with external equipment according to the customized configuration information in the configuration information table so as to realize customized setting of data transmission. The FPGA can carry out coding/decoding processing on the communication data according to a coding/decoding mode in the current configuration information when the FPGA sends/receives the communication data, and simultaneously can send the communication data to the external equipment in a specific communication data format to realize the access to the external equipment.

In some examples, the external processor may store the configuration information table in a specific memory, and then when the communication mode of the virtual serial port system is switched to the polling mode, the FPGA may read the configuration information table stored in the memory, thereby performing polling access to each external device based on the configuration information table.

In some examples, when the communication mode of the virtual serial port system is the polling mode, if a second control instruction output by the external processor is received, the communication mode of the virtual serial port system is switched to the random mode based on the second control instruction, so that the external processor performs random access to the external device through the virtual serial port system.

In some examples, finally, after the random access of the CPU10 is ended, the first control instruction output by the CPU10 is received, and the communication mode of the virtual serial port system 21 is switched to the polling mode again based on the first control instruction, so that the FPGA20 continues to perform polling access on the external device 30 from the breakpoint of the polling access. The communication method in this embodiment can ensure that the insertion of the random access process of the CPU10 does not disturb the polling access process of the FPGA20, and ensure that the FPGA20 can continue to poll the access task according to the stored breakpoint. It is understood that the FPGA20 may suspend the polling access process after receiving the complete communication data of the current frame, and save the breakpoint of the polling access to prevent the current communication data from being lost.

The communication method switches the communication mode of the virtual serial port system into a polling mode after receiving a first control instruction output by an external processor, and then performs polling access on the external device based on a configuration information table set by the external processor; the self-defining setting of data interaction with the external equipment is realized by setting the configuration information and the channel information corresponding to the external equipment in the configuration information table, so that the FPGA can select a channel and configure a data format according to the channel information and the configuration information; meanwhile, the communication mode is switched by using the control instruction, the current communication mode is switched to the polling mode, one-to-many serial port communication between the FPGA and the external equipment can be realized, each external equipment is accessed through an independent channel, polling access is realized, and data transmission can be efficiently and reliably carried out with the external equipment.

Referring to fig. 2 and fig. 3, fig. 2 is a flowchart of a part of steps of another embodiment of a communication method provided by the present application, and fig. 3 is a schematic structural diagram of an external processor, a virtual serial port system, and an external device provided by the present application, where the method is applied to a virtual serial port system 21 in a programmable logic device. The virtual serial port system 21 is connected to an external processor and a plurality of external devices 30. The external processor is used for setting the configuration information table. In this embodiment, an external processor is taken as a CPU10, and a programmable logic device is taken as an FPGA20 for explanation, and the method includes:

step S21: and receiving a first control instruction output by the external processor.

Step S22: and switching the communication mode of the virtual serial port system to a polling mode based on the first control instruction.

Specifically, the communication mode in the virtual serial port system 21 may include a polling mode and a random mode. When the communication mode is the polling mode, the FPGA20 controls the virtual serial port system 21, and the FPGA20 can perform polling access to the external device 30 through the virtual serial port system 21. When the communication mode is the random mode, the CPU10 controls the virtual serial port system 21, and the CPU10 can perform random access to the external device 30 through the virtual serial port system 21. It will be appreciated that upon initial power-up of the CPU10 and FPGA20, one of the communication modes (i.e., polling mode or random mode) is selected by default. Such as: the random mode is selected by default for data interaction with the external device 30. After power-up, the CPU10 can switch the communication mode by outputting a corresponding control instruction according to the demand. For example: the CPU10 can switch the communication mode to the polling mode by outputting a first control instruction.

In some examples, step S22 includes step S221 and step S222.

Step S221: and generating a first mode switching instruction according to the first control instruction.

In some examples, referring to fig. 3, virtual serial port system 21 may include a first state machine 214. The CPU10 may be communicatively connected to the FPGA20 using a unique handshake mechanism, and the CPU10 may send the first control instruction to the first state machine 214 through the handshake mechanism. The first state machine 214 may process the received first control instruction to generate a first mode switching instruction, so as to switch the communication mode in the virtual serial port system 21.

In some examples, the CPU10 and the FPGA20 are connected by a common configuration bus. For example: local bus, Peripheral Component Interface (PCIe), axi (advanced eXtensible Interface) bus, Serial Peripheral Interface (SPI), and the like. The FPGA20 can be connected to the external device 30 through a serial bus, and the FPGA20 and the external device 30 follow the same interface protocol so that communication data can be normally transmitted.

Step 222: and selecting to receive the first communication data based on the first mode switching instruction.

In particular, FPGA20 may also include a processor (not shown) that may be used to generate the first communication data. When the virtual serial port system receives the first mode switching instruction, the virtual serial port system selects to receive the first communication data generated by the processor, and therefore the communication mode is switched to the polling mode.

In this embodiment, the virtual serial port system performs polling access to each external device based on the first communication data. After the communication mode of the virtual serial port system is switched to the polling mode, the master right of the virtual serial port system 21 is on the FPGA20 side, that is, the source of the communication data that performs data interaction with the external device 30 and is output to the external device 30 is the FPGA 20. At this time, the FPGA20 outputs the first communication data to the external devices 30 one by one in the polling access mode, thereby performing polling access to the plurality of external devices 30.

In some examples, virtual serial port system 21 also includes first memory 211. The first Memory 211 may be a Random Access Memory (RAM), a cloud Memory, or the like. The first memory 211 is used to acquire and store a configuration information table set by the CPU 10. When the communication mode is the polling mode, the FPGA20 may call the configuration information table stored in the first memory 211 to perform polling access to the external device 30.

In some examples, virtual serial port system 21 may also include a selector 212 and a configurator 213. The configurator 213 is configured to forward data information output to the external device 30 or data information input from the external device 30. The selector 212 is configured to receive a first mode switching instruction generated by the first state machine 214. The selector 212 switches the data source of the configurator 213 to the FPGA20 side upon receiving the first mode switching instruction, so that the configurator 213 receives the first communication data generated by the processor within the FPGA20 to perform polling access to the external device 30.

In this embodiment, when the communication mode is the polling mode, the FPGA20 configures a corresponding channel for each external device 30 based on the channel information in the acquired configuration information table, so as to perform polling access on the external device 30 through the corresponding channel. The configuration information table is set by the CPU 10. The configuration information table may include channel information and configuration information, and the configuration information includes a communication data format, an encoding/decoding manner or a polling manner. The CPU10 may set the configuration information and the channel information in the configuration information table to implement customized setting of each channel, and may perform polling access to the corresponding external device 30 through different customized channels and sending customized data formats.

In some examples, the CPU10 and FPGA20 may also implement broadcast functionality for multiple external devices 30. The CPU10 may configure a broadcast channel, such as channel 0, in the configuration information table. Then, when broadcasting needs to be performed on a plurality of external devices 30, the broadcast control word in the configuration information table is set to "1", so that when the FPGA20 calls the configuration information table for polling access, the broadcast control word "1" can be identified, so that other channel information in the configuration information table is copied to channel 0, and then a broadcast message is sent to each external device 30 based on channel 0. Similarly, when the CPU10 makes a random access to the external device 30, the CPU10 may also broadcast all the external devices 30 on the channel 0 basis. It is to be understood that, when the broadcast control word in the configuration information table is set to "0", the broadcast mode is canceled, and the FPGA20 unicasts to each external device 30 based on each channel information and the configuration information in the configuration information table.

In some examples, after the communication mode is switched to the polling mode, the first communication data generated by the processor in the FPGA20 may be further processed and then output to the external device 30. Specifically, step S231 and step S232 may be included.

Step S231: and performing coding processing on the first communication data to generate coded first communication data.

Specifically, the frame structure of the first communication data may include a frame header, a channel number, a frame length, an operation code, frame data, a start flag, and the like. The operation code may represent a frame type, and different frame types may be identified according to the operation code during decoding, thereby performing different decoding operations. The start mark may be represented by letters, numbers or other special symbols.

In some examples, virtual serial port system 21 may also include a modulation module 215. The modulation module 215 specifically includes a second memory 2151 and a second state machine 2152. The second memory 2151 may be a RAM or a First-in-First-out queue (FIFO). The second memory 2151 is used to store first communication data. In the polling mode, the configurator 213 receives the first communication data generated by the processor in the FPGA20, and after recognizing the start flag, the configurator 213 starts the second state machine 2152, so that the second state machine 2152 retrieves the first communication data in the second memory 2151, and then transmits the first communication data bit by bit in units of bytes to the coding table for coding, thereby generating the coded first communication data. The byte unit of the first communication data transmitted to the coding table may be one, two or more, and the specific number may be set according to actual situations.

Step S232: and carrying out verification processing on the coded first communication data to generate second communication data.

In some examples, virtual serial port system 21 also includes a first check module 2153. After generating the encoded first communication data, the second state machine 2152 transfers the encoded first communication data into the first check module 2153 bit by bit in units of bytes. The first check module 2153 performs cyclic redundancy check calculation on the encoded first communication data, generates a check code, and appends the check code to the last field of the encoded first communication data. The second state machine 2152 then frames the encoded first communication data and the check code to generate second communication data, where the frame structure of the second communication data may be as shown in table 1 below, and each byte may be 9 bits long.

TABLE 1

It is to be understood that the length of the operation data in the frame data of the second communication data may be 1-N, and the specific length thereof may be set according to actual situations. N may be an integer, such as equal to 8.

In this embodiment, when polling access is performed on each external device 30 through the corresponding channel of each external device 30 and after the first communication data is processed as described above to generate the second communication data, parallel-to-serial conversion processing may be performed on the second communication data, that is, the second communication data transmitted in parallel is converted into serial data, so that the second communication data can be output to the external device 30 through the serial bus connected to the external device 30 through the virtual serial port system 21. It is understood that the unit of transferring the encoded first communication data into the first check module 2153 may be one, two, or more than two bytes, and the specific number may be set according to actual situations.

In some examples, referring to fig. 4, the communication method further includes step S41.

Step S41: and when the communication mode of the virtual serial port system is the polling mode, if a second control instruction output by the external processor is received, switching the communication mode of the virtual serial port system to a random mode based on the second control instruction so that the external processor can randomly access the external equipment through the virtual serial port system.

In some examples, referring to fig. 4, step S41 includes step S411 and step S412.

Step S411: and generating a second mode switching instruction according to the second control instruction.

Specifically, referring to fig. 3, the CPU10 may send the second control instruction to the first state machine 214 through a handshake mechanism. The first state machine 214 processes the received second control instruction to generate a second mode switching instruction.

Step S412: and selecting and receiving third communication data output by the external processor based on the second mode switching instruction so that the external processor can randomly access the external device based on the third communication data.

Specifically, referring to fig. 3, when receiving the second mode switching instruction, the selector 212 switches the data source of the configurator 213 to the CPU10 side, so that the configurator 213 receives the third communication data generated by the CPU10, and the CPU10 can randomly access the external device 30 based on the third communication data.

In some examples, when the communication mode of the virtual serial port system 21 is the polling mode and the second control instruction is received, so that the polling mode is switched to the random mode, the FPGA20 stops the polling access to the external device 30 and saves the breakpoint of the polling access. Then, the communication mode of the virtual serial port system 21 is switched to the random mode, so that the CPU10 performs random access to the external device 30. In some examples, after the communication mode is switched to the random mode, the third communication data generated by the CPU10 is further processed and then output to the external device 30. Specifically, please refer to steps S42 to S43 in fig. 4, which are similar to steps S231 to S232, and only the processing of the first communication data is changed to the processing of the third communication data, and the detailed process is not repeated herein.

Step S42: and encoding the third communication data to generate encoded third communication data.

Step S43: and checking the encoded third communication data to generate fourth communication data for the external processor to randomly access the external device through the virtual serial port system, and sending the fourth communication data to the external device.

In some examples, the FPGA20 may further include a byte alignment processing module (not shown) for performing byte conversion and alignment on the third communication data output from the CPU10, and may further configure the depth of the memories (including the first memory 211 and the second memory 2151) according to the frame length of the communication data. The byte alignment processing module can respectively buffer one or more pieces of communication data in the direction of receiving the communication data or receiving the communication data, and supports message scheduling control.

In some examples, referring to fig. 5, the communication method may further include step S51 and step S53.

Step S51: and receiving fifth communication data sent by the external equipment, and generating sixth communication data according to the fifth communication data.

Specifically, the FPGA20 receives the fifth communication data transmitted by each external device 30. The fifth communication data transmitted by each external device 30 may be different or the same. The fifth communication data is raw data output by the external device 30, and the data may be data encoded by the external device 30. The FPGA20 may obtain the sixth communication data by decoding the received fifth communication data, that is, the sixth communication data may be data obtained by decoding the fifth communication data.

In some examples, as shown in fig. 3, virtual serial port system 21 also includes demodulation module 216, which specifically includes third state machine 2162. Before the external device 30 sends the fifth communication data to the virtual serial port system 21, the FPGA20 turns on the third state machine 2162 in the virtual serial port system 21, so that the third state machine 2162 receives the fifth communication data input from the serial bus. The third state machine 2162 analyzes the frame data based on the frame header, then performs serial-to-parallel conversion on the fifth communication data, converts the serially inputted fifth communication data into parallel data for transmission, and finally processes the fifth communication data to generate the sixth communication data.

Step S53: and storing the sixth communication data for the external processor to read the stored sixth communication data in the random mode.

Specifically, the FPGA20 may store sixth communication data obtained according to fifth communication data sent by different external devices 30 in different storage units to distinguish which external device 30 each of the sixth communication data belongs to. The memory locations may be identified with different memory addresses. In the random mode, the external processor 10 may obtain the sixth communication data corresponding to the external device 30 according to the memory address of the memory location in the FPGA20 corresponding to the randomly accessed external device 30.

In some examples, as shown in fig. 3, demodulation module 216 may also include a third memory 2161. The third memory 2161 may be, for example, a RAM or a FIFO. The third memory 2161 may be used for storing the sixth communication data, and the external processor may read the sixth communication data stored in the third memory 2161 in the random mode.

In some examples, the generating of the sixth communication data from the fifth communication data in step S51 may include performing a decoding process on the fifth communication data, generating the sixth communication data.

Specifically, referring to fig. 3, the third state machine 2162 receives the fifth communication data sent by the external device 30, and then transmits the fifth communication data to the decoding table bit by bit in units of bytes for decoding processing, thereby generating the sixth communication data. The byte unit of the fifth communication data transmitted to the decoding table may be one, two or more, and the specific number may be set according to actual situations.

In this embodiment, referring to fig. 5, the communication method may further include step S52.

Step S52: and checking the sixth communication data, and judging whether the sixth communication data is checked successfully.

Specifically, the method may include performing cyclic redundancy check calculation on the sixth communication data to generate a check code; judging whether the check code is consistent with the original check code; if so, determining that the sixth communication data is successfully verified.

If the sixth communication data is successfully verified, step S53 is executed.

In some examples, demodulation module 216 may also include a second parity module 2163. The third state machine 2162 transmits the generated sixth communication data to the second check module 2163 bit by bit in byte unit, so as to check the sixth communication data, and determine whether the sixth communication data is checked successfully. The fifth communication data includes an original check code, and cyclic redundancy check calculation may be performed on the sixth communication data generated after decoding to generate a check code, and then it is determined whether the check code is identical to the original check code. And if the first communication data and the second communication data are consistent, determining that the sixth communication data is verified successfully. At this time, it is described that the sixth communication data is valid data, which can be recognized by the virtual serial port system 21, the third state machine 2162 may output the sixth communication data to the third memory 2161, so that the third memory 2161 may store the sixth communication data. If the two are not identical, it is determined that the check on the sixth communication data failed and the transmission may be in error. At this time, the third state machine 2162 may perform an invalid identification on the sixth communication data or directly discard the sixth communication data. It is understood that the byte unit of the sixth communication data transmitted to the second check module 2163 may be one, two or more, and the specific number may be set according to the actual situation.

In some examples, the FPGA20 may send a notification message to the CPU10 to inform the CPU10 that the sixth communication data has been stored in the third memory 2161 every time the sixth communication data successfully checked for one frame is stored in the polling mode, so that the CPU10 retrieves the sixth communication data directly from the third memory 2161 at the time of random access.

The communication method in the above embodiment may further receive fifth communication data sent by the external device 30 when performing polling access or random access with the external device 30, so as to implement data interaction with the external device 30.

When the current communication mode is the polling mode, the third state machine 2162 stores the verified sixth communication data in the third memory 2161, and when the CPU10 wants to perform random access to the external device 30, the sixth communication data stored in the third memory 2161 can be directly read, so that the time and resources occupied by the CPU10 in accessing the external device 30 are saved, and the working efficiency of the CPU10 is improved.

It will be appreciated that the time for the FPGA20 to complete the polling access depends on the number of external devices 30, the amount of communication data that the FPGA20 needs to send and receive, the communication data transfer rate or response speed, and other factors. It is understood that if the current communication mode is the random mode, the third state machine 2162 can directly send the sixth communication data successfully verified to the CPU10 without being stored in the third memory 2161, so as to save the storage space.

In some examples, the number of virtual serial port systems 21 included in the FPGA20 may be one or more. When the number of the virtual serial port system 21 is one, the virtual serial port system 21 may be connected to a plurality of external devices 30, so as to implement one-to-many serial processing on the plurality of external devices 30. When the number of the virtual serial port systems 21 is plural, the plural virtual serial port systems 21 can perform many-to-many parallel processing on the plural external devices 30, and can improve the working efficiency.

In this embodiment, the FPGA20 performs polling access to the plurality of external devices 30 through the virtual serial port system 21, and can implement serial/parallel processing on the plurality of external devices 30 by increasing the number of the virtual serial port systems 21, thereby improving the efficiency of communication with the external devices 30; the CPU10 can set configuration information such as channel information, communication data format, encoding/decoding method, polling method, etc. when accessing the external device 30 through the configuration information table, to realize a function of supporting multi-channel custom data transmission, and can realize a broadcast/unicast function of the CPU10/FPGA20 through setting the configuration information table; in addition, the FPGA20 can also store communication data received through polling access, so that the CPU10 can directly read at the time of random access, saving processing time and resources of the CPU10, and further improving communication efficiency.

It should be understood that, although the steps in the flowcharts of fig. 1, 2, 4 and 5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1, 2, 4, and 5 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least some of the other steps.

The application also provides a communication device. Referring to fig. 6, the communication device 70 is applied to a programmable logic device. The programmable logic device comprises a virtual serial port system. The virtual serial port system is in communication connection with the external processor and the plurality of external devices. The external processor is used for setting a configuration information table, and the configuration information table comprises channel information and configuration information. The communication device 70 includes: a first control instruction receiving module 71, a polling mode switching module 72, a configuration information table obtaining module 73, a channel configuration module 74 and a polling access module 75. The first control instruction receiving module 71 is configured to receive a first control instruction output by an external processor. The polling mode switching module 72 is configured to switch the communication mode of the virtual serial port system to a polling mode based on the first control instruction. The configuration information table obtaining module 73 is used for obtaining the configuration information table. The channel configuration module 74 is configured to configure a corresponding channel for each external device based on the channel information. The polling access module 75 is configured to perform polling access to each external device through a channel corresponding to each external device based on the configuration information.

In some examples, the programmable logic device further comprises a processor to generate first communication data; the polling mode switching module 72 includes a first mode switching instruction generating unit and a first communication data receiving unit. The first mode switching instruction generating unit is used for generating a first mode switching instruction according to the first control instruction. The first communication data receiving unit is used for selecting to receive the first communication data based on the first mode switching instruction. The polling access module 75 performs polling access to each external device based on the first communication data.

In some examples, the communication data verification module is further configured to verify the first communication data. The first communication data encoding module is used for encoding the first communication data to generate encoded first communication data. The first communication data checking module is used for checking the coded first communication data to generate second communication data. The polling access module 75 transmits the second communication data to each external device.

In some examples, the configuration information table further includes configuration information including a communication data format, a coding/decoding manner, or a polling manner.

In some examples, a random mode switching module is also included. And the random mode switching module is used for switching the communication mode of the virtual serial port system to a random mode based on a second control instruction if the second control instruction output by the external processor is received when the communication mode of the virtual serial port system is the polling mode, so that the external processor can randomly access the external equipment through the virtual serial port system.

In some examples, a breakpoint saving module is also included. Upon receiving the second control instruction, the polling access module 75 stops polling access to the external device, and the breakpoint saving module saves the breakpoint of the polling access. After the random access is finished, the first control instruction receiving module 71 receives a first control instruction output by the external processor, the polling mode switching module 72 switches the communication mode of the virtual serial port system to the polling mode again based on the first control instruction, and the polling access module 75 in the programmable logic device continues to perform polling access on each external device from a breakpoint of the polling access.

In some examples, the random mode switching module includes a second mode switching instruction unit and a third communication data receiving unit. The second mode switching instruction unit is used for generating a second mode switching instruction according to the second control instruction. The third communication data receiving unit is used for selectively receiving third communication data output by the external processor based on the second mode switching instruction, so that the external processor can randomly access the external device based on the third communication data.

In some examples, further comprising: a third communication data coding module and a third communication data checking module. The third communication data coding module is used for coding the third communication data to generate coded third communication data. The third communication data check module is used for checking the coded third communication data to generate fourth communication data so that the fourth communication data can be sent to the external equipment when the external processor carries out random access on the external equipment through the virtual serial port system.

In some examples, a fifth communication data receiving module, a sixth communication data generating module, and a sixth communication data storing module are further included. The fifth communication data receiving module is used for receiving fifth communication data sent by the external equipment. The sixth communication data generation module is used for generating sixth communication data according to the fifth communication data; the sixth communication data storage module is used for storing sixth communication data for the external processor to read the stored sixth communication data in the random mode.

In some examples, the sixth communication data generation module performs a decoding process on the fifth communication data, generating sixth communication data. The apparatus further comprises a sixth communication data verification module. And the sixth communication data checking module is used for checking the sixth communication data and judging whether the sixth communication data is checked successfully. And if so, the sixth communication data storage module stores the sixth communication data.

In some examples, the fifth communication data includes an original check code, and the sixth communication data check module includes a redundancy check unit and a check code determination unit. And the redundancy check unit is used for performing cyclic redundancy check calculation on the sixth communication data to generate a check code. The check code judging unit is used for judging whether the check code is consistent with the original check code; if so, determining that the sixth communication data is successfully verified.

For specific limitations of the communication device 70, reference may be made to the above limitations of the communication method, which are not described herein again. The various modules in the communication device 70 described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.

The application also provides a communication system. Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of a communication system according to the present application. The communication system 60 includes an external processor 61, a programmable logic device 62 and a plurality of external devices 63, the programmable logic device 62 includes a virtual serial port system (not shown), the programmable logic device 62 is connected with the external processor 61 and the plurality of external devices 63 (N communication devices 63 are shown in fig. 7) through the virtual serial port system, and the programmable logic device 62 is configured to implement the steps of the communication method in any of the above embodiments. Specifically, the external processor 61 may be a CPU, an MCU or the like, and the programmable logic device 62 may be an FPGA, a CPLD or the like.

The present application also provides a computer-readable storage medium having stored thereon a computer program which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A communication method is characterized in that the communication method is applied to a programmable logic device, the programmable logic device comprises a virtual serial port system, the virtual serial port system is in communication connection with an external processor and a plurality of external devices, the external processor is used for setting a configuration information table, and the configuration information table comprises channel information and configuration information; the method comprises the following steps:

after the random access is finished, the communication mode of the virtual serial port system is switched to the polling mode again based on the first control instruction, and the programmable logic device continues to perform polling access on each external device from the breakpoint of the polling access.

2. The communication method according to claim 1, wherein the programmable logic device further comprises a processor for generating first communication data; the switching the communication mode of the virtual serial port system to the polling mode based on the first control instruction comprises:

3. The communication method of claim 2, wherein the method further comprises:

4. The communication method according to claim 1, wherein the configuration information includes a communication data format, a coding/decoding scheme, or a polling scheme.

5. The communication method of claim 1, wherein the method further comprises:

6. The communication method according to claim 5, wherein the switching the communication mode of the virtual serial port system to a random mode based on the second control instruction comprises:

7. The communication method of claim 6, wherein the method further comprises:

8. The communication method of claim 5, wherein the method further comprises:

9. The communication method according to claim 8, wherein the generating sixth communication data from the fifth communication data comprises: decoding the fifth communication data to generate sixth communication data;

the method further comprises the following steps:

and if so, executing the step of storing the sixth communication data.

10. The communication method according to claim 9, wherein the fifth communication data includes an original check code, and the step of performing the check processing on the sixth communication data and determining whether the check of the sixth communication data is successful includes:

judging whether the check code is consistent with the original check code;

11. A communication device is characterized in that the communication device is applied to a programmable logic device, the programmable logic device comprises a virtual serial port system, the virtual serial port system is in communication connection with an external processor and a plurality of external devices, the external processor is used for setting a configuration information table, and the configuration information table comprises channel information and configuration information; the device comprises:

12. The communication apparatus of claim 11, wherein the programmable logic device further comprises a processor configured to generate first communication data; the polling mode switching module comprises:

13. The communications device of claim 12, further comprising:

14. The communications apparatus as claimed in claim 11, wherein the configuration information includes a communication data format, a coding/decoding scheme or a polling scheme.

15. The communications device of claim 11, further comprising:

when the second control instruction is received, the polling access module stops polling access to the external device, and the breakpoint saving module saves a breakpoint of the polling access, so that the external processor performs random access to the external device through the virtual serial port system.

16. The communications apparatus of claim 15, wherein the random mode switching module comprises:

17. The communications device of claim 16, further comprising:

18. The communications device of claim 11, further comprising:

19. The communications apparatus according to claim 18, wherein the sixth communication data generation module performs decoding processing on the fifth communication data to generate the sixth communication data;

the device further comprises:

20. The communications apparatus as claimed in claim 19, wherein the fifth communications data includes an original check code, and the sixth communications data checking module comprises:

21. A communication system, comprising: an external processor, a programmable logic device and a plurality of external devices, the programmable logic device comprising a virtual serial system communicatively connected to the external processor and the plurality of external devices, the programmable logic device being adapted to implement the steps of the method of any of claims 1 to 10.

22. A storage medium having a computer program stored thereon, the computer program, when being executed by a processor, realizing the steps of the method of any one of claims 1 to 10.